1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/spi/rockchi 4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Rockchip Serial Flash Controller (SFC) 7 title: Rockchip Serial Flash Controller (SFC)
8 8
9 maintainers: 9 maintainers:
10 - Heiko Stuebner <heiko@sntech.de> 10 - Heiko Stuebner <heiko@sntech.de>
11 - Chris Morgan <macromorgan@hotmail.com> 11 - Chris Morgan <macromorgan@hotmail.com>
12 12
13 allOf: 13 allOf:
14 - $ref: spi-controller.yaml# 14 - $ref: spi-controller.yaml#
15 15
16 properties: 16 properties:
17 compatible: 17 compatible:
18 const: rockchip,sfc 18 const: rockchip,sfc
19 description: 19 description:
20 The rockchip sfc controller is a standal 20 The rockchip sfc controller is a standalone IP with version register,
21 and the driver can handle all the featur 21 and the driver can handle all the feature difference inside the IP
22 depending on the version register. 22 depending on the version register.
23 23
24 reg: 24 reg:
25 maxItems: 1 25 maxItems: 1
26 26
27 interrupts: 27 interrupts:
28 maxItems: 1 28 maxItems: 1
29 29
30 clocks: 30 clocks:
31 items: 31 items:
32 - description: Bus Clock 32 - description: Bus Clock
33 - description: Module Clock 33 - description: Module Clock
34 34
35 clock-names: 35 clock-names:
36 items: 36 items:
37 - const: clk_sfc 37 - const: clk_sfc
38 - const: hclk_sfc 38 - const: hclk_sfc
39 39
40 power-domains: 40 power-domains:
41 maxItems: 1 41 maxItems: 1
42 42
43 rockchip,sfc-no-dma: 43 rockchip,sfc-no-dma:
44 description: Disable DMA and utilize FIFO 44 description: Disable DMA and utilize FIFO mode only
45 type: boolean 45 type: boolean
46 46
47 patternProperties: 47 patternProperties:
48 "^flash@[0-3]$": 48 "^flash@[0-3]$":
49 type: object 49 type: object
50 additionalProperties: true <<
51 <<
52 properties: 50 properties:
53 reg: 51 reg:
54 minimum: 0 52 minimum: 0
55 maximum: 3 53 maximum: 3
56 54
57 required: 55 required:
58 - compatible 56 - compatible
59 - reg 57 - reg
60 - interrupts 58 - interrupts
61 - clocks 59 - clocks
62 - clock-names 60 - clock-names
63 61
64 unevaluatedProperties: false 62 unevaluatedProperties: false
65 63
66 examples: 64 examples:
67 - | 65 - |
68 #include <dt-bindings/clock/px30-cru.h> 66 #include <dt-bindings/clock/px30-cru.h>
69 #include <dt-bindings/interrupt-controller 67 #include <dt-bindings/interrupt-controller/arm-gic.h>
70 #include <dt-bindings/power/px30-power.h> 68 #include <dt-bindings/power/px30-power.h>
71 69
72 sfc: spi@ff3a0000 { 70 sfc: spi@ff3a0000 {
73 compatible = "rockchip,sfc"; 71 compatible = "rockchip,sfc";
74 reg = <0xff3a0000 0x4000>; 72 reg = <0xff3a0000 0x4000>;
75 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVE 73 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
76 clocks = <&cru SCLK_SFC>, <&cru HCLK_S 74 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
77 clock-names = "clk_sfc", "hclk_sfc"; 75 clock-names = "clk_sfc", "hclk_sfc";
78 pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus 76 pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>;
79 pinctrl-names = "default"; 77 pinctrl-names = "default";
80 power-domains = <&power PX30_PD_MMC_NA 78 power-domains = <&power PX30_PD_MMC_NAND>;
81 #address-cells = <1>; 79 #address-cells = <1>;
82 #size-cells = <0>; 80 #size-cells = <0>;
83 81
84 flash@0 { 82 flash@0 {
85 compatible = "jedec,spi-nor"; 83 compatible = "jedec,spi-nor";
86 reg = <0>; 84 reg = <0>;
87 spi-max-frequency = <108000000>; 85 spi-max-frequency = <108000000>;
88 spi-rx-bus-width = <2>; 86 spi-rx-bus-width = <2>;
89 spi-tx-bus-width = <2>; 87 spi-tx-bus-width = <2>;
90 }; 88 };
91 }; 89 };
92 90
93 ... 91 ...
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