1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/spmi/qcom,x 4 $id: http://devicetree.org/schemas/spmi/qcom,x1e80100-spmi-pmic-arb.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm X1E80100 SPMI Controller (PMIC 7 title: Qualcomm X1E80100 SPMI Controller (PMIC Arbiter v7)
8 8
9 maintainers: 9 maintainers:
10 - Stephen Boyd <sboyd@kernel.org> 10 - Stephen Boyd <sboyd@kernel.org>
11 11
12 description: | 12 description: |
13 The X1E80100 SPMI PMIC Arbiter implements HW 13 The X1E80100 SPMI PMIC Arbiter implements HW version 7 and it's an SPMI
14 controller with wrapping arbitration logic t 14 controller with wrapping arbitration logic to allow for multiple on-chip
15 devices to control up to 2 SPMI separate bus 15 devices to control up to 2 SPMI separate buses.
16 16
17 The PMIC Arbiter can also act as an interrup 17 The PMIC Arbiter can also act as an interrupt controller, providing interrupts
18 to slave devices. 18 to slave devices.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 const: qcom,x1e80100-spmi-pmic-arb 22 const: qcom,x1e80100-spmi-pmic-arb
23 23
24 reg: 24 reg:
25 items: 25 items:
26 - description: core registers 26 - description: core registers
27 - description: tx-channel per virtual sl 27 - description: tx-channel per virtual slave registers
28 - description: rx-channel (called observ 28 - description: rx-channel (called observer) per virtual slave registers
29 29
30 reg-names: 30 reg-names:
31 items: 31 items:
32 - const: core 32 - const: core
33 - const: chnls 33 - const: chnls
34 - const: obsrvr 34 - const: obsrvr
35 35
36 ranges: true 36 ranges: true
37 37
38 '#address-cells': 38 '#address-cells':
39 const: 2 39 const: 2
40 40
41 '#size-cells': 41 '#size-cells':
42 const: 2 42 const: 2
43 43
44 qcom,ee: 44 qcom,ee:
45 $ref: /schemas/types.yaml#/definitions/uin 45 $ref: /schemas/types.yaml#/definitions/uint32
46 minimum: 0 46 minimum: 0
47 maximum: 5 47 maximum: 5
48 description: > 48 description: >
49 indicates the active Execution Environme 49 indicates the active Execution Environment identifier
50 50
51 qcom,channel: 51 qcom,channel:
52 $ref: /schemas/types.yaml#/definitions/uin 52 $ref: /schemas/types.yaml#/definitions/uint32
53 minimum: 0 53 minimum: 0
54 maximum: 5 54 maximum: 5
55 description: > 55 description: >
56 which of the PMIC Arb provided channels 56 which of the PMIC Arb provided channels to use for accesses
57 57
58 patternProperties: 58 patternProperties:
59 "^spmi@[a-f0-9]+$": 59 "^spmi@[a-f0-9]+$":
60 type: object 60 type: object
61 $ref: /schemas/spmi/spmi.yaml 61 $ref: /schemas/spmi/spmi.yaml
62 unevaluatedProperties: false 62 unevaluatedProperties: false
63 63
64 properties: 64 properties:
65 reg: 65 reg:
66 items: 66 items:
67 - description: configuration registe 67 - description: configuration registers
68 - description: interrupt controller 68 - description: interrupt controller registers
69 69
70 reg-names: 70 reg-names:
71 items: 71 items:
72 - const: cnfg 72 - const: cnfg
73 - const: intr 73 - const: intr
74 74
75 interrupts: 75 interrupts:
76 maxItems: 1 76 maxItems: 1
77 77
78 interrupt-names: 78 interrupt-names:
79 const: periph_irq 79 const: periph_irq
80 80
81 interrupt-controller: true 81 interrupt-controller: true
82 82
83 '#interrupt-cells': 83 '#interrupt-cells':
84 const: 4 84 const: 4
85 description: | 85 description: |
86 cell 1: slave ID for the requested i 86 cell 1: slave ID for the requested interrupt (0-15)
87 cell 2: peripheral ID for requested 87 cell 2: peripheral ID for requested interrupt (0-255)
88 cell 3: the requested peripheral int 88 cell 3: the requested peripheral interrupt (0-7)
89 cell 4: interrupt flags indicating l 89 cell 4: interrupt flags indicating level-sense information,
90 as defined in dt-bindings/in 90 as defined in dt-bindings/interrupt-controller/irq.h
91 91
92 required: 92 required:
93 - compatible 93 - compatible
94 - reg-names 94 - reg-names
95 - qcom,ee 95 - qcom,ee
96 - qcom,channel 96 - qcom,channel
97 97
98 additionalProperties: false 98 additionalProperties: false
99 99
100 examples: 100 examples:
101 - | 101 - |
102 #include <dt-bindings/interrupt-controller 102 #include <dt-bindings/interrupt-controller/arm-gic.h>
103 103
104 soc { 104 soc {
105 #address-cells = <2>; 105 #address-cells = <2>;
106 #size-cells = <2>; 106 #size-cells = <2>;
107 107
108 spmi: arbiter@c400000 { 108 spmi: arbiter@c400000 {
109 compatible = "qcom,x1e80100-spmi-pmic- 109 compatible = "qcom,x1e80100-spmi-pmic-arb";
110 reg = <0 0x0c400000 0 0x3000>, 110 reg = <0 0x0c400000 0 0x3000>,
111 <0 0x0c500000 0 0x4000000>, 111 <0 0x0c500000 0 0x4000000>,
112 <0 0x0c440000 0 0x80000>; 112 <0 0x0c440000 0 0x80000>;
113 reg-names = "core", "chnls", "obsrvr"; 113 reg-names = "core", "chnls", "obsrvr";
114 114
115 qcom,ee = <0>; 115 qcom,ee = <0>;
116 qcom,channel = <0>; 116 qcom,channel = <0>;
117 117
118 #address-cells = <2>; 118 #address-cells = <2>;
119 #size-cells = <2>; 119 #size-cells = <2>;
120 ranges; 120 ranges;
121 121
122 spmi_bus0: spmi@c42d000 { 122 spmi_bus0: spmi@c42d000 {
123 reg = <0 0x0c42d000 0 0x4000>, 123 reg = <0 0x0c42d000 0 0x4000>,
124 <0 0x0c4c0000 0 0x10000>; 124 <0 0x0c4c0000 0 0x10000>;
125 reg-names = "cnfg", "intr"; 125 reg-names = "cnfg", "intr";
126 126
127 interrupt-names = "periph_irq"; 127 interrupt-names = "periph_irq";
128 interrupts-extended = <&pdc 1 IRQ_TY 128 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-controller; 129 interrupt-controller;
130 #interrupt-cells = <4>; 130 #interrupt-cells = <4>;
131 131
132 #address-cells = <2>; 132 #address-cells = <2>;
133 #size-cells = <0>; 133 #size-cells = <0>;
134 }; 134 };
135 }; 135 };
136 }; 136 };
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