1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvi
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: NVIDIA Tegra124 SOCTHERM Thermal Manage
8
9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12
13 description: The SOCTHERM IP block contains th
14 polled or interrupt-based thermal monitoring
15 on temperature trip points, and handling ext
16 It is also used to manage emergency shutdown
17
18 properties:
19 compatible:
20 enum:
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
24
25 reg:
26 maxItems: 2
27
28 reg-names:
29 maxItems: 2
30
31 interrupts:
32 items:
33 - description: module interrupt
34 - description: EDP interrupt
35
36 interrupt-names:
37 items:
38 - const: thermal
39 - const: edp
40
41 clocks:
42 items:
43 - description: thermal sensor clock
44 - description: module clock
45
46 clock-names:
47 items:
48 - const: tsensor
49 - const: soctherm
50
51 resets:
52 items:
53 - description: module reset
54
55 reset-names:
56 items:
57 - const: soctherm
58
59 "#thermal-sensor-cells":
60 const: 1
61
62 throttle-cfgs:
63 $ref: thermal-cooling-devices.yaml
64 description: A sub-node which is a contain
65 hardware throttle events. These events c
66 Throttle event sub-nodes must be named a
67 unevaluatedProperties: false
68 patternProperties:
69 "^(light|heavy|oc1)$":
70 type: object
71 additionalProperties: false
72
73 properties:
74 "#cooling-cells":
75 const: 2
76
77 nvidia,priority:
78 $ref: /schemas/types.yaml#/definit
79 minimum: 1
80 maximum: 100
81 description: Each throttles has it
82 SW need to set priorities for va
83 can select the final throttle se
84 higher priority, In general, hig
85 target frequency. SW needs to en
86 alarms are given higher priority
87 race if priority of two vectors
88
89 nvidia,cpu-throt-percent:
90 description: This property is for
91 throttling depth of pulse skippe
92 throttling.
93 minimum: 0
94 maximum: 100
95
96 nvidia,cpu-throt-level:
97 $ref: /schemas/types.yaml#/definit
98 description: This property is only
99 of pulse skippers, which used to
100 indicates cpu clock throttling d
101 programmed.
102 enum:
103 # none (TEGRA_SOCTHERM_THROT_LEV
104 - 0
105 # low (TEGRA_SOCTHERM_THROT_LEVE
106 - 1
107 # medium (TEGRA_SOCTHERM_THROT_L
108 - 2
109 # high (TEGRA_SOCTHERM_THROT_LEV
110 - 3
111
112 nvidia,gpu-throt-level:
113 $ref: /schemas/types.yaml#/definit
114 description: This property is for
115 level of pulse skippers, which u
116 frequencies. It indicates gpu cl
117 programmed to any of the followi
118 throttling percentage.
119 enum:
120 # none (0%, TEGRA_SOCTHERM_THROT
121 - 0
122 # low (50%, TEGRA_SOCTHERM_THROT
123 - 1
124 # medium (75%, TEGRA_SOCTHERM_TH
125 - 2
126 # high (85%, TEGRA_SOCTHERM_THRO
127 - 3
128
129 # optional
130 # Tegra210 specific and valid only f
131 nvidia,count-threshold:
132 $ref: /schemas/types.yaml#/definit
133 description: Specifies the number
134 for triggering an interrupt. Int
135 property is missing. A value of
136 alarm.
137
138 nvidia,polarity-active-low:
139 $ref: /schemas/types.yaml#/definit
140 description: Configures the polari
141 present, this means assert low,
142
143 nvidia,alarm-filter:
144 $ref: /schemas/types.yaml#/definit
145 description: Number of clocks to f
146 expires (which means the OC even
147 time), the counter is cleared an
148 default: 0
149
150 nvidia,throttle-period-us:
151 description: Specifies the number
152 throttling is engaged after the
153 default: 0
154
155 # optional
156 nvidia,thermtrips:
157 $ref: /schemas/types.yaml#/definitions/uin
158 description: |
159 When present, this property specifies th
160 SOCTHERM hardware will assert the therma
161 Management IC, which can be configured t
162 It is an array of pairs where each pair
163 by a temperature in milli Celcius. In th
164 critical trip point will be used for the
165
166 Note:
167 - the "critical" type trip points will b
168 which the SOCTHERM hardware will asser
169 "nvidia,thermtrips" property is missin
170 is present, the breach of a critical t
171 the thermal framework to implement sof
172
173 - the "hot" type trip points will be set
174 throttle temperature. Once the temper
175 higher than it, it will trigger the HW
176 items:
177 items:
178 - description: sensor ID
179 oneOf:
180 - description: CPU sensor
181 const: 0
182 - description: MEM sensor
183 const: 1
184 - description: GPU sensor
185 const: 2
186 - description: PLLX sensor
187 const: 3
188 - description: temperature threshold (
189
190 required:
191 - compatible
192 - reg
193 - reg-names
194 - interrupts
195 - interrupt-names
196 - clocks
197 - clock-names
198 - resets
199 - reset-names
200
201 allOf:
202 - $ref: thermal-sensor.yaml
203 - if:
204 properties:
205 compatible:
206 contains:
207 enum:
208 - nvidia,tegra124-soctherm
209 - nvidia,tegra210-soctherm
210 then:
211 properties:
212 reg:
213 items:
214 - description: SOCTHERM register s
215 - description: clock and reset con
216
217 reg-names:
218 items:
219 - const: soctherm-reg
220 - const: car-reg
221
222 else:
223 properties:
224 reg:
225 items:
226 - description: SOCTHERM register s
227 - description: CCROC registers
228
229 reg-names:
230 items:
231 - const: soctherm-reg
232 - const: ccroc-reg
233
234 additionalProperties: false
235
236 examples:
237 - |
238 #include <dt-bindings/clock/tegra124-car.h
239 #include <dt-bindings/interrupt-controller
240 #include <dt-bindings/thermal/tegra124-soc
241
242 soctherm@700e2000 {
243 compatible = "nvidia,tegra124-soctherm
244 reg = <0x700e2000 0x600>, /* SOC_THERM
245 <0x60006000 0x400>; /* CAR reg_b
246 reg-names = "soctherm-reg", "car-reg";
247 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVE
248 <GIC_SPI 51 IRQ_TYPE_LEVE
249 interrupt-names = "thermal", "edp";
250 clocks = <&tegra_car TEGRA124_CLK_TSEN
251 <&tegra_car TEGRA124_CLK_SOC_
252 clock-names = "tsensor", "soctherm";
253 resets = <&tegra_car 78>;
254 reset-names = "soctherm";
255
256 #thermal-sensor-cells = <1>;
257
258 nvidia,thermtrips = <TEGRA124_SOCTHERM
259 <TEGRA124_SOCTHERM
260
261 throttle-cfgs {
262 /*
263 * When the "heavy" cooling device
264 * the HW will skip cpu clock's pu
265 * skip gpu clock's pulse in 85% l
266 */
267 heavy {
268 nvidia,priority = <100>;
269 nvidia,cpu-throt-percent = <85
270 nvidia,gpu-throt-level = <TEGR
271
272 #cooling-cells = <2>;
273 };
274
275 /*
276 * When the "light" cooling device
277 * the HW will skip cpu clock's pu
278 * skip gpu clock's pulse in 50% l
279 */
280 light {
281 nvidia,priority = <80>;
282 nvidia,cpu-throt-percent = <50
283 nvidia,gpu-throt-level = <TEGR
284
285 #cooling-cells = <2>;
286 };
287
288 /*
289 * If these two devices are trigge
290 * arbiter will select the highest
291 * settings to skip cpu pulse.
292 */
293
294 oc1 {
295 nvidia,priority = <50>;
296 nvidia,polarity-active-low;
297 nvidia,count-threshold = <100>
298 nvidia,alarm-filter = <5100000
299 nvidia,throttle-period-us = <0
300 nvidia,cpu-throt-percent = <75
301 nvidia,gpu-throt-level = <TEGR
302 };
303 };
304 };
305
306 # referring to Tegra132's "reg", "reg-names"
307 - |
308 thermal-sensor@700e2000 {
309 compatible = "nvidia,tegra132-soctherm
310 reg = <0x700e2000 0x600>, /* SOC_THERM
311 <0x70040000 0x200>; /* CCROC reg
312 reg-names = "soctherm-reg", "ccroc-reg
313 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVE
314 <GIC_SPI 51 IRQ_TYPE_LEVE
315 interrupt-names = "thermal", "edp";
316 clocks = <&tegra_car TEGRA124_CLK_TSEN
317 <&tegra_car TEGRA124_CLK_SOC_
318 clock-names = "tsensor", "soctherm";
319 resets = <&tegra_car 78>;
320 reset-names = "soctherm";
321 #thermal-sensor-cells = <1>;
322
323 throttle-cfgs {
324 /*
325 * When the "heavy" cooling device
326 * the HW will skip cpu clock's pu
327 */
328 heavy {
329 nvidia,priority = <100>;
330 nvidia,cpu-throt-level = <TEGR
331
332 #cooling-cells = <2>;
333 };
334
335 /*
336 * When the "light" cooling device
337 * the HW will skip cpu clock's pu
338 */
339 light {
340 nvidia,priority = <80>;
341 nvidia,cpu-throt-level = <TEGR
342
343 #cooling-cells = <2>;
344 };
345
346 /*
347 * If these two devices are trigge
348 * arbiter will select the highest
349 * settings to skip cpu pulse.
350 */
351 };
352 };
353
354 # referring to thermal sensors
355 - |
356 thermal-zones {
357 cpu-thermal {
358 polling-delay-passive = <1000>;
359 polling-delay = <1000>;
360
361 thermal-sensors = <&soctherm TEGRA
362
363 trips {
364 cpu_shutdown_trip: shutdown-tr
365 temperature = <102500>;
366 hysteresis = <1000>;
367 type = "critical";
368 };
369
370 cpu_throttle_trip: throttle-tr
371 temperature = <100000>;
372 hysteresis = <1000>;
373 type = "hot";
374 };
375 };
376
377 cooling-maps {
378 map0 {
379 trip = <&cpu_throttle_trip
380 cooling-device = <&throttl
381 };
382 };
383 };
384 };
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