1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/thermal/nvi 4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: NVIDIA Tegra124 SOCTHERM Thermal Manage 7 title: NVIDIA Tegra124 SOCTHERM Thermal Management System
8 8
9 maintainers: 9 maintainers:
10 - Thierry Reding <thierry.reding@gmail.com> 10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com> 11 - Jon Hunter <jonathanh@nvidia.com>
12 12
13 description: The SOCTHERM IP block contains th 13 description: The SOCTHERM IP block contains thermal sensors, support for
14 polled or interrupt-based thermal monitoring 14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
15 on temperature trip points, and handling ext 15 on temperature trip points, and handling external overcurrent notifications.
16 It is also used to manage emergency shutdown 16 It is also used to manage emergency shutdown in an overheating situation.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 enum: 20 enum:
21 - nvidia,tegra124-soctherm 21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm 22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm 23 - nvidia,tegra210-soctherm
24 24
25 reg: 25 reg:
26 maxItems: 2 26 maxItems: 2
27 27
28 reg-names: 28 reg-names:
29 maxItems: 2 29 maxItems: 2
30 30
31 interrupts: 31 interrupts:
32 items: 32 items:
33 - description: module interrupt 33 - description: module interrupt
34 - description: EDP interrupt 34 - description: EDP interrupt
35 35
36 interrupt-names: 36 interrupt-names:
37 items: 37 items:
38 - const: thermal 38 - const: thermal
39 - const: edp 39 - const: edp
40 40
41 clocks: 41 clocks:
42 items: 42 items:
43 - description: thermal sensor clock 43 - description: thermal sensor clock
44 - description: module clock 44 - description: module clock
45 45
46 clock-names: 46 clock-names:
47 items: 47 items:
48 - const: tsensor 48 - const: tsensor
49 - const: soctherm 49 - const: soctherm
50 50
51 resets: 51 resets:
52 items: 52 items:
53 - description: module reset 53 - description: module reset
54 54
55 reset-names: 55 reset-names:
56 items: 56 items:
57 - const: soctherm 57 - const: soctherm
58 58
59 "#thermal-sensor-cells": 59 "#thermal-sensor-cells":
60 const: 1 60 const: 1
61 61
62 throttle-cfgs: 62 throttle-cfgs:
63 $ref: thermal-cooling-devices.yaml 63 $ref: thermal-cooling-devices.yaml
64 description: A sub-node which is a contain 64 description: A sub-node which is a container of configuration for each
65 hardware throttle events. These events c 65 hardware throttle events. These events can be set as cooling devices.
66 Throttle event sub-nodes must be named a 66 Throttle event sub-nodes must be named as "light" or "heavy".
67 unevaluatedProperties: false 67 unevaluatedProperties: false
68 patternProperties: 68 patternProperties:
69 "^(light|heavy|oc1)$": 69 "^(light|heavy|oc1)$":
70 type: object 70 type: object
71 additionalProperties: false <<
72 <<
73 properties: 71 properties:
74 "#cooling-cells": <<
75 const: 2 <<
76 <<
77 nvidia,priority: 72 nvidia,priority:
78 $ref: /schemas/types.yaml#/definit 73 $ref: /schemas/types.yaml#/definitions/uint32
79 minimum: 1 74 minimum: 1
80 maximum: 100 75 maximum: 100
81 description: Each throttles has it 76 description: Each throttles has its own throttle settings, so the
82 SW need to set priorities for va 77 SW need to set priorities for various throttle, the HW arbiter
83 can select the final throttle se 78 can select the final throttle settings. Bigger value indicates
84 higher priority, In general, hig 79 higher priority, In general, higher priority translates to lower
85 target frequency. SW needs to en 80 target frequency. SW needs to ensure that critical thermal
86 alarms are given higher priority 81 alarms are given higher priority, and ensure that there is no
87 race if priority of two vectors 82 race if priority of two vectors is set to the same value.
88 83
89 nvidia,cpu-throt-percent: 84 nvidia,cpu-throt-percent:
90 description: This property is for 85 description: This property is for Tegra124 and Tegra210. It is the
91 throttling depth of pulse skippe 86 throttling depth of pulse skippers, it's the percentage
92 throttling. 87 throttling.
93 minimum: 0 88 minimum: 0
94 maximum: 100 89 maximum: 100
95 90
96 nvidia,cpu-throt-level: 91 nvidia,cpu-throt-level:
97 $ref: /schemas/types.yaml#/definit 92 $ref: /schemas/types.yaml#/definitions/uint32
98 description: This property is only 93 description: This property is only for Tegra132, it is the level
99 of pulse skippers, which used to 94 of pulse skippers, which used to throttle clock frequencies. It
100 indicates cpu clock throttling d 95 indicates cpu clock throttling depth, and the depth can be
101 programmed. 96 programmed.
102 enum: 97 enum:
103 # none (TEGRA_SOCTHERM_THROT_LEV 98 # none (TEGRA_SOCTHERM_THROT_LEVEL_NONE)
104 - 0 99 - 0
105 # low (TEGRA_SOCTHERM_THROT_LEVE 100 # low (TEGRA_SOCTHERM_THROT_LEVEL_LOW)
106 - 1 101 - 1
107 # medium (TEGRA_SOCTHERM_THROT_L 102 # medium (TEGRA_SOCTHERM_THROT_LEVEL_MED)
108 - 2 103 - 2
109 # high (TEGRA_SOCTHERM_THROT_LEV 104 # high (TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
110 - 3 105 - 3
111 106
112 nvidia,gpu-throt-level: 107 nvidia,gpu-throt-level:
113 $ref: /schemas/types.yaml#/definit 108 $ref: /schemas/types.yaml#/definitions/uint32
114 description: This property is for 109 description: This property is for Tegra124 and Tegra210. It is the
115 level of pulse skippers, which u 110 level of pulse skippers, which used to throttle clock
116 frequencies. It indicates gpu cl 111 frequencies. It indicates gpu clock throttling depth and can be
117 programmed to any of the followi 112 programmed to any of the following values which represent a
118 throttling percentage. 113 throttling percentage.
119 enum: 114 enum:
120 # none (0%, TEGRA_SOCTHERM_THROT 115 # none (0%, TEGRA_SOCTHERM_THROT_LEVEL_NONE)
121 - 0 116 - 0
122 # low (50%, TEGRA_SOCTHERM_THROT 117 # low (50%, TEGRA_SOCTHERM_THROT_LEVEL_LOW)
123 - 1 118 - 1
124 # medium (75%, TEGRA_SOCTHERM_TH 119 # medium (75%, TEGRA_SOCTHERM_THROT_LEVEL_MED)
125 - 2 120 - 2
126 # high (85%, TEGRA_SOCTHERM_THRO 121 # high (85%, TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
127 - 3 122 - 3
128 123
129 # optional 124 # optional
130 # Tegra210 specific and valid only f 125 # Tegra210 specific and valid only for OCx throttle events
131 nvidia,count-threshold: 126 nvidia,count-threshold:
132 $ref: /schemas/types.yaml#/definit 127 $ref: /schemas/types.yaml#/definitions/uint32
133 description: Specifies the number 128 description: Specifies the number of OC events that are required
134 for triggering an interrupt. Int 129 for triggering an interrupt. Interrupts are not triggered if the
135 property is missing. A value of 130 property is missing. A value of 0 will interrupt on every OC
136 alarm. 131 alarm.
137 132
138 nvidia,polarity-active-low: 133 nvidia,polarity-active-low:
139 $ref: /schemas/types.yaml#/definit 134 $ref: /schemas/types.yaml#/definitions/flag
140 description: Configures the polari 135 description: Configures the polarity of the OC alaram signal. If
141 present, this means assert low, 136 present, this means assert low, otherwise assert high.
142 137
143 nvidia,alarm-filter: 138 nvidia,alarm-filter:
144 $ref: /schemas/types.yaml#/definit 139 $ref: /schemas/types.yaml#/definitions/uint32
145 description: Number of clocks to f 140 description: Number of clocks to filter event. When the filter
146 expires (which means the OC even 141 expires (which means the OC event has not occurred for a long
147 time), the counter is cleared an 142 time), the counter is cleared and filter is rearmed.
148 default: 0 143 default: 0
149 144
150 nvidia,throttle-period-us: 145 nvidia,throttle-period-us:
151 description: Specifies the number 146 description: Specifies the number of microseconds for which
152 throttling is engaged after the 147 throttling is engaged after the OC event is deasserted.
153 default: 0 148 default: 0
154 149
155 # optional 150 # optional
156 nvidia,thermtrips: 151 nvidia,thermtrips:
157 $ref: /schemas/types.yaml#/definitions/uin 152 $ref: /schemas/types.yaml#/definitions/uint32-matrix
158 description: | 153 description: |
159 When present, this property specifies th 154 When present, this property specifies the temperature at which the
160 SOCTHERM hardware will assert the therma 155 SOCTHERM hardware will assert the thermal trigger signal to the Power
161 Management IC, which can be configured t 156 Management IC, which can be configured to reset or shutdown the device.
162 It is an array of pairs where each pair 157 It is an array of pairs where each pair represents a tsensor ID followed
163 by a temperature in milli Celcius. In th 158 by a temperature in milli Celcius. In the absence of this property the
164 critical trip point will be used for the 159 critical trip point will be used for thermtrip temperature.
165 160
166 Note: 161 Note:
167 - the "critical" type trip points will b 162 - the "critical" type trip points will be used to set the temperature at
168 which the SOCTHERM hardware will asser 163 which the SOCTHERM hardware will assert a thermal trigger if the
169 "nvidia,thermtrips" property is missin 164 "nvidia,thermtrips" property is missing. When the thermtrips property
170 is present, the breach of a critical t 165 is present, the breach of a critical trip point is reported back to
171 the thermal framework to implement sof 166 the thermal framework to implement software shutdown.
172 167
173 - the "hot" type trip points will be set 168 - the "hot" type trip points will be set to SOCTHERM hardware as the
174 throttle temperature. Once the temper 169 throttle temperature. Once the temperature of this thermal zone is
175 higher than it, it will trigger the HW 170 higher than it, it will trigger the HW throttle event.
176 items: 171 items:
177 items: 172 items:
178 - description: sensor ID 173 - description: sensor ID
179 oneOf: 174 oneOf:
180 - description: CPU sensor 175 - description: CPU sensor
181 const: 0 176 const: 0
182 - description: MEM sensor 177 - description: MEM sensor
183 const: 1 178 const: 1
184 - description: GPU sensor 179 - description: GPU sensor
185 const: 2 180 const: 2
186 - description: PLLX sensor 181 - description: PLLX sensor
187 const: 3 182 const: 3
188 - description: temperature threshold ( 183 - description: temperature threshold (in millidegree Celsius)
189 184
190 required: 185 required:
191 - compatible 186 - compatible
192 - reg 187 - reg
193 - reg-names 188 - reg-names
194 - interrupts 189 - interrupts
195 - interrupt-names 190 - interrupt-names
196 - clocks 191 - clocks
197 - clock-names 192 - clock-names
198 - resets 193 - resets
199 - reset-names 194 - reset-names
>> 195 - "#thermal-sensor-cells"
200 196
201 allOf: 197 allOf:
202 - $ref: thermal-sensor.yaml 198 - $ref: thermal-sensor.yaml
203 - if: 199 - if:
204 properties: 200 properties:
205 compatible: 201 compatible:
206 contains: 202 contains:
207 enum: 203 enum:
208 - nvidia,tegra124-soctherm 204 - nvidia,tegra124-soctherm
209 - nvidia,tegra210-soctherm 205 - nvidia,tegra210-soctherm
210 then: 206 then:
211 properties: 207 properties:
212 reg: 208 reg:
213 items: 209 items:
214 - description: SOCTHERM register s 210 - description: SOCTHERM register set
215 - description: clock and reset con 211 - description: clock and reset controller registers
216 212
217 reg-names: 213 reg-names:
218 items: 214 items:
219 - const: soctherm-reg 215 - const: soctherm-reg
220 - const: car-reg 216 - const: car-reg
221 217
222 else: 218 else:
223 properties: 219 properties:
224 reg: 220 reg:
225 items: 221 items:
226 - description: SOCTHERM register s 222 - description: SOCTHERM register set
227 - description: CCROC registers 223 - description: CCROC registers
228 224
229 reg-names: 225 reg-names:
230 items: 226 items:
231 - const: soctherm-reg 227 - const: soctherm-reg
232 - const: ccroc-reg 228 - const: ccroc-reg
233 229
234 additionalProperties: false 230 additionalProperties: false
235 231
236 examples: 232 examples:
237 - | 233 - |
238 #include <dt-bindings/clock/tegra124-car.h 234 #include <dt-bindings/clock/tegra124-car.h>
239 #include <dt-bindings/interrupt-controller 235 #include <dt-bindings/interrupt-controller/arm-gic.h>
240 #include <dt-bindings/thermal/tegra124-soc 236 #include <dt-bindings/thermal/tegra124-soctherm.h>
241 237
242 soctherm@700e2000 { 238 soctherm@700e2000 {
243 compatible = "nvidia,tegra124-soctherm 239 compatible = "nvidia,tegra124-soctherm";
244 reg = <0x700e2000 0x600>, /* SOC_THERM 240 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
245 <0x60006000 0x400>; /* CAR reg_b 241 <0x60006000 0x400>; /* CAR reg_base */
246 reg-names = "soctherm-reg", "car-reg"; 242 reg-names = "soctherm-reg", "car-reg";
247 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVE 243 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 51 IRQ_TYPE_LEVE 244 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
249 interrupt-names = "thermal", "edp"; 245 interrupt-names = "thermal", "edp";
250 clocks = <&tegra_car TEGRA124_CLK_TSEN 246 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
251 <&tegra_car TEGRA124_CLK_SOC_ 247 <&tegra_car TEGRA124_CLK_SOC_THERM>;
252 clock-names = "tsensor", "soctherm"; 248 clock-names = "tsensor", "soctherm";
253 resets = <&tegra_car 78>; 249 resets = <&tegra_car 78>;
254 reset-names = "soctherm"; 250 reset-names = "soctherm";
255 251
256 #thermal-sensor-cells = <1>; 252 #thermal-sensor-cells = <1>;
257 253
258 nvidia,thermtrips = <TEGRA124_SOCTHERM 254 nvidia,thermtrips = <TEGRA124_SOCTHERM_SENSOR_CPU 102500>,
259 <TEGRA124_SOCTHERM 255 <TEGRA124_SOCTHERM_SENSOR_GPU 103000>;
260 256
261 throttle-cfgs { 257 throttle-cfgs {
262 /* 258 /*
263 * When the "heavy" cooling device 259 * When the "heavy" cooling device triggered,
264 * the HW will skip cpu clock's pu 260 * the HW will skip cpu clock's pulse in 85% depth,
265 * skip gpu clock's pulse in 85% l 261 * skip gpu clock's pulse in 85% level
266 */ 262 */
267 heavy { 263 heavy {
268 nvidia,priority = <100>; 264 nvidia,priority = <100>;
269 nvidia,cpu-throt-percent = <85 265 nvidia,cpu-throt-percent = <85>;
270 nvidia,gpu-throt-level = <TEGR 266 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
271 267
272 #cooling-cells = <2>; 268 #cooling-cells = <2>;
273 }; 269 };
274 270
275 /* 271 /*
276 * When the "light" cooling device 272 * When the "light" cooling device triggered,
277 * the HW will skip cpu clock's pu 273 * the HW will skip cpu clock's pulse in 50% depth,
278 * skip gpu clock's pulse in 50% l 274 * skip gpu clock's pulse in 50% level
279 */ 275 */
280 light { 276 light {
281 nvidia,priority = <80>; 277 nvidia,priority = <80>;
282 nvidia,cpu-throt-percent = <50 278 nvidia,cpu-throt-percent = <50>;
283 nvidia,gpu-throt-level = <TEGR 279 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_LOW>;
284 280
285 #cooling-cells = <2>; 281 #cooling-cells = <2>;
286 }; 282 };
287 283
288 /* 284 /*
289 * If these two devices are trigge 285 * If these two devices are triggered in same time, the HW throttle
290 * arbiter will select the highest 286 * arbiter will select the highest priority as the final throttle
291 * settings to skip cpu pulse. 287 * settings to skip cpu pulse.
292 */ 288 */
293 289
294 oc1 { 290 oc1 {
295 nvidia,priority = <50>; 291 nvidia,priority = <50>;
296 nvidia,polarity-active-low; 292 nvidia,polarity-active-low;
297 nvidia,count-threshold = <100> 293 nvidia,count-threshold = <100>;
298 nvidia,alarm-filter = <5100000 294 nvidia,alarm-filter = <5100000>;
299 nvidia,throttle-period-us = <0 295 nvidia,throttle-period-us = <0>;
300 nvidia,cpu-throt-percent = <75 296 nvidia,cpu-throt-percent = <75>;
301 nvidia,gpu-throt-level = <TEGR 297 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
302 }; 298 };
303 }; 299 };
304 }; 300 };
305 301
306 # referring to Tegra132's "reg", "reg-names" 302 # referring to Tegra132's "reg", "reg-names" and "throttle-cfgs"
307 - | 303 - |
308 thermal-sensor@700e2000 { 304 thermal-sensor@700e2000 {
309 compatible = "nvidia,tegra132-soctherm 305 compatible = "nvidia,tegra132-soctherm";
310 reg = <0x700e2000 0x600>, /* SOC_THERM 306 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */
311 <0x70040000 0x200>; /* CCROC reg 307 <0x70040000 0x200>; /* CCROC reg_base */
312 reg-names = "soctherm-reg", "ccroc-reg 308 reg-names = "soctherm-reg", "ccroc-reg";
313 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVE 309 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 51 IRQ_TYPE_LEVE 310 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
315 interrupt-names = "thermal", "edp"; 311 interrupt-names = "thermal", "edp";
316 clocks = <&tegra_car TEGRA124_CLK_TSEN 312 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
317 <&tegra_car TEGRA124_CLK_SOC_ 313 <&tegra_car TEGRA124_CLK_SOC_THERM>;
318 clock-names = "tsensor", "soctherm"; 314 clock-names = "tsensor", "soctherm";
319 resets = <&tegra_car 78>; 315 resets = <&tegra_car 78>;
320 reset-names = "soctherm"; 316 reset-names = "soctherm";
321 #thermal-sensor-cells = <1>; 317 #thermal-sensor-cells = <1>;
322 318
323 throttle-cfgs { 319 throttle-cfgs {
324 /* 320 /*
325 * When the "heavy" cooling device 321 * When the "heavy" cooling device triggered,
326 * the HW will skip cpu clock's pu 322 * the HW will skip cpu clock's pulse in HIGH level
327 */ 323 */
328 heavy { 324 heavy {
329 nvidia,priority = <100>; 325 nvidia,priority = <100>;
330 nvidia,cpu-throt-level = <TEGR 326 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
331 327
332 #cooling-cells = <2>; 328 #cooling-cells = <2>;
333 }; 329 };
334 330
335 /* 331 /*
336 * When the "light" cooling device 332 * When the "light" cooling device triggered,
337 * the HW will skip cpu clock's pu 333 * the HW will skip cpu clock's pulse in MED level
338 */ 334 */
339 light { 335 light {
340 nvidia,priority = <80>; 336 nvidia,priority = <80>;
341 nvidia,cpu-throt-level = <TEGR 337 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
342 338
343 #cooling-cells = <2>; 339 #cooling-cells = <2>;
344 }; 340 };
345 341
346 /* 342 /*
347 * If these two devices are trigge 343 * If these two devices are triggered in same time, the HW throttle
348 * arbiter will select the highest 344 * arbiter will select the highest priority as the final throttle
349 * settings to skip cpu pulse. 345 * settings to skip cpu pulse.
350 */ 346 */
351 }; 347 };
352 }; 348 };
353 349
354 # referring to thermal sensors 350 # referring to thermal sensors
355 - | 351 - |
356 thermal-zones { 352 thermal-zones {
357 cpu-thermal { 353 cpu-thermal {
358 polling-delay-passive = <1000>; 354 polling-delay-passive = <1000>;
359 polling-delay = <1000>; 355 polling-delay = <1000>;
360 356
361 thermal-sensors = <&soctherm TEGRA 357 thermal-sensors = <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
362 358
363 trips { 359 trips {
364 cpu_shutdown_trip: shutdown-tr 360 cpu_shutdown_trip: shutdown-trip {
365 temperature = <102500>; 361 temperature = <102500>;
366 hysteresis = <1000>; 362 hysteresis = <1000>;
367 type = "critical"; 363 type = "critical";
368 }; 364 };
369 365
370 cpu_throttle_trip: throttle-tr 366 cpu_throttle_trip: throttle-trip {
371 temperature = <100000>; 367 temperature = <100000>;
372 hysteresis = <1000>; 368 hysteresis = <1000>;
373 type = "hot"; 369 type = "hot";
374 }; 370 };
375 }; 371 };
376 372
377 cooling-maps { 373 cooling-maps {
378 map0 { 374 map0 {
379 trip = <&cpu_throttle_trip 375 trip = <&cpu_throttle_trip>;
380 cooling-device = <&throttl 376 cooling-device = <&throttle_heavy 1 1>;
381 }; 377 };
382 }; 378 };
383 }; 379 };
384 }; 380 };
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