1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright 2021 Linaro Ltd. 2 # Copyright 2021 Linaro Ltd.
3 %YAML 1.2 3 %YAML 1.2
4 --- 4 ---
5 $id: http://devicetree.org/schemas/thermal/qco 5 $id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
6 $schema: http://devicetree.org/meta-schemas/co 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 7
8 title: Qualcomm Limits Management Hardware(LMh 8 title: Qualcomm Limits Management Hardware(LMh)
9 9
10 maintainers: 10 maintainers:
11 - Thara Gopinath <thara.gopinath@gmail.com> 11 - Thara Gopinath <thara.gopinath@gmail.com>
12 12
13 description: 13 description:
14 Limits Management Hardware(LMh) is a hardwar 14 Limits Management Hardware(LMh) is a hardware infrastructure on some
15 Qualcomm SoCs that can enforce temperature a 15 Qualcomm SoCs that can enforce temperature and current limits as
16 programmed by software for certain IPs like 16 programmed by software for certain IPs like CPU.
17 17
18 properties: 18 properties:
19 compatible: 19 compatible:
20 oneOf: 20 oneOf:
21 - enum: 21 - enum:
22 - qcom,sc8180x-lmh 22 - qcom,sc8180x-lmh
23 - qcom,sdm845-lmh 23 - qcom,sdm845-lmh
24 - qcom,sm8150-lmh 24 - qcom,sm8150-lmh
25 - items: 25 - items:
26 - const: qcom,qcm2290-lmh 26 - const: qcom,qcm2290-lmh
27 - const: qcom,sm8150-lmh 27 - const: qcom,sm8150-lmh
28 28
29 reg: 29 reg:
30 items: 30 items:
31 - description: core registers 31 - description: core registers
32 32
33 interrupts: 33 interrupts:
34 maxItems: 1 34 maxItems: 1
35 35
36 '#interrupt-cells': 36 '#interrupt-cells':
37 const: 1 37 const: 1
38 38
39 interrupt-controller: true 39 interrupt-controller: true
40 40
41 cpus: 41 cpus:
42 description: 42 description:
43 phandle of the first cpu in the LMh clus 43 phandle of the first cpu in the LMh cluster
44 maxItems: 1 44 maxItems: 1
45 45
46 qcom,lmh-temp-arm-millicelsius: 46 qcom,lmh-temp-arm-millicelsius:
47 description: 47 description:
48 An integer expressing temperature thresh 48 An integer expressing temperature threshold at which the LMh thermal
49 FSM is engaged. 49 FSM is engaged.
50 50
51 qcom,lmh-temp-low-millicelsius: 51 qcom,lmh-temp-low-millicelsius:
52 description: 52 description:
53 An integer expressing temperature thresh 53 An integer expressing temperature threshold at which the state machine
54 will attempt to remove frequency throttl 54 will attempt to remove frequency throttling.
55 55
56 qcom,lmh-temp-high-millicelsius: 56 qcom,lmh-temp-high-millicelsius:
57 description: 57 description:
58 An integer expressing temperature thresh 58 An integer expressing temperature threshold at which the state machine
59 will attempt to throttle the frequency. 59 will attempt to throttle the frequency.
60 60
61 required: 61 required:
62 - compatible 62 - compatible
63 - reg 63 - reg
64 - interrupts 64 - interrupts
65 - '#interrupt-cells' 65 - '#interrupt-cells'
66 - interrupt-controller 66 - interrupt-controller
67 - cpus 67 - cpus
68 - qcom,lmh-temp-arm-millicelsius 68 - qcom,lmh-temp-arm-millicelsius
69 - qcom,lmh-temp-low-millicelsius 69 - qcom,lmh-temp-low-millicelsius
70 - qcom,lmh-temp-high-millicelsius 70 - qcom,lmh-temp-high-millicelsius
71 71
72 additionalProperties: false 72 additionalProperties: false
73 73
74 examples: 74 examples:
75 - | 75 - |
76 #include <dt-bindings/interrupt-controller 76 #include <dt-bindings/interrupt-controller/arm-gic.h>
77 77
78 lmh@17d70800 { 78 lmh@17d70800 {
79 compatible = "qcom,sdm845-lmh"; 79 compatible = "qcom,sdm845-lmh";
80 reg = <0x17d70800 0x400>; 80 reg = <0x17d70800 0x400>;
81 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_ 81 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
82 cpus = <&CPU4>; 82 cpus = <&CPU4>;
83 qcom,lmh-temp-arm-millicelsius = <65000> 83 qcom,lmh-temp-arm-millicelsius = <65000>;
84 qcom,lmh-temp-low-millicelsius = <94500> 84 qcom,lmh-temp-low-millicelsius = <94500>;
85 qcom,lmh-temp-high-millicelsius = <95000 85 qcom,lmh-temp-high-millicelsius = <95000>;
86 interrupt-controller; 86 interrupt-controller;
87 #interrupt-cells = <1>; 87 #interrupt-cells = <1>;
88 }; 88 };
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