1 # SPDX-License-Identifier: GPL-2.0 1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/timer/arm,s 4 $id: http://devicetree.org/schemas/timer/arm,sp804.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: ARM sp804 Dual Timers 7 title: ARM sp804 Dual Timers
8 8
9 maintainers: 9 maintainers:
10 - Haojian Zhuang <haojian.zhuang@linaro.org> 10 - Haojian Zhuang <haojian.zhuang@linaro.org>
11 11
12 description: |+ 12 description: |+
13 The Arm SP804 IP implements two independent 13 The Arm SP804 IP implements two independent timers, configurable for
14 16 or 32 bit operation and capable of runnin 14 16 or 32 bit operation and capable of running in one-shot, periodic, or
15 free-running mode. The input clock is shared 15 free-running mode. The input clock is shared, but can be gated and prescaled
16 independently for each timer. 16 independently for each timer.
17 17
18 There is a viriant of Arm SP804: Hisilicon 6 18 There is a viriant of Arm SP804: Hisilicon 64-bit SP804 timer. Some Hisilicon
19 SoCs, such as Hi1212, should use the dedicat 19 SoCs, such as Hi1212, should use the dedicated compatible: "hisilicon,sp804".
20 20
21 # Need a custom select here or 'arm,primecell' 21 # Need a custom select here or 'arm,primecell' will match on lots of nodes
22 select: 22 select:
23 properties: 23 properties:
24 compatible: 24 compatible:
25 contains: 25 contains:
26 enum: !! 26 oneOf:
27 - arm,sp804 !! 27 - const: arm,sp804
28 - hisilicon,sp804 !! 28 - const: hisilicon,sp804
29 required: 29 required:
30 - compatible 30 - compatible
31 31
32 properties: 32 properties:
33 compatible: 33 compatible:
34 items: 34 items:
35 - enum: 35 - enum:
36 - arm,sp804 36 - arm,sp804
37 - hisilicon,sp804 37 - hisilicon,sp804
38 - const: arm,primecell 38 - const: arm,primecell
39 39
40 interrupts: 40 interrupts:
41 description: | 41 description: |
42 If two interrupts are listed, those are 42 If two interrupts are listed, those are the interrupts for timer
43 1 and 2, respectively. If there is only 43 1 and 2, respectively. If there is only a single interrupt, it is
44 either a combined interrupt or the sole 44 either a combined interrupt or the sole interrupt of one timer, as
45 specified by the "arm,sp804-has-irq" pro 45 specified by the "arm,sp804-has-irq" property.
46 minItems: 1 46 minItems: 1
47 maxItems: 2 47 maxItems: 2
48 48
49 reg: 49 reg:
50 description: The physical base address of 50 description: The physical base address of the SP804 IP.
51 maxItems: 1 51 maxItems: 1
52 52
53 clocks: 53 clocks:
54 description: | 54 description: |
55 Clocks driving the dual timer hardware. 55 Clocks driving the dual timer hardware. This list should
56 be 1 or 3 clocks. With 3 clocks, the ord 56 be 1 or 3 clocks. With 3 clocks, the order is timer0 clock, timer1
57 clock, apb_pclk. A single clock can also 57 clock, apb_pclk. A single clock can also be specified if the same
58 clock is used for all clock inputs. 58 clock is used for all clock inputs.
59 oneOf: 59 oneOf:
60 - items: 60 - items:
61 - description: clock for timer 1 61 - description: clock for timer 1
62 - description: clock for timer 2 62 - description: clock for timer 2
63 - description: bus clock 63 - description: bus clock
64 - items: 64 - items:
65 - description: unified clock for bot 65 - description: unified clock for both timers and the bus
66 66
67 clock-names: true 67 clock-names: true
68 # The original binding did not specify any 68 # The original binding did not specify any clock names, and there is no
69 # consistent naming used in the existing D 69 # consistent naming used in the existing DTs. The primecell binding
70 # requires the "apb_pclk" name, so we need 70 # requires the "apb_pclk" name, so we need this property.
71 # Use "timer0clk", "timer1clk", "apb_pclk" 71 # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.
72 72
73 arm,sp804-has-irq: 73 arm,sp804-has-irq:
74 description: If only one interrupt line is 74 description: If only one interrupt line is connected to the interrupt
75 controller, this property specifies whic 75 controller, this property specifies which timer is connected to this
76 line. 76 line.
77 $ref: /schemas/types.yaml#/definitions/uin 77 $ref: /schemas/types.yaml#/definitions/uint32
78 minimum: 1 78 minimum: 1
79 maximum: 2 79 maximum: 2
80 80
81 required: 81 required:
82 - compatible 82 - compatible
83 - interrupts 83 - interrupts
84 - reg 84 - reg
85 - clocks 85 - clocks
86 86
87 additionalProperties: false 87 additionalProperties: false
88 88
89 examples: 89 examples:
90 - | 90 - |
91 timer0: timer@fc800000 { 91 timer0: timer@fc800000 {
92 compatible = "arm,sp804", "arm,primece 92 compatible = "arm,sp804", "arm,primecell";
93 reg = <0xfc800000 0x1000>; 93 reg = <0xfc800000 0x1000>;
94 interrupts = <0 0 4>, <0 1 4>; 94 interrupts = <0 0 4>, <0 1 4>;
95 clocks = <&timclk1>, <&timclk2>, <&pcl 95 clocks = <&timclk1>, <&timclk2>, <&pclk>;
96 clock-names = "timer1", "timer2", "apb 96 clock-names = "timer1", "timer2", "apb_pclk";
97 }; 97 };
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