1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/timer/cdns, 4 $id: http://devicetree.org/schemas/timer/cdns,ttc.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Cadence TTC - Triple Timer Counter 7 title: Cadence TTC - Triple Timer Counter
8 8
9 maintainers: 9 maintainers:
10 - Michal Simek <michal.simek@amd.com> 10 - Michal Simek <michal.simek@amd.com>
11 11
12 properties: 12 properties:
13 compatible: 13 compatible:
14 const: cdns,ttc 14 const: cdns,ttc
15 15
16 reg: 16 reg:
17 maxItems: 1 17 maxItems: 1
18 18
19 interrupts: 19 interrupts:
20 maxItems: 3 20 maxItems: 3
21 description: | 21 description: |
22 A list of 3 interrupts; one per timer ch 22 A list of 3 interrupts; one per timer channel.
23 23
24 clocks: 24 clocks:
25 maxItems: 1 25 maxItems: 1
26 26
27 power-domains: 27 power-domains:
28 maxItems: 1 28 maxItems: 1
29 29
30 timer-width: 30 timer-width:
31 $ref: /schemas/types.yaml#/definitions/uin 31 $ref: /schemas/types.yaml#/definitions/uint32
32 description: | 32 description: |
33 Bit width of the timer, necessary if not 33 Bit width of the timer, necessary if not 16.
34 34
35 "#pwm-cells": 35 "#pwm-cells":
36 const: 3 36 const: 3
37 37
38 required: 38 required:
39 - compatible 39 - compatible
40 - reg 40 - reg
41 - clocks 41 - clocks
42 42
43 allOf: 43 allOf:
44 - if: 44 - if:
45 not: 45 not:
46 required: 46 required:
47 - "#pwm-cells" 47 - "#pwm-cells"
48 then: 48 then:
49 required: 49 required:
50 - interrupts 50 - interrupts
51 51
52 additionalProperties: false 52 additionalProperties: false
53 53
54 examples: 54 examples:
55 - | 55 - |
56 ttc0: ttc0@f8001000 { 56 ttc0: ttc0@f8001000 {
57 interrupt-parent = <&intc>; 57 interrupt-parent = <&intc>;
58 interrupts = <0 10 4>, <0 11 4>, <0 12 58 interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
59 compatible = "cdns,ttc"; 59 compatible = "cdns,ttc";
60 reg = <0xF8001000 0x1000>; 60 reg = <0xF8001000 0x1000>;
61 clocks = <&cpu_clk 3>; 61 clocks = <&cpu_clk 3>;
62 timer-width = <32>; 62 timer-width = <32>;
63 }; 63 };
64 64
65 - | 65 - |
66 pwm: pwm@f8002000 { 66 pwm: pwm@f8002000 {
67 compatible = "cdns,ttc"; 67 compatible = "cdns,ttc";
68 reg = <0xf8002000 0x1000>; 68 reg = <0xf8002000 0x1000>;
69 clocks = <&cpu_clk 3>; 69 clocks = <&cpu_clk 3>;
70 timer-width = <32>; 70 timer-width = <32>;
71 #pwm-cells = <3>; 71 #pwm-cells = <3>;
72 }; 72 };
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