1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/timer/renes 4 $id: http://devicetree.org/schemas/timer/renesas,ostm.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Renesas OS Timer (OSTM) 7 title: Renesas OS Timer (OSTM)
8 8
9 maintainers: 9 maintainers:
10 - Chris Brandt <chris.brandt@renesas.com> 10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be 11 - Geert Uytterhoeven <geert+renesas@glider.be>
12 12
13 description: 13 description:
14 The OSTM is a multi-channel 32-bit timer/cou 14 The OSTM is a multi-channel 32-bit timer/counter with fixed clock source that
15 can operate in either interval count down ti 15 can operate in either interval count down timer or free-running compare match
16 mode. 16 mode.
17 17
18 Channels are independent from each other. 18 Channels are independent from each other.
19 19
20 properties: 20 properties:
21 compatible: 21 compatible:
22 items: 22 items:
23 - enum: 23 - enum:
24 - renesas,r7s72100-ostm # RZ/A1H 24 - renesas,r7s72100-ostm # RZ/A1H
25 - renesas,r7s9210-ostm # RZ/A2M 25 - renesas,r7s9210-ostm # RZ/A2M
26 - renesas,r9a07g043-ostm # RZ/G2UL a 26 - renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five
27 - renesas,r9a07g044-ostm # RZ/G2{L,L 27 - renesas,r9a07g044-ostm # RZ/G2{L,LC}
28 - renesas,r9a07g054-ostm # RZ/V2L 28 - renesas,r9a07g054-ostm # RZ/V2L
29 - renesas,r9a09g057-ostm # RZ/V2H(P) 29 - renesas,r9a09g057-ostm # RZ/V2H(P)
30 - const: renesas,ostm # Generic 30 - const: renesas,ostm # Generic
31 31
32 reg: 32 reg:
33 maxItems: 1 33 maxItems: 1
34 34
35 interrupts: 35 interrupts:
36 maxItems: 1 36 maxItems: 1
37 37
38 clocks: 38 clocks:
39 maxItems: 1 39 maxItems: 1
40 40
41 power-domains: 41 power-domains:
42 maxItems: 1 42 maxItems: 1
43 43
44 resets: 44 resets:
45 maxItems: 1 45 maxItems: 1
46 46
47 required: 47 required:
48 - compatible 48 - compatible
49 - reg 49 - reg
50 - interrupts 50 - interrupts
51 - clocks 51 - clocks
52 - power-domains 52 - power-domains
53 53
54 if: 54 if:
55 properties: 55 properties:
56 compatible: 56 compatible:
57 contains: 57 contains:
58 enum: 58 enum:
59 - renesas,r9a07g043-ostm 59 - renesas,r9a07g043-ostm
60 - renesas,r9a07g044-ostm 60 - renesas,r9a07g044-ostm
61 - renesas,r9a07g054-ostm 61 - renesas,r9a07g054-ostm
62 - renesas,r9a09g057-ostm 62 - renesas,r9a09g057-ostm
63 then: 63 then:
64 required: 64 required:
65 - resets 65 - resets
66 66
67 additionalProperties: false 67 additionalProperties: false
68 68
69 examples: 69 examples:
70 - | 70 - |
71 #include <dt-bindings/clock/r7s72100-clock 71 #include <dt-bindings/clock/r7s72100-clock.h>
72 #include <dt-bindings/interrupt-controller 72 #include <dt-bindings/interrupt-controller/arm-gic.h>
73 ostm0: timer@fcfec000 { 73 ostm0: timer@fcfec000 {
74 compatible = "renesas,r7s72100-ost 74 compatible = "renesas,r7s72100-ostm", "renesas,ostm";
75 reg = <0xfcfec000 0x30>; 75 reg = <0xfcfec000 0x30>;
76 interrupts = <GIC_SPI 102 IRQ_TYPE 76 interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
77 clocks = <&mstp5_clks R7S72100_CLK 77 clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
78 power-domains = <&cpg_clocks>; 78 power-domains = <&cpg_clocks>;
79 }; 79 };
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