1 # SPDX-License-Identifier: (GPL-2.0-only OR BS
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/timer/sifiv
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: SiFive Core Local Interruptor
8
9 maintainers:
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
12
13 description:
14 SiFive (and other RISC-V) SOCs include an im
15 Core Local Interruptor (CLINT) for M-mode ti
16 interrupts. It directly connects to the time
17 lines of various HARTs (or CPUs) so RISC-V p
18 interrupt controller is the parent interrupt
19 The clock frequency of CLINT is specified vi
20 property of "/cpus" DT node. The "timebase-f
21 described in Documentation/devicetree/bindin
22
23 T-Head C906/C910 CPU cores include an implem
24 their implementation lacks a memory-mapped M
25 compatible with SiFive ones.
26
27 properties:
28 compatible:
29 oneOf:
30 - items:
31 - enum:
32 - canaan,k210-clint # Cana
33 - sifive,fu540-c000-clint # SiFi
34 - starfive,jh7100-clint # Star
35 - starfive,jh7110-clint # Star
36 - starfive,jh8100-clint # Star
37 - const: sifive,clint0 # SiFi
38 - items:
39 - enum:
40 - allwinner,sun20i-d1-clint
41 - sophgo,cv1800b-clint
42 - sophgo,cv1812h-clint
43 - sophgo,sg2002-clint
44 - thead,th1520-clint
45 - const: thead,c900-clint
46 - items:
47 - const: sifive,clint0
48 - const: riscv,clint0
49 deprecated: true
50 description: For the QEMU virt machine
51
52 description:
53 Should be "<vendor>,<chip>-clint", follo
54 when compatible with a SiFive CLINT. Pl
55 sifive-blocks-ip-versioning.txt for deta
56
57 reg:
58 maxItems: 1
59
60 interrupts-extended:
61 minItems: 1
62 maxItems: 4095
63
64 additionalProperties: false
65
66 required:
67 - compatible
68 - reg
69 - interrupts-extended
70
71 examples:
72 - |
73 timer@2000000 {
74 compatible = "sifive,fu540-c000-clint",
75 interrupts-extended = <&cpu1intc 3>, <&c
76 <&cpu2intc 3>, <&c
77 <&cpu3intc 3>, <&c
78 <&cpu4intc 3>, <&c
79 reg = <0x2000000 0x10000>;
80 };
81 ...
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