1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/timer/sifiv 4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: SiFive Core Local Interruptor 7 title: SiFive Core Local Interruptor
8 8
9 maintainers: 9 maintainers:
10 - Palmer Dabbelt <palmer@dabbelt.com> 10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com> 11 - Anup Patel <anup.patel@wdc.com>
12 12
13 description: 13 description:
14 SiFive (and other RISC-V) SOCs include an im 14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode ti 15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the time 16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V p 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18 interrupt controller is the parent interrupt 18 interrupt controller is the parent interrupt controller for CLINT device.
19 The clock frequency of CLINT is specified vi 19 The clock frequency of CLINT is specified via "timebase-frequency" DT
20 property of "/cpus" DT node. The "timebase-f 20 property of "/cpus" DT node. The "timebase-frequency" DT property is
21 described in Documentation/devicetree/bindin 21 described in Documentation/devicetree/bindings/riscv/cpus.yaml
22 22
23 T-Head C906/C910 CPU cores include an implem <<
24 their implementation lacks a memory-mapped M <<
25 compatible with SiFive ones. <<
26 <<
27 properties: 23 properties:
28 compatible: 24 compatible:
29 oneOf: 25 oneOf:
30 - items: 26 - items:
31 - enum: 27 - enum:
32 - canaan,k210-clint # Cana !! 28 - sifive,fu540-c000-clint
33 - sifive,fu540-c000-clint # SiFi !! 29 - starfive,jh7100-clint
34 - starfive,jh7100-clint # Star !! 30 - canaan,k210-clint
35 - starfive,jh7110-clint # Star !! 31 - const: sifive,clint0
36 - starfive,jh8100-clint # Star <<
37 - const: sifive,clint0 # SiFi <<
38 - items: <<
39 - enum: <<
40 - allwinner,sun20i-d1-clint <<
41 - sophgo,cv1800b-clint <<
42 - sophgo,cv1812h-clint <<
43 - sophgo,sg2002-clint <<
44 - thead,th1520-clint <<
45 - const: thead,c900-clint <<
46 - items: 32 - items:
47 - const: sifive,clint0 33 - const: sifive,clint0
48 - const: riscv,clint0 34 - const: riscv,clint0
49 deprecated: true 35 deprecated: true
50 description: For the QEMU virt machine 36 description: For the QEMU virt machine only
51 37
52 description: 38 description:
53 Should be "<vendor>,<chip>-clint", follo !! 39 Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
54 when compatible with a SiFive CLINT. Pl !! 40 Supported compatible strings are -
55 sifive-blocks-ip-versioning.txt for deta !! 41 "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
>> 42 onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
>> 43 CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
>> 44 "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
>> 45 integration tweaks.
>> 46 Please refer to sifive-blocks-ip-versioning.txt for details
56 47
57 reg: 48 reg:
58 maxItems: 1 49 maxItems: 1
59 50
60 interrupts-extended: 51 interrupts-extended:
61 minItems: 1 52 minItems: 1
62 maxItems: 4095 53 maxItems: 4095
63 54
64 additionalProperties: false 55 additionalProperties: false
65 56
66 required: 57 required:
67 - compatible 58 - compatible
68 - reg 59 - reg
69 - interrupts-extended 60 - interrupts-extended
70 61
71 examples: 62 examples:
72 - | 63 - |
73 timer@2000000 { 64 timer@2000000 {
74 compatible = "sifive,fu540-c000-clint", 65 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
75 interrupts-extended = <&cpu1intc 3>, <&c 66 interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
76 <&cpu2intc 3>, <&c 67 <&cpu2intc 3>, <&cpu2intc 7>,
77 <&cpu3intc 3>, <&c 68 <&cpu3intc 3>, <&cpu3intc 7>,
78 <&cpu4intc 3>, <&c 69 <&cpu4intc 3>, <&cpu4intc 7>;
79 reg = <0x2000000 0x10000>; 70 reg = <0x2000000 0x10000>;
80 }; 71 };
81 ... 72 ...
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