1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/timer/sifiv 4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: SiFive Core Local Interruptor 7 title: SiFive Core Local Interruptor
8 8
9 maintainers: 9 maintainers:
10 - Palmer Dabbelt <palmer@dabbelt.com> 10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com> 11 - Anup Patel <anup.patel@wdc.com>
12 12
13 description: 13 description:
14 SiFive (and other RISC-V) SOCs include an im 14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode ti 15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the time 16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V p 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18 interrupt controller is the parent interrupt 18 interrupt controller is the parent interrupt controller for CLINT device.
19 The clock frequency of CLINT is specified vi 19 The clock frequency of CLINT is specified via "timebase-frequency" DT
20 property of "/cpus" DT node. The "timebase-f 20 property of "/cpus" DT node. The "timebase-frequency" DT property is
21 described in Documentation/devicetree/bindin 21 described in Documentation/devicetree/bindings/riscv/cpus.yaml
22 22
23 T-Head C906/C910 CPU cores include an implem 23 T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24 their implementation lacks a memory-mapped M 24 their implementation lacks a memory-mapped MTIME register, thus not
25 compatible with SiFive ones. 25 compatible with SiFive ones.
26 26
27 properties: 27 properties:
28 compatible: 28 compatible:
29 oneOf: 29 oneOf:
30 - items: 30 - items:
31 - enum: 31 - enum:
32 - canaan,k210-clint # Cana 32 - canaan,k210-clint # Canaan Kendryte K210
33 - sifive,fu540-c000-clint # SiFi 33 - sifive,fu540-c000-clint # SiFive FU540
34 - starfive,jh7100-clint # Star 34 - starfive,jh7100-clint # StarFive JH7100
35 - starfive,jh7110-clint # Star 35 - starfive,jh7110-clint # StarFive JH7110
36 - starfive,jh8100-clint # Star <<
37 - const: sifive,clint0 # SiFi 36 - const: sifive,clint0 # SiFive CLINT v0 IP block
38 - items: 37 - items:
39 - enum: 38 - enum:
40 - allwinner,sun20i-d1-clint 39 - allwinner,sun20i-d1-clint
41 - sophgo,cv1800b-clint <<
42 - sophgo,cv1812h-clint <<
43 - sophgo,sg2002-clint <<
44 - thead,th1520-clint 40 - thead,th1520-clint
45 - const: thead,c900-clint 41 - const: thead,c900-clint
46 - items: 42 - items:
47 - const: sifive,clint0 43 - const: sifive,clint0
48 - const: riscv,clint0 44 - const: riscv,clint0
49 deprecated: true 45 deprecated: true
50 description: For the QEMU virt machine 46 description: For the QEMU virt machine only
51 47
52 description: 48 description:
53 Should be "<vendor>,<chip>-clint", follo 49 Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
54 when compatible with a SiFive CLINT. Pl 50 when compatible with a SiFive CLINT. Please refer to
55 sifive-blocks-ip-versioning.txt for deta 51 sifive-blocks-ip-versioning.txt for details regarding the latter.
56 52
57 reg: 53 reg:
58 maxItems: 1 54 maxItems: 1
59 55
60 interrupts-extended: 56 interrupts-extended:
61 minItems: 1 57 minItems: 1
62 maxItems: 4095 58 maxItems: 4095
63 59
64 additionalProperties: false 60 additionalProperties: false
65 61
66 required: 62 required:
67 - compatible 63 - compatible
68 - reg 64 - reg
69 - interrupts-extended 65 - interrupts-extended
70 66
71 examples: 67 examples:
72 - | 68 - |
73 timer@2000000 { 69 timer@2000000 {
74 compatible = "sifive,fu540-c000-clint", 70 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
75 interrupts-extended = <&cpu1intc 3>, <&c 71 interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
76 <&cpu2intc 3>, <&c 72 <&cpu2intc 3>, <&cpu2intc 7>,
77 <&cpu3intc 3>, <&c 73 <&cpu3intc 3>, <&cpu3intc 7>,
78 <&cpu4intc 3>, <&c 74 <&cpu4intc 3>, <&cpu4intc 7>;
79 reg = <0x2000000 0x10000>; 75 reg = <0x2000000 0x10000>;
80 }; 76 };
81 ... 77 ...
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