1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 %YAML 1.2 2 %YAML 1.2 3 --- 3 --- 4 $id: http://devicetree.org/schemas/ufs/cdns,uf 4 $id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml# 5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 title: Cadence Universal Flash Storage (UFS) C 7 title: Cadence Universal Flash Storage (UFS) Controller 8 8 9 maintainers: 9 maintainers: 10 - Jan Kotas <jank@cadence.com> 10 - Jan Kotas <jank@cadence.com> 11 11 12 # Select only our matches, not all jedec,ufs-2 12 # Select only our matches, not all jedec,ufs-2.0 13 select: 13 select: 14 properties: 14 properties: 15 compatible: 15 compatible: 16 contains: 16 contains: 17 enum: 17 enum: 18 - cdns,ufshc 18 - cdns,ufshc 19 - cdns,ufshc-m31-16nm 19 - cdns,ufshc-m31-16nm 20 required: 20 required: 21 - compatible 21 - compatible 22 22 23 allOf: 23 allOf: 24 - $ref: ufs-common.yaml 24 - $ref: ufs-common.yaml 25 25 26 properties: 26 properties: 27 compatible: 27 compatible: 28 items: 28 items: 29 - enum: 29 - enum: 30 - cdns,ufshc 30 - cdns,ufshc 31 # CDNS UFS HC + M31 16nm PHY 31 # CDNS UFS HC + M31 16nm PHY 32 - cdns,ufshc-m31-16nm 32 - cdns,ufshc-m31-16nm 33 - const: jedec,ufs-2.0 33 - const: jedec,ufs-2.0 34 34 35 clocks: 35 clocks: 36 minItems: 1 36 minItems: 1 37 maxItems: 3 37 maxItems: 3 38 38 39 clock-names: 39 clock-names: 40 minItems: 1 40 minItems: 1 41 items: 41 items: 42 - const: core_clk 42 - const: core_clk 43 - const: phy_clk 43 - const: phy_clk 44 - const: ref_clk 44 - const: ref_clk 45 45 46 power-domains: 46 power-domains: 47 maxItems: 1 47 maxItems: 1 48 48 49 reg: 49 reg: 50 maxItems: 1 50 maxItems: 1 51 51 52 dma-coherent: true << 53 << 54 required: 52 required: 55 - compatible 53 - compatible 56 - clocks 54 - clocks 57 - clock-names 55 - clock-names 58 - reg 56 - reg 59 57 60 unevaluatedProperties: false 58 unevaluatedProperties: false 61 59 62 examples: 60 examples: 63 - | 61 - | 64 #include <dt-bindings/interrupt-controller 62 #include <dt-bindings/interrupt-controller/arm-gic.h> 65 63 66 ufs@fd030000 { 64 ufs@fd030000 { 67 compatible = "cdns,ufshc", "jedec,ufs- 65 compatible = "cdns,ufshc", "jedec,ufs-2.0"; 68 reg = <0xfd030000 0x10000>; 66 reg = <0xfd030000 0x10000>; 69 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL 67 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 70 freq-table-hz = <0 0>, <0 0>; 68 freq-table-hz = <0 0>, <0 0>; 71 clocks = <&ufs_core_clk>, <&ufs_phy_cl 69 clocks = <&ufs_core_clk>, <&ufs_phy_clk>; 72 clock-names = "core_clk", "phy_clk"; 70 clock-names = "core_clk", "phy_clk"; 73 }; 71 };
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