1 TI DA8xx MUSB 1 TI DA8xx MUSB
2 ~~~~~~~~~~~~~ 2 ~~~~~~~~~~~~~
3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms. 3 For DA8xx/OMAP-L1x/AM17xx/AM18xx platforms.
4 4
5 Required properties: 5 Required properties:
6 ~~~~~~~~~~~~~~~~~~~~ 6 ~~~~~~~~~~~~~~~~~~~~
7 - compatible : Should be set to "ti,da830-mus 7 - compatible : Should be set to "ti,da830-musb".
8 8
9 - reg: Offset and length of the USB controlle 9 - reg: Offset and length of the USB controller register set.
10 10
11 - interrupts: The USB interrupt number. 11 - interrupts: The USB interrupt number.
12 12
13 - interrupt-names: Should be set to "mc". 13 - interrupt-names: Should be set to "mc".
14 14
15 - dr_mode: The USB operation mode. Should be 15 - dr_mode: The USB operation mode. Should be one of "host", "peripheral" or "otg".
16 16
17 - phys: Phandle for the PHY device 17 - phys: Phandle for the PHY device
18 18
19 - phy-names: Should be "usb-phy" 19 - phy-names: Should be "usb-phy"
20 20
21 - dmas: specifies the dma channels 21 - dmas: specifies the dma channels
22 22
23 - dma-names: specifies the names of the chann 23 - dma-names: specifies the names of the channels. Use "rxN" for receive
24 and "txN" for transmit endpoints. N specifi 24 and "txN" for transmit endpoints. N specifies the endpoint number.
25 25
26 Optional properties: 26 Optional properties:
27 ~~~~~~~~~~~~~~~~~~~~ 27 ~~~~~~~~~~~~~~~~~~~~
28 - vbus-supply: Phandle to a regulator providi 28 - vbus-supply: Phandle to a regulator providing the USB bus power.
29 29
30 DMA 30 DMA
31 ~~~ 31 ~~~
32 - compatible: ti,da830-cppi41 32 - compatible: ti,da830-cppi41
33 - reg: offset and length of the following regi 33 - reg: offset and length of the following register spaces: CPPI DMA Controller,
34 CPPI DMA Scheduler, Queue Manager 34 CPPI DMA Scheduler, Queue Manager
35 - reg-names: "controller", "scheduler", "queue 35 - reg-names: "controller", "scheduler", "queuemgr"
36 - #dma-cells: should be set to 2. The first nu 36 - #dma-cells: should be set to 2. The first number represents the
37 channel number (0 … 3 for endpoints 1 … 37 channel number (0 … 3 for endpoints 1 … 4).
38 The second number is 0 for RX and 1 for TX t 38 The second number is 0 for RX and 1 for TX transfers.
39 - dma-channels: should be set to 4 representin 39 - dma-channels: should be set to 4 representing the 4 endpoints.
40 - #dma-channels: deprecated 40 - #dma-channels: deprecated
41 41
42 Example: 42 Example:
43 usb_phy: usb-phy { 43 usb_phy: usb-phy {
44 compatible = "ti,da830-usb-phy 44 compatible = "ti,da830-usb-phy";
45 #phy-cells = <0>; 45 #phy-cells = <0>;
46 }; 46 };
47 usb0: usb@200000 { 47 usb0: usb@200000 {
48 compatible = "ti,da830-musb"; 48 compatible = "ti,da830-musb";
49 reg = <0x00200000 0x1000>; 49 reg = <0x00200000 0x1000>;
50 ranges; 50 ranges;
51 #address-cells = <1>; 51 #address-cells = <1>;
52 #size-cells = <1>; 52 #size-cells = <1>;
53 interrupts = <58>; 53 interrupts = <58>;
54 interrupt-names = "mc"; 54 interrupt-names = "mc";
55 55
56 dr_mode = "host"; 56 dr_mode = "host";
57 vbus-supply = <&usb_vbus>; 57 vbus-supply = <&usb_vbus>;
58 phys = <&usb_phy 0>; 58 phys = <&usb_phy 0>;
59 phy-names = "usb-phy"; 59 phy-names = "usb-phy";
60 60
61 dmas = <&cppi41dma 0 0 &cppi41 61 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
62 &cppi41dma 2 0 &cppi41 62 &cppi41dma 2 0 &cppi41dma 3 0
63 &cppi41dma 0 1 &cppi41 63 &cppi41dma 0 1 &cppi41dma 1 1
64 &cppi41dma 2 1 &cppi41 64 &cppi41dma 2 1 &cppi41dma 3 1>;
65 dma-names = 65 dma-names =
66 "rx1", "rx2", "rx3", " 66 "rx1", "rx2", "rx3", "rx4",
67 "tx1", "tx2", "tx3", " 67 "tx1", "tx2", "tx3", "tx4";
68 68
69 69
70 cppi41dma: dma-controller@2010 70 cppi41dma: dma-controller@201000 {
71 compatible = "ti,da830 71 compatible = "ti,da830-cppi41";
72 reg = <0x201000 0x100 72 reg = <0x201000 0x1000
73 0x202000 0x100 73 0x202000 0x1000
74 0x204000 0x400 74 0x204000 0x4000>;
75 reg-names = "controlle 75 reg-names = "controller", "scheduler", "queuemgr";
76 interrupts = <58>; 76 interrupts = <58>;
77 #dma-cells = <2>; 77 #dma-cells = <2>;
78 dma-channels = <4>; 78 dma-channels = <4>;
79 }; 79 };
80 80
81 }; 81 };
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