1 ST DWC3 glue logic
2
3 This file documents the parameters for the dwc
4 This driver controls the glue logic used to co
5 STiH407 based platforms.
6
7 Required properties:
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and
10 - reg-names : should be "reg-glue" and "sy
11 - st,syscon : should be phandle to system
12 encompasses the glue registe
13 - resets : list of phandle and reset sp
14 for the powerdown and softre
15 - reset-names : list of reset signal names.
16 See: Documentation/devicetree/bindings/reset/s
17 See: Documentation/devicetree/bindings/reset/r
18
19 - #address-cells, #size-cells : should be '1'
20 with 'reg' property
21
22 - pinctl-names : A pinctrl state named "defau
23 See: Documentation/devicetree/bindings/pinctrl
24
25 - pinctrl-0 : Pin control group
26 See: Documentation/devicetree/bindings/pinctrl
27
28 - ranges : allows valid 1:1 translation
29 parent's address space
30
31 Sub-nodes:
32 The dwc3 core should be added as subnode to ST
33 example below. The DT binding details of dwc3
34 Documentation/devicetree/bindings/usb/snps,dwc
35
36 NB: The dr_mode property described in [1] is N
37 is "otg", which isn't supported by this SoC. V
38 or "device".
39
40 [1] Documentation/devicetree/bindings/usb/usb-
41
42 Example:
43
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
46 reg = <0x08f94000 0x1000>,
47 reg-names = "reg-glue", "syscfg-
48 st,syscfg = <&syscfg_core>;
49 resets = <&powerdown STIH407_
50 <&softreset STIH407_
51 reset-names = "powerdown", "softre
52 #address-cells = <1>;
53 #size-cells = <1>;
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_usb3>;
56 ranges;
57
58 dwc3: dwc3@9900000 {
59 compatible = "snps,dwc3";
60 reg = <0x09900000
61 interrupts = <GIC_SPI 155
62 dr_mode = "host";
63 phy-names = "usb2-phy",
64 phys = <&usb2_picop
65 };
66 };
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