1 * NXP LPC32xx SoC USB Device Controller (UDC) 1 * NXP LPC32xx SoC USB Device Controller (UDC) 2 2 3 Required properties: 3 Required properties: 4 - compatible: Must be "nxp,lpc3220-udc" 4 - compatible: Must be "nxp,lpc3220-udc" 5 - reg: Physical base address of the controller 5 - reg: Physical base address of the controller and length of memory mapped 6 region. 6 region. 7 - interrupts: The USB interrupts: 7 - interrupts: The USB interrupts: 8 * USB Device Low Priority Interr 8 * USB Device Low Priority Interrupt 9 * USB Device High Priority Inter 9 * USB Device High Priority Interrupt 10 * USB Device DMA Interrupt 10 * USB Device DMA Interrupt 11 * External USB Transceiver Inter 11 * External USB Transceiver Interrupt (OTG ATX) 12 - transceiver: phandle of the associated ISP13 12 - transceiver: phandle of the associated ISP1301 device - this is necessary for 13 the UDC controller for connecti 13 the UDC controller for connecting to the USB physical layer 14 14 15 Example: 15 Example: 16 16 17 isp1301: usb-transceiver@2c { 17 isp1301: usb-transceiver@2c { 18 compatible = "nxp,isp1301"; 18 compatible = "nxp,isp1301"; 19 reg = <0x2c>; 19 reg = <0x2c>; 20 }; 20 }; 21 21 22 usbd@31020000 { 22 usbd@31020000 { 23 compatible = "nxp,lpc3220-udc" 23 compatible = "nxp,lpc3220-udc"; 24 reg = <0x31020000 0x300>; 24 reg = <0x31020000 0x300>; 25 interrupt-parent = <&mic>; 25 interrupt-parent = <&mic>; 26 interrupts = <0x3d 0>, <0x3e 0 26 interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>; 27 transceiver = <&isp1301>; 27 transceiver = <&isp1301>; 28 }; 28 };
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