1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/watchdog/as 4 $id: http://devicetree.org/schemas/watchdog/aspeed,ast2400-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Aspeed watchdog timer controllers 7 title: Aspeed watchdog timer controllers
8 8
9 maintainers: 9 maintainers:
10 - Andrew Jeffery <andrew@codeconstruct.com.au 10 - Andrew Jeffery <andrew@codeconstruct.com.au>
11 11
12 properties: 12 properties:
13 compatible: 13 compatible:
14 enum: 14 enum:
15 - aspeed,ast2400-wdt 15 - aspeed,ast2400-wdt
16 - aspeed,ast2500-wdt 16 - aspeed,ast2500-wdt
17 - aspeed,ast2600-wdt 17 - aspeed,ast2600-wdt
18 18
19 reg: 19 reg:
20 maxItems: 1 20 maxItems: 1
21 21
22 clocks: 22 clocks:
23 maxItems: 1 23 maxItems: 1
24 description: > 24 description: >
25 The clock used to drive the watchdog cou 25 The clock used to drive the watchdog counter. From the AST2500 no source
26 other than the 1MHz clock can be selecte 26 other than the 1MHz clock can be selected, so the clocks property is
27 optional. 27 optional.
28 28
29 aspeed,reset-type: 29 aspeed,reset-type:
30 $ref: /schemas/types.yaml#/definitions/str 30 $ref: /schemas/types.yaml#/definitions/string
31 enum: 31 enum:
32 - cpu 32 - cpu
33 - soc 33 - soc
34 - system 34 - system
35 - none 35 - none
36 default: system 36 default: system
37 description: > 37 description: >
38 The watchdog can be programmed to genera 38 The watchdog can be programmed to generate one of three different types of
39 reset when a timeout occcurs. 39 reset when a timeout occcurs.
40 40
41 Specifying 'cpu' will only reset the pro 41 Specifying 'cpu' will only reset the processor on a timeout event.
42 42
43 Specifying 'soc' will reset a configurab 43 Specifying 'soc' will reset a configurable subset of the SoC's controllers
44 on a timeout event. Controllers critical 44 on a timeout event. Controllers critical to the SoC's operation may remain
45 untouched. The set of SoC controllers to 45 untouched. The set of SoC controllers to reset may be specified via the
46 aspeed,reset-mask property if the node h 46 aspeed,reset-mask property if the node has the aspeed,ast2500-wdt or
47 aspeed,ast2600-wdt compatible. 47 aspeed,ast2600-wdt compatible.
48 48
49 Specifying 'system' will reset all contr 49 Specifying 'system' will reset all controllers on a timeout event, as if
50 EXTRST had been asserted. 50 EXTRST had been asserted.
51 51
52 Specifying 'none' will cause the timeout 52 Specifying 'none' will cause the timeout event to have no reset effect.
53 Another watchdog engine on the chip must 53 Another watchdog engine on the chip must be used for chip reset operations.
54 54
55 aspeed,alt-boot: 55 aspeed,alt-boot:
56 $ref: /schemas/types.yaml#/definitions/fla 56 $ref: /schemas/types.yaml#/definitions/flag
57 description: > 57 description: >
58 Direct the watchdog to configure the SoC 58 Direct the watchdog to configure the SoC to boot from the alternative boot
59 region if a timeout occurs. 59 region if a timeout occurs.
60 60
61 aspeed,external-signal: 61 aspeed,external-signal:
62 $ref: /schemas/types.yaml#/definitions/fla 62 $ref: /schemas/types.yaml#/definitions/flag
63 description: > 63 description: >
64 Assert the timeout event on an external 64 Assert the timeout event on an external signal pin associated with the
65 watchdog controller instance. The pin mu 65 watchdog controller instance. The pin must be muxed appropriately.
66 66
67 aspeed,ext-pulse-duration: 67 aspeed,ext-pulse-duration:
68 $ref: /schemas/types.yaml#/definitions/uin 68 $ref: /schemas/types.yaml#/definitions/uint32
69 description: > 69 description: >
70 The duration, in microseconds, of the pu 70 The duration, in microseconds, of the pulse emitted on the external signal
71 pin. 71 pin.
72 72
73 aspeed,ext-push-pull: 73 aspeed,ext-push-pull:
74 $ref: /schemas/types.yaml#/definitions/fla 74 $ref: /schemas/types.yaml#/definitions/flag
75 description: > 75 description: >
76 If aspeed,external-signal is specified i 76 If aspeed,external-signal is specified in the node, set the external
77 signal pin's drive type to push-pull. If 77 signal pin's drive type to push-pull. If aspeed,ext-push-pull is not
78 specified then the pin is configured as 78 specified then the pin is configured as open-drain.
79 79
80 aspeed,ext-active-high: 80 aspeed,ext-active-high:
81 $ref: /schemas/types.yaml#/definitions/fla 81 $ref: /schemas/types.yaml#/definitions/flag
82 description: > 82 description: >
83 If both aspeed,external-signal and aspee 83 If both aspeed,external-signal and aspeed,ext-push-pull are specified in
84 the node, set the pulse polarity to acti 84 the node, set the pulse polarity to active-high. If aspeed,ext-active-high
85 is not specified then the pin is configu 85 is not specified then the pin is configured as active-low.
86 86
87 aspeed,reset-mask: 87 aspeed,reset-mask:
88 $ref: /schemas/types.yaml#/definitions/uin 88 $ref: /schemas/types.yaml#/definitions/uint32-array
89 minItems: 1 89 minItems: 1
90 maxItems: 2 90 maxItems: 2
91 description: > 91 description: >
92 A bitmask indicating which peripherals w 92 A bitmask indicating which peripherals will be reset if the watchdog
93 timer expires. On AST2500 SoCs this shou 93 timer expires. On AST2500 SoCs this should be a single word defined using
94 the AST2500_WDT_RESET_* macros; on AST26 94 the AST2500_WDT_RESET_* macros; on AST2600 SoCs this should be a two-word
95 array with the first word defined using 95 array with the first word defined using the AST2600_WDT_RESET1_* macros,
96 and the second word defined using the AS 96 and the second word defined using the AST2600_WDT_RESET2_* macros.
97 97
98 required: 98 required:
99 - compatible 99 - compatible
100 - reg 100 - reg
101 101
102 allOf: 102 allOf:
103 - if: 103 - if:
104 anyOf: 104 anyOf:
105 - required: 105 - required:
106 - aspeed,ext-push-pull 106 - aspeed,ext-push-pull
107 - required: 107 - required:
108 - aspeed,ext-active-high 108 - aspeed,ext-active-high
109 - required: 109 - required:
110 - aspeed,reset-mask 110 - aspeed,reset-mask
111 then: 111 then:
112 properties: 112 properties:
113 compatible: 113 compatible:
114 enum: 114 enum:
115 - aspeed,ast2500-wdt 115 - aspeed,ast2500-wdt
116 - aspeed,ast2600-wdt 116 - aspeed,ast2600-wdt
117 - if: 117 - if:
118 required: 118 required:
119 - aspeed,ext-active-high 119 - aspeed,ext-active-high
120 then: 120 then:
121 required: 121 required:
122 - aspeed,ext-push-pull 122 - aspeed,ext-push-pull
123 123
124 additionalProperties: false 124 additionalProperties: false
125 125
126 examples: 126 examples:
127 - | 127 - |
128 watchdog@1e785000 { 128 watchdog@1e785000 {
129 compatible = "aspeed,ast2400-wdt"; 129 compatible = "aspeed,ast2400-wdt";
130 reg = <0x1e785000 0x1c>; 130 reg = <0x1e785000 0x1c>;
131 aspeed,reset-type = "system"; 131 aspeed,reset-type = "system";
132 aspeed,external-signal; 132 aspeed,external-signal;
133 }; 133 };
134 - | 134 - |
135 #include <dt-bindings/watchdog/aspeed-wdt. 135 #include <dt-bindings/watchdog/aspeed-wdt.h>
136 watchdog@1e785040 { 136 watchdog@1e785040 {
137 compatible = "aspeed,ast2600-wdt"; 137 compatible = "aspeed,ast2600-wdt";
138 reg = <0x1e785040 0x40>; 138 reg = <0x1e785040 0x40>;
139 aspeed,reset-type = "soc"; 139 aspeed,reset-type = "soc";
140 aspeed,reset-mask = <AST2600_WDT_RESET 140 aspeed,reset-mask = <AST2600_WDT_RESET1_DEFAULT
141 (AST2600_WDT_RESET 141 (AST2600_WDT_RESET2_DEFAULT & ~AST2600_WDT_RESET2_LPC)>;
142 }; 142 };
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