1 # SPDX-License-Identifier: (GPL-2.0-only OR BS 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/watchdog/qc 4 $id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Qualcomm Krait Processor Sub-system (KP 7 title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
8 8
9 maintainers: 9 maintainers:
10 - Rajendra Nayak <quic_rjendra@quicinc.com> 10 - Rajendra Nayak <quic_rjendra@quicinc.com>
11 11
12 properties: 12 properties:
13 $nodename: 13 $nodename:
14 pattern: "^(watchdog|timer)@[0-9a-f]+$" 14 pattern: "^(watchdog|timer)@[0-9a-f]+$"
15 15
16 compatible: 16 compatible:
17 oneOf: 17 oneOf:
18 - items: 18 - items:
19 - enum: 19 - enum:
20 - qcom,kpss-wdt-ipq4019 20 - qcom,kpss-wdt-ipq4019
21 - qcom,apss-wdt-ipq5018 21 - qcom,apss-wdt-ipq5018
22 - qcom,apss-wdt-ipq5332 22 - qcom,apss-wdt-ipq5332
23 - qcom,apss-wdt-ipq9574 23 - qcom,apss-wdt-ipq9574
24 - qcom,apss-wdt-msm8226 24 - qcom,apss-wdt-msm8226
25 - qcom,apss-wdt-msm8974 25 - qcom,apss-wdt-msm8974
26 - qcom,apss-wdt-msm8994 26 - qcom,apss-wdt-msm8994
27 - qcom,apss-wdt-qcm2290 27 - qcom,apss-wdt-qcm2290
28 - qcom,apss-wdt-qcs404 28 - qcom,apss-wdt-qcs404
29 - qcom,apss-wdt-sa8255p 29 - qcom,apss-wdt-sa8255p
30 - qcom,apss-wdt-sa8775p 30 - qcom,apss-wdt-sa8775p
31 - qcom,apss-wdt-sc7180 31 - qcom,apss-wdt-sc7180
32 - qcom,apss-wdt-sc7280 32 - qcom,apss-wdt-sc7280
33 - qcom,apss-wdt-sc8180x 33 - qcom,apss-wdt-sc8180x
34 - qcom,apss-wdt-sc8280xp 34 - qcom,apss-wdt-sc8280xp
35 - qcom,apss-wdt-sdm845 35 - qcom,apss-wdt-sdm845
36 - qcom,apss-wdt-sdx55 36 - qcom,apss-wdt-sdx55
37 - qcom,apss-wdt-sdx65 37 - qcom,apss-wdt-sdx65
38 - qcom,apss-wdt-sm6115 38 - qcom,apss-wdt-sm6115
39 - qcom,apss-wdt-sm6350 39 - qcom,apss-wdt-sm6350
40 - qcom,apss-wdt-sm8150 40 - qcom,apss-wdt-sm8150
41 - qcom,apss-wdt-sm8250 41 - qcom,apss-wdt-sm8250
42 - const: qcom,kpss-wdt 42 - const: qcom,kpss-wdt
43 - const: qcom,kpss-wdt 43 - const: qcom,kpss-wdt
44 deprecated: true 44 deprecated: true
45 - items: 45 - items:
46 - const: qcom,scss-timer 46 - const: qcom,scss-timer
47 - const: qcom,msm-timer 47 - const: qcom,msm-timer
48 - items: 48 - items:
49 - enum: 49 - enum:
50 - qcom,kpss-wdt-apq8064 50 - qcom,kpss-wdt-apq8064
51 - qcom,kpss-wdt-ipq8064 51 - qcom,kpss-wdt-ipq8064
52 - qcom,kpss-wdt-mdm9615 52 - qcom,kpss-wdt-mdm9615
53 - qcom,kpss-wdt-msm8960 53 - qcom,kpss-wdt-msm8960
54 - const: qcom,kpss-timer 54 - const: qcom,kpss-timer
55 - const: qcom,msm-timer 55 - const: qcom,msm-timer
56 56
57 reg: 57 reg:
58 maxItems: 1 58 maxItems: 1
59 59
60 clocks: 60 clocks:
61 maxItems: 1 61 maxItems: 1
62 62
63 clock-names: 63 clock-names:
64 items: 64 items:
65 - const: sleep 65 - const: sleep
66 66
67 clock-frequency: 67 clock-frequency:
68 description: 68 description:
69 The frequency of the general purpose tim 69 The frequency of the general purpose timer in Hz.
70 70
71 cpu-offset: 71 cpu-offset:
72 $ref: /schemas/types.yaml#/definitions/uin 72 $ref: /schemas/types.yaml#/definitions/uint32
73 description: 73 description:
74 Per-CPU offset used when the timer is ac 74 Per-CPU offset used when the timer is accessed without the CPU remapping
75 facilities. The offset is cpu-offset + ( 75 facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
76 76
77 interrupts: 77 interrupts:
78 minItems: 1 78 minItems: 1
79 maxItems: 5 79 maxItems: 5
80 80
81 required: 81 required:
82 - compatible 82 - compatible
83 - reg 83 - reg
84 - clocks 84 - clocks
85 85
86 allOf: 86 allOf:
87 - $ref: watchdog.yaml# 87 - $ref: watchdog.yaml#
88 88
89 - if: 89 - if:
90 properties: 90 properties:
91 compatible: 91 compatible:
92 contains: 92 contains:
93 const: qcom,kpss-wdt 93 const: qcom,kpss-wdt
94 then: 94 then:
95 properties: 95 properties:
96 clock-frequency: false 96 clock-frequency: false
97 cpu-offset: false 97 cpu-offset: false
98 interrupts: 98 interrupts:
99 minItems: 1 99 minItems: 1
100 items: 100 items:
101 - description: Bark 101 - description: Bark
102 - description: Bite 102 - description: Bite
103 103
104 else: 104 else:
105 properties: 105 properties:
106 interrupts: 106 interrupts:
107 minItems: 3 107 minItems: 3
108 items: 108 items:
109 - description: Debug 109 - description: Debug
110 - description: First general purpo 110 - description: First general purpose timer
111 - description: Second general purp 111 - description: Second general purpose timer
112 - description: First watchdog 112 - description: First watchdog
113 - description: Second watchdog 113 - description: Second watchdog
114 required: 114 required:
115 - clock-frequency 115 - clock-frequency
116 116
117 unevaluatedProperties: false 117 unevaluatedProperties: false
118 118
119 examples: 119 examples:
120 - | 120 - |
121 #include <dt-bindings/interrupt-controller 121 #include <dt-bindings/interrupt-controller/arm-gic.h>
122 122
123 watchdog@17c10000 { 123 watchdog@17c10000 {
124 compatible = "qcom,apss-wdt-sm8150", " 124 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
125 reg = <0x17c10000 0x1000>; 125 reg = <0x17c10000 0x1000>;
126 clocks = <&sleep_clk>; 126 clocks = <&sleep_clk>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_ 127 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
128 timeout-sec = <10>; 128 timeout-sec = <10>;
129 }; 129 };
130 130
131 - | 131 - |
132 #include <dt-bindings/interrupt-controller 132 #include <dt-bindings/interrupt-controller/arm-gic.h>
133 133
134 watchdog@200a000 { 134 watchdog@200a000 {
135 compatible = "qcom,kpss-wdt-ipq8064", 135 compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
136 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_ 136 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
137 <GIC_PPI 2 (GIC_CPU_MASK_ 137 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
138 <GIC_PPI 3 (GIC_CPU_MASK_ 138 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
139 <GIC_PPI 4 (GIC_CPU_MASK_ 139 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
140 <GIC_PPI 5 (GIC_CPU_MASK_ 140 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
141 reg = <0x0200a000 0x100>; 141 reg = <0x0200a000 0x100>;
142 clock-frequency = <25000000>; 142 clock-frequency = <25000000>;
143 clocks = <&sleep_clk>; 143 clocks = <&sleep_clk>;
144 clock-names = "sleep"; 144 clock-names = "sleep";
145 cpu-offset = <0x80000>; 145 cpu-offset = <0x80000>;
146 }; 146 };
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