1 # SPDX-License-Identifier: GPL-2.0-only OR BSD
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/watchdog/re
5 $schema: http://devicetree.org/meta-schemas/co
6
7 title: Realtek Otto watchdog timer
8
9 maintainers:
10 - Sander Vanheule <sander@svanheule.net>
11
12 description: |
13 The timer has two timeout phases. Both phase
14 prescaled clock ticks, which is ca. 43s with
15 minimum duration of each phase is one tick.
16 interrupt, although the phase 2 interrupt wi
17 - Phase 1: During this phase, the WDT can be
18 - Phase 2: Starts after phase 1 has timed ou
19 system some time to clean up, or notify ot
20 During this phase, pinging the WDT has no
21 unavoidable, unless the WDT is disabled.
22
23 allOf:
24 - $ref: watchdog.yaml#
25
26 properties:
27 compatible:
28 enum:
29 - realtek,rtl8380-wdt
30 - realtek,rtl8390-wdt
31 - realtek,rtl9300-wdt
32 - realtek,rtl9310-wdt
33
34 reg:
35 maxItems: 1
36
37 clocks:
38 maxItems: 1
39
40 interrupts:
41 items:
42 - description: interrupt specifier for p
43 - description: interrupt specifier for t
44
45 interrupt-names:
46 items:
47 - const: phase1
48 - const: phase2
49
50 realtek,reset-mode:
51 $ref: /schemas/types.yaml#/definitions/str
52 description: |
53 Specify how the system is reset after a
54 left unspecified.
55 oneOf:
56 - description: Reset the entire chip
57 const: soc
58 - description: |
59 Reset the CPU and IPsec engine, but
60 const: cpu
61 - description: |
62 Reset the execution pointer, but don
63 const: software
64
65 required:
66 - compatible
67 - reg
68 - clocks
69 - interrupts
70 - interrupt-names
71
72 unevaluatedProperties: false
73
74 examples:
75 - |
76 watchdog: watchdog@3150 {
77 compatible = "realtek,rtl8380-wdt";
78 reg = <0x3150 0xc>;
79
80 realtek,reset-mode = "soc";
81
82 clocks = <&lxbus_clock>;
83 timeout-sec = <20>;
84
85 interrupt-parent = <&rtlintc>;
86 interrupt-names = "phase1", "phase2";
87 interrupts = <19>, <18>;
88 };
89
90 ...
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