1 # SPDX-License-Identifier: GPL-2.0-only OR BSD 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2 %YAML 1.2 2 %YAML 1.2
3 --- 3 ---
4 $id: http://devicetree.org/schemas/watchdog/re 4 $id: http://devicetree.org/schemas/watchdog/realtek,otto-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/co 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6 6
7 title: Realtek Otto watchdog timer 7 title: Realtek Otto watchdog timer
8 8
9 maintainers: 9 maintainers:
10 - Sander Vanheule <sander@svanheule.net> 10 - Sander Vanheule <sander@svanheule.net>
11 11
12 description: | 12 description: |
13 The timer has two timeout phases. Both phase 13 The timer has two timeout phases. Both phases have a maximum duration of 32
14 prescaled clock ticks, which is ca. 43s with 14 prescaled clock ticks, which is ca. 43s with a bus clock of 200MHz. The
15 minimum duration of each phase is one tick. 15 minimum duration of each phase is one tick. Each phase can trigger an
16 interrupt, although the phase 2 interrupt wi 16 interrupt, although the phase 2 interrupt will occur with the system reset.
17 - Phase 1: During this phase, the WDT can be 17 - Phase 1: During this phase, the WDT can be pinged to reset the timeout.
18 - Phase 2: Starts after phase 1 has timed ou 18 - Phase 2: Starts after phase 1 has timed out, and only serves to give the
19 system some time to clean up, or notify ot 19 system some time to clean up, or notify others that it's going to reset.
20 During this phase, pinging the WDT has no 20 During this phase, pinging the WDT has no effect, and a reset is
21 unavoidable, unless the WDT is disabled. 21 unavoidable, unless the WDT is disabled.
22 22
23 allOf: 23 allOf:
24 - $ref: watchdog.yaml# 24 - $ref: watchdog.yaml#
25 25
26 properties: 26 properties:
27 compatible: 27 compatible:
28 enum: 28 enum:
29 - realtek,rtl8380-wdt 29 - realtek,rtl8380-wdt
30 - realtek,rtl8390-wdt 30 - realtek,rtl8390-wdt
31 - realtek,rtl9300-wdt 31 - realtek,rtl9300-wdt
32 - realtek,rtl9310-wdt 32 - realtek,rtl9310-wdt
33 33
34 reg: 34 reg:
35 maxItems: 1 35 maxItems: 1
36 36
37 clocks: 37 clocks:
38 maxItems: 1 38 maxItems: 1
39 39
40 interrupts: 40 interrupts:
41 items: 41 items:
42 - description: interrupt specifier for p 42 - description: interrupt specifier for pretimeout
43 - description: interrupt specifier for t 43 - description: interrupt specifier for timeout
44 44
45 interrupt-names: 45 interrupt-names:
46 items: 46 items:
47 - const: phase1 47 - const: phase1
48 - const: phase2 48 - const: phase2
49 49
50 realtek,reset-mode: 50 realtek,reset-mode:
51 $ref: /schemas/types.yaml#/definitions/str 51 $ref: /schemas/types.yaml#/definitions/string
52 description: | 52 description: |
53 Specify how the system is reset after a 53 Specify how the system is reset after a timeout. Defaults to "cpu" if
54 left unspecified. 54 left unspecified.
55 oneOf: 55 oneOf:
56 - description: Reset the entire chip 56 - description: Reset the entire chip
57 const: soc 57 const: soc
58 - description: | 58 - description: |
59 Reset the CPU and IPsec engine, but 59 Reset the CPU and IPsec engine, but leave other peripherals untouched
60 const: cpu 60 const: cpu
61 - description: | 61 - description: |
62 Reset the execution pointer, but don 62 Reset the execution pointer, but don't actually reset any hardware
63 const: software 63 const: software
64 64
65 required: 65 required:
66 - compatible 66 - compatible
67 - reg 67 - reg
68 - clocks 68 - clocks
69 - interrupts 69 - interrupts
70 - interrupt-names 70 - interrupt-names
71 71
72 unevaluatedProperties: false 72 unevaluatedProperties: false
73 73
74 examples: 74 examples:
75 - | 75 - |
76 watchdog: watchdog@3150 { 76 watchdog: watchdog@3150 {
77 compatible = "realtek,rtl8380-wdt"; 77 compatible = "realtek,rtl8380-wdt";
78 reg = <0x3150 0xc>; 78 reg = <0x3150 0xc>;
79 79
80 realtek,reset-mode = "soc"; 80 realtek,reset-mode = "soc";
81 81
82 clocks = <&lxbus_clock>; 82 clocks = <&lxbus_clock>;
83 timeout-sec = <20>; 83 timeout-sec = <20>;
84 84
85 interrupt-parent = <&rtlintc>; 85 interrupt-parent = <&rtlintc>;
86 interrupt-names = "phase1", "phase2"; 86 interrupt-names = "phase1", "phase2";
87 interrupts = <19>, <18>; 87 interrupts = <19>, <18>;
88 }; 88 };
89 89
90 ... 90 ...
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