1 d) Xilinx IP cores
2
3 The Xilinx EDK toolchain ships with a set o
4 in Xilinx Spartan and Virtex FPGAs. The de
5 of standard device types (network, serial,
6 devices (gpio, LCD, spi, etc). Also, since
7 implemented within the fpga fabric every in
8 synthesised with different options that cha
9
10 Each IP-core has a set of parameters which
11 control how the core is synthesized. Histo
12 extract the device parameters relevant to d
13 into an 'xparameters.h' in the form of #def
14 device drivers how the IP cores are configu
15 to be recompiled every time the FPGA bitstr
16
17 The new approach is to export the parameter
18 generate a new device tree each time the FP
19 parameters which used to be exported as #de
20 properties of the device node. In general,
21 will take the following form:
22
23 (name): (generic-name)@(base-address)
24 compatible = "xlnx,(ip-core-na
25 [, (list of compa
26 reg = <(baseaddr) (size)>;
27 interrupt-parent = <&interrupt
28 interrupts = < ... >;
29 xlnx,(parameter1) = "(string-v
30 xlnx,(parameter2) = <(int-valu
31 };
32
33 (generic-name): an open firmware-sty
34 generic class of devic
35 as 'serial' or 'ethern
36 (ip-core-name): the name of the ip blo
37 directive in system.mh
38 and all underscores '_
39 (name): is derived from the "P
40 (parameter#): C_* parameters from sy
41 dropped from the param
42 to lowercase and all u
43 converted to dashes '-
44 (baseaddr): the baseaddr parameter
45 (HW_VER): from the HW_VER parame
46 (size): the address range size
47
48 Typically, the compatible list will include
49 followed by an older IP core version which
50 interface or any other device with the same
51
52 'reg' and 'interrupts' are all optional pro
53
54 For example, the following block from syste
55
56 BEGIN opb_uartlite
57 PARAMETER INSTANCE = opb_uartl
58 PARAMETER HW_VER = 1.00.b
59 PARAMETER C_BAUDRATE = 115200
60 PARAMETER C_DATA_BITS = 8
61 PARAMETER C_ODD_PARITY = 0
62 PARAMETER C_USE_PARITY = 0
63 PARAMETER C_CLK_FREQ = 5000000
64 PARAMETER C_BASEADDR = 0xEC100
65 PARAMETER C_HIGHADDR = 0xEC10F
66 BUS_INTERFACE SOPB = opb_7
67 PORT OPB_Clk = CLK_50MHz
68 PORT Interrupt = opb_uartlite_
69 PORT RX = opb_uartlite_0_RX
70 PORT TX = opb_uartlite_0_TX
71 PORT OPB_Rst = sys_bus_reset_0
72 END
73
74 becomes the following device tree node:
75
76 opb_uartlite_0: serial@ec100000 {
77 device_type = "serial";
78 compatible = "xlnx,opb-uartlit
79 reg = <ec100000 10000>;
80 interrupt-parent = <&opb_intc_
81 interrupts = <1 0>; // got thi
82 current-speed = <d#115200>;
83 clock-frequency = <d#50000000>
84 xlnx,data-bits = <8>;
85 xlnx,odd-parity = <0>;
86 xlnx,use-parity = <0>;
87 };
88
89 That covers the general approach to binding
90 device tree. The following are bindings fo
91
92 i) Xilinx ML300 Framebuffer
93
94 Simple framebuffer device from the ML300
95 ML403 reference design as well as others
96
97 Optional properties:
98 - resolution = <xres yres> : pixel reso
99 implementa
100 Default is
101 - virt-resolution = <xvirt yvirt> : Siz
102 Def
103 - rotate-display (empty) : rotate displ
104
105 ii) Xilinx SystemACE
106
107 The Xilinx SystemACE device is used to p
108 bitstream stored on a CF card. It can a
109 interface device.
110
111 Optional properties:
112 - 8-bit (empty) : Set this property for
113
114 iii) Xilinx EMAC and Xilinx TEMAC
115
116 Xilinx Ethernet devices. In addition to
117 listed above, nodes for these devices sh
118 property, and may include other common n
119 like local-mac-address.
120
121 iv) Xilinx Uartlite
122
123 Xilinx uartlite devices are simple fixed
124
125 Required properties:
126 - current-speed : Baud rate of uartlite
127
128 v) Xilinx hwicap
129
130 Xilinx hwicap devices provide
131 of the FPGA through the Intern
132 (ICAP). The ICAP enables part
133 readback of the configuration
134 'warm boots' of the FPGA fabri
135
136 Required properties:
137 - xlnx,family : The family of
138 capabilities of the unde
139 differ between different
140 'virtex2p', 'virtex4', o
141 - compatible : should contain
142 "xlnx,opb-hwic
143
144 vi) Xilinx Uart 16550
145
146 Xilinx UART 16550 devices are very simil
147 different register spacing and an offset
148
149 Required properties:
150 - clock-frequency : Frequency of the cl
151 - reg-offset : A value of 3 is required
152 - reg-shift : A value of 2 is required
153
154 vii) Xilinx USB Host controller
155
156 The Xilinx USB host controller is EHCI c
157 base address for the EHCI registers, and
158 USB Host controller. The hardware can be
159 or high speed/full speed hybrid.
160
161 Required properties:
162 - xlnx,support-usb-fs: A value 0 means t
163 only. A value 1 m
164 full speed device
165
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