1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: <isonum.txt>
3
4 ==================================
5 CXL Access Coordinates Computation
6 ==================================
7
8 Shared Upstream Link Calculation
9 ================================
10 For certain CXL region construction with endpo
11 Root Ports (RP), there is the possibility of t
12 the endpoints behind a switch being more than
13 A similar situation can occur within the host,
14 The CXL driver performs an additional pass aft
15 arrived for a region in order to recalculate t
16 upstream link being a limiting factor in mind.
17
18 The algorithm assumes the configuration is a s
19 maximizes performance. When asymmetric topolog
20 is aborted. An asymmetric topology is detected
21 number of RPs detected as a grandparent is not
22 iterated in the same iteration loop. The assum
23 asymmetry in properties does not happen and al
24
25 There can be multiple switches under an RP. Th
26 a CXL Host Bridge (HB). There can be multiple
27 Window Structure (CFMWS).
28
29 An example hierarchy:
30
31 > CFMWS 0
32 > |
33 > _________|_________
34 > | |
35 > ACPI0017-0 ACPI0017-1
36 > GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1
37 > | | | |
38 > RP0 RP1 RP2 RP3
39 > | | | |
40 > SW 0 SW 1 SW 2 SW 3
41 > | | | | | | | |
42 > EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7
43
44 Computation for the example hierarchy:
45
46 Min (GP0 to CPU BW,
47 Min(SW 0 Upstream Link to RP0 BW,
48 Min(SW0SSLBIS for SW0DSP0 (EP0), EP0
49 Min(SW0SSLBIS for SW0DSP1 (EP1), EP1
50 Min(SW 1 Upstream Link to RP1 BW,
51 Min(SW1SSLBIS for SW1DSP0 (EP2), EP2
52 Min(SW1SSLBIS for SW1DSP1 (EP3), EP3
53 Min (GP1 to CPU BW,
54 Min(SW 2 Upstream Link to RP2 BW,
55 Min(SW2SSLBIS for SW2DSP0 (EP4), EP4
56 Min(SW2SSLBIS for SW2DSP1 (EP5), EP5
57 Min(SW 3 Upstream Link to RP3 BW,
58 Min(SW3SSLBIS for SW3DSP0 (EP6), EP6
59 Min(SW3SSLBIS for SW3DSP1 (EP7), EP7
60
61 The calculation starts at cxl_region_shared_up
62 is created to collect all the endpoint bandwid
63 cxl_endpoint_gather_bandwidth() function. The
64 endpoint CDAT and the upstream link bandwidth
65 has a CXL switch as a parent, then min() of ca
66 bandwidth from the SSLBIS for the switch downs
67 with the endpoint is calculated. The final ban
68 'struct cxl_perf_ctx' in the xarray indexed by
69 endpoint is direct attached to a root port (RP
70 RP device. If the endpoint is behind a switch,
71 upstream device of the parent switch.
72
73 At the next stage, the code walks through one
74 in the topology. For endpoints directly attach
75 If there is another switch upstream, the code
76 gathered bandwidth and the upstream link bandw
77 upstream, then the SSLBIS of the upstream swit
78
79 Once the topology walk reaches the RP, whether
80 or walking through the switch(es), cxl_rp_gath
81 this point all the bandwidths are aggregated p
82 also the index for the resulting xarray.
83
84 The next step is to take the min() of the per
85 bandwidth from the Generic Port (GP). The band
86 via ACPI tables SRAT/HMAT. The min bandwidth a
87 ACPI0017 device to form a new xarray.
88
89 Finally, the cxl_region_update_bandwidth() is
90 bandwidth from all the members of the last xar
91 access coordinates residing in the cxl region
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