1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: <isonum.txt>
3
4 ===========================================
5 Compute Express Link Subsystem Maturity Map
6 ===========================================
7
8 The Linux CXL subsystem tracks the dynamic `CX
9 <https://computeexpresslink.org/cxl-specificat
10 continues to respond to new use cases with new
11 updates and fixes. At any given point some asp
12 more mature than others. While the periodic pu
13 `work being incorporated each merge window
14 <https://lore.kernel.org/linux-cxl/?q=s%3APULL
15 those do not always convey progress relative t
16 future end goal.
17
18 What follows is a coarse breakdown of the subs
19 responsibilities along with a maturity score.
20 the change-history of this document provides a
21 subsystem maturation over time.
22
23 The maturity scores are:
24
25 - [3] Mature: Work in this area is complete an
26 Note that this score can regress from one ke
27 based on new test results or end user report
28
29 - [2] Stabilizing: Major functionality operati
30 mature, but known corner cases are still a w
31
32 - [1] Initial: Capability that has exited the
33 may still have significant gaps to close and
34 world testing occurs.
35
36 - [0] Known gap: Feature is on a medium to lon
37 implement. If the specification has a featu
38 a '0' score in this document, there is a goo
39 the linux-cxl@vger.kernel.org community has
40
41 - X: Out of scope for kernel enabling, or kern
42
43 Feature and Capabilities
44 ========================
45
46 Enumeration / Provisioning
47 --------------------------
48 All of the fundamental enumeration an object m
49 in place, but there are several corner cases t
50
51
52 * [2] CXL Window Enumeration
53
54 * [0] :ref:`Extended-linear memory-side cach
55 * [0] Low Memory-hole
56 * [0] Hetero-interleave
57
58 * [2] Switch Enumeration
59
60 * [0] CXL register enumeration link-up depen
61
62 * [2] HDM Decoder Configuration
63
64 * [0] Decoder target and granularity constra
65
66 * [2] Performance enumeration
67
68 * [3] Endpoint CDAT
69 * [3] Switch CDAT
70 * [1] CDAT to Core-mm integration
71
72 * [1] x86
73 * [0] Arm64
74 * [0] All other arch.
75
76 * [0] Shared link
77
78 * [2] Hotplug
79 (see CXL Window Enumeration)
80
81 * [0] Handle Soft Reserved conflicts
82
83 * [0] :ref:`RCH link status <rch-link-status>`
84 * [0] Fabrics / G-FAM (chapter 7)
85 * [0] Global Access Endpoint
86
87
88 RAS
89 ---
90 In many ways CXL can be seen as a standardizat
91 be handled by custom EDAC drivers. The open de
92 mainly caused by the enumeration corner cases
93
94 * [3] Component events (OS)
95 * [2] Component events (FFM)
96 * [1] Endpoint protocol errors (OS)
97 * [1] Endpoint protocol errors (FFM)
98 * [0] Switch protocol errors (OS)
99 * [1] Switch protocol errors (FFM)
100 * [2] DPA->HPA Address translation
101
102 * [1] XOR Interleave translation
103 (see CXL Window Enumeration)
104
105 * [1] Memory Failure coordination
106 * [0] Scrub control
107 * [2] ACPI error injection EINJ
108
109 * [0] EINJ v2
110 * [X] Compliance DOE
111
112 * [2] Native error injection
113 * [3] RCH error handling
114 * [1] VH error handling
115 * [0] PPR
116 * [0] Sparing
117 * [0] Device built in test
118
119
120 Mailbox commands
121 ----------------
122
123 * [3] Firmware update
124 * [3] Health / Alerts
125 * [1] :ref:`Background commands <background-co
126 * [3] Sanitization
127 * [3] Security commands
128 * [3] RAW Command Debug Passthrough
129 * [0] CEL-only-validation Passthrough
130 * [0] Switch CCI
131 * [3] Timestamp
132 * [1] PMEM labels
133 * [0] PMEM GPF / Dirty Shutdown
134 * [0] Scan Media
135
136 PMU
137 ---
138 * [1] Type 3 PMU
139 * [0] Switch USP/ DSP, Root Port
140
141 Security
142 --------
143
144 * [X] CXL Trusted Execution Environment Securi
145 * [X] CXL IDE (subsumed by TSP)
146
147 Memory-pooling
148 --------------
149
150 * [1] Hotplug of LDs (via PCI hotplug)
151 * [0] Dynamic Capacity Device (DCD) Support
152
153 Multi-host sharing
154 ------------------
155
156 * [0] Hardware coherent shared memory
157 * [0] Software managed coherency shared memory
158
159 Multi-host memory
160 -----------------
161
162 * [0] Dynamic Capacity Device Support
163 * [0] Sharing
164
165 Accelerator
166 -----------
167
168 * [0] Accelerator memory enumeration HDM-D (CX
169 * [0] Accelerator memory enumeration HDM-DB (C
170 * [0] CXL.cache 68b (CXL 2.0)
171 * [0] CXL.cache 256b Cache IDs (CXL 3.0)
172
173 User Flow Support
174 -----------------
175
176 * [0] HPA->DPA Address translation (need xorma
177
178 Details
179 =======
180
181 .. _extended-linear:
182
183 * **Extended-linear memory-side cache**: An HM
184 memory-side cache where the cache capacity e
185 range capacity. `See the ECN
186 <https://lore.kernel.org/linux-cxl/6650e4f835
187 for more details:
188
189 .. _rch-link-status:
190
191 * **RCH Link Status**: RCH (Restricted CXL Hos
192 hiding some standard registers like PCIe Lin
193 the CXL RCRB (Root Complex Register Block).
194
195 .. _background-commands:
196
197 * **Background commands**: The CXL background
198 awkward as the single slot is monopolized po
199 various commands. A `cancel on conflict
200 <http://lore.kernel.org/r/66035c2e8ba17_77023
201 facility is needed to make sure the kernel c
202 of priority commands.
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.