1 Introduction 1 Introduction
2 ============ 2 ============
3 3
4 The FPGA subsystem supports reprogramming FPGA 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPG 5 Linux. Some of the core intentions of the FPGA subsystems are:
6 6
7 * The FPGA subsystem is vendor agnostic. 7 * The FPGA subsystem is vendor agnostic.
8 8
9 * The FPGA subsystem separates upper layers (u 9 * The FPGA subsystem separates upper layers (userspace interfaces and
10 enumeration) from lower layers that know how 10 enumeration) from lower layers that know how to program a specific
11 FPGA. 11 FPGA.
12 12
13 * Code should not be shared between upper and 13 * Code should not be shared between upper and lower layers. This
14 should go without saying. If that seems nec 14 should go without saying. If that seems necessary, there's probably
15 framework functionality that can be added th 15 framework functionality that can be added that will benefit
16 other users. Write the linux-fpga mailing l 16 other users. Write the linux-fpga mailing list and maintainers and
17 seek out a solution that expands the framewo 17 seek out a solution that expands the framework for broad reuse.
18 18
19 * Generally, when adding code, think of the fu 19 * Generally, when adding code, think of the future. Plan for reuse.
20 20
21 The framework in the kernel is divided into: 21 The framework in the kernel is divided into:
22 22
23 FPGA Manager 23 FPGA Manager
24 ------------ 24 ------------
25 25
26 If you are adding a new FPGA or a new method o 26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA 27 this is the subsystem for you. Low level FPGA manager drivers contain
28 the knowledge of how to program a specific dev 28 the knowledge of how to program a specific device. This subsystem
29 includes the framework in fpga-mgr.c and the l 29 includes the framework in fpga-mgr.c and the low level drivers that
30 are registered with it. 30 are registered with it.
31 31
32 FPGA Bridge 32 FPGA Bridge
33 ----------- 33 -----------
34 34
35 FPGA Bridges prevent spurious signals from goi 35 FPGA Bridges prevent spurious signals from going out of an FPGA or a
36 region of an FPGA during programming. They ar 36 region of an FPGA during programming. They are disabled before
37 programming begins and re-enabled afterwards. 37 programming begins and re-enabled afterwards. An FPGA bridge may be
38 actual hard hardware that gates a bus to a CPU 38 actual hard hardware that gates a bus to a CPU or a soft ("freeze")
39 bridge in FPGA fabric that surrounds a partial 39 bridge in FPGA fabric that surrounds a partial reconfiguration region
40 of an FPGA. This subsystem includes fpga-brid 40 of an FPGA. This subsystem includes fpga-bridge.c and the low level
41 drivers that are registered with it. 41 drivers that are registered with it.
42 42
43 FPGA Region 43 FPGA Region
44 ----------- 44 -----------
45 45
46 If you are adding a new interface to the FPGA 46 If you are adding a new interface to the FPGA framework, add it on top
47 of an FPGA region. 47 of an FPGA region.
48 48
49 The FPGA Region framework (fpga-region.c) asso 49 The FPGA Region framework (fpga-region.c) associates managers and
50 bridges as reconfigurable regions. A region m 50 bridges as reconfigurable regions. A region may refer to the whole
51 FPGA in full reconfiguration or to a partial r 51 FPGA in full reconfiguration or to a partial reconfiguration region.
52 52
53 The Device Tree FPGA Region support (of-fpga-r 53 The Device Tree FPGA Region support (of-fpga-region.c) handles
54 reprogramming FPGAs when device tree overlays 54 reprogramming FPGAs when device tree overlays are applied.
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