1 ==================================== 1 ====================================
2 Samsung USB 2.0 PHY adaptation layer 2 Samsung USB 2.0 PHY adaptation layer
3 ==================================== 3 ====================================
4 4
5 1. Description 5 1. Description
6 -------------- 6 --------------
7 7
8 The architecture of the USB 2.0 PHY module in 8 The architecture of the USB 2.0 PHY module in Samsung SoCs is similar
9 among many SoCs. In spite of the similarities 9 among many SoCs. In spite of the similarities it proved difficult to
10 create a one driver that would fit all these P 10 create a one driver that would fit all these PHY controllers. Often
11 the differences were minor and were found in p 11 the differences were minor and were found in particular bits of the
12 registers of the PHY. In some rare cases the o 12 registers of the PHY. In some rare cases the order of register writes or
13 the PHY powering up process had to be altered. 13 the PHY powering up process had to be altered. This adaptation layer is
14 a compromise between having separate drivers a 14 a compromise between having separate drivers and having a single driver
15 with added support for many special cases. 15 with added support for many special cases.
16 16
17 2. Files description 17 2. Files description
18 -------------------- 18 --------------------
19 19
20 - phy-samsung-usb2.c 20 - phy-samsung-usb2.c
21 This is the main file of the adaptation lay 21 This is the main file of the adaptation layer. This file contains
22 the probe function and provides two callbac 22 the probe function and provides two callbacks to the Generic PHY
23 Framework. This two callbacks are used to p 23 Framework. This two callbacks are used to power on and power off the
24 phy. They carry out the common work that ha 24 phy. They carry out the common work that has to be done on all version
25 of the PHY module. Depending on which SoC w 25 of the PHY module. Depending on which SoC was chosen they execute SoC
26 specific callbacks. The specific SoC versio 26 specific callbacks. The specific SoC version is selected by choosing
27 the appropriate compatible string. In addit 27 the appropriate compatible string. In addition, this file contains
28 struct of_device_id definitions for particu 28 struct of_device_id definitions for particular SoCs.
29 29
30 - phy-samsung-usb2.h 30 - phy-samsung-usb2.h
31 This is the include file. It declares the s 31 This is the include file. It declares the structures used by this
32 driver. In addition it should contain exter 32 driver. In addition it should contain extern declarations for
33 structures that describe particular SoCs. 33 structures that describe particular SoCs.
34 34
35 3. Supporting SoCs 35 3. Supporting SoCs
36 ------------------ 36 ------------------
37 37
38 To support a new SoC a new file should be adde 38 To support a new SoC a new file should be added to the drivers/phy
39 directory. Each SoC's configuration is stored 39 directory. Each SoC's configuration is stored in an instance of the
40 struct samsung_usb2_phy_config:: 40 struct samsung_usb2_phy_config::
41 41
42 struct samsung_usb2_phy_config { 42 struct samsung_usb2_phy_config {
43 const struct samsung_usb2_common_phy * 43 const struct samsung_usb2_common_phy *phys;
44 int (*rate_to_clk)(unsigned long, u32 44 int (*rate_to_clk)(unsigned long, u32 *);
45 unsigned int num_phys; 45 unsigned int num_phys;
46 bool has_mode_switch; 46 bool has_mode_switch;
47 }; 47 };
48 48
49 The num_phys is the number of phys handled by 49 The num_phys is the number of phys handled by the driver. `*phys` is an
50 array that contains the configuration for each 50 array that contains the configuration for each phy. The has_mode_switch
51 property is a boolean flag that determines whe 51 property is a boolean flag that determines whether the SoC has USB host
52 and device on a single pair of pins. If so, a 52 and device on a single pair of pins. If so, a special register has to
53 be modified to change the internal routing of 53 be modified to change the internal routing of these pins between a USB
54 device or host module. 54 device or host module.
55 55
56 For example the configuration for Exynos 4210 56 For example the configuration for Exynos 4210 is following::
57 57
58 const struct samsung_usb2_phy_config exynos4 58 const struct samsung_usb2_phy_config exynos4210_usb2_phy_config = {
59 .has_mode_switch = 0, 59 .has_mode_switch = 0,
60 .num_phys = EXYNOS4210_N 60 .num_phys = EXYNOS4210_NUM_PHYS,
61 .phys = exynos4210_p 61 .phys = exynos4210_phys,
62 .rate_to_clk = exynos4210_r 62 .rate_to_clk = exynos4210_rate_to_clk,
63 } 63 }
64 64
65 - `int (*rate_to_clk)(unsigned long, u32 *)` 65 - `int (*rate_to_clk)(unsigned long, u32 *)`
66 66
67 The rate_to_clk callback is to convert 67 The rate_to_clk callback is to convert the rate of the clock
68 used as the reference clock for the PH 68 used as the reference clock for the PHY module to the value
69 that should be written in the hardware 69 that should be written in the hardware register.
70 70
71 The exynos4210_phys configuration array is as 71 The exynos4210_phys configuration array is as follows::
72 72
73 static const struct samsung_usb2_common_phy 73 static const struct samsung_usb2_common_phy exynos4210_phys[] = {
74 { 74 {
75 .label = "device", 75 .label = "device",
76 .id = EXYNOS4210_D 76 .id = EXYNOS4210_DEVICE,
77 .power_on = exynos4210_p 77 .power_on = exynos4210_power_on,
78 .power_off = exynos4210_p 78 .power_off = exynos4210_power_off,
79 }, 79 },
80 { 80 {
81 .label = "host", 81 .label = "host",
82 .id = EXYNOS4210_H 82 .id = EXYNOS4210_HOST,
83 .power_on = exynos4210_p 83 .power_on = exynos4210_power_on,
84 .power_off = exynos4210_p 84 .power_off = exynos4210_power_off,
85 }, 85 },
86 { 86 {
87 .label = "hsic0", 87 .label = "hsic0",
88 .id = EXYNOS4210_H 88 .id = EXYNOS4210_HSIC0,
89 .power_on = exynos4210_p 89 .power_on = exynos4210_power_on,
90 .power_off = exynos4210_p 90 .power_off = exynos4210_power_off,
91 }, 91 },
92 { 92 {
93 .label = "hsic1", 93 .label = "hsic1",
94 .id = EXYNOS4210_H 94 .id = EXYNOS4210_HSIC1,
95 .power_on = exynos4210_p 95 .power_on = exynos4210_power_on,
96 .power_off = exynos4210_p 96 .power_off = exynos4210_power_off,
97 }, 97 },
98 {}, 98 {},
99 }; 99 };
100 100
101 - `int (*power_on)(struct samsung_usb2_phy_ins 101 - `int (*power_on)(struct samsung_usb2_phy_instance *);`
102 `int (*power_off)(struct samsung_usb2_phy_in 102 `int (*power_off)(struct samsung_usb2_phy_instance *);`
103 103
104 These two callbacks are used to power 104 These two callbacks are used to power on and power off the phy
105 by modifying appropriate registers. 105 by modifying appropriate registers.
106 106
107 Final change to the driver is adding appropria 107 Final change to the driver is adding appropriate compatible value to the
108 phy-samsung-usb2.c file. In case of Exynos 421 108 phy-samsung-usb2.c file. In case of Exynos 4210 the following lines were
109 added to the struct of_device_id samsung_usb2_ 109 added to the struct of_device_id samsung_usb2_phy_of_match[] array::
110 110
111 #ifdef CONFIG_PHY_EXYNOS4210_USB2 111 #ifdef CONFIG_PHY_EXYNOS4210_USB2
112 { 112 {
113 .compatible = "samsung,exynos4 113 .compatible = "samsung,exynos4210-usb2-phy",
114 .data = &exynos4210_usb2_phy_c 114 .data = &exynos4210_usb2_phy_config,
115 }, 115 },
116 #endif 116 #endif
117 117
118 To add further flexibility to the driver the K 118 To add further flexibility to the driver the Kconfig file enables to
119 include support for selected SoCs in the compi 119 include support for selected SoCs in the compiled driver. The Kconfig
120 entry for Exynos 4210 is following:: 120 entry for Exynos 4210 is following::
121 121
122 config PHY_EXYNOS4210_USB2 122 config PHY_EXYNOS4210_USB2
123 bool "Support for Exynos 4210" 123 bool "Support for Exynos 4210"
124 depends on PHY_SAMSUNG_USB2 124 depends on PHY_SAMSUNG_USB2
125 depends on CPU_EXYNOS4210 125 depends on CPU_EXYNOS4210
126 help 126 help
127 Enable USB PHY support for Exynos 42 127 Enable USB PHY support for Exynos 4210. This option requires that
128 Samsung USB 2.0 PHY driver is enable 128 Samsung USB 2.0 PHY driver is enabled and means that support for this
129 particular SoC is compiled in the dr 129 particular SoC is compiled in the driver. In case of Exynos 4210 four
130 phys are available - device, host, H 130 phys are available - device, host, HSCI0 and HSCI1.
131 131
132 The newly created file that supports the new S 132 The newly created file that supports the new SoC has to be also added to the
133 Makefile. In case of Exynos 4210 the added lin 133 Makefile. In case of Exynos 4210 the added line is following::
134 134
135 obj-$(CONFIG_PHY_EXYNOS4210_USB2) += p 135 obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
136 136
137 After completing these steps the support for t 137 After completing these steps the support for the new SoC should be ready.
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