1 ====================================
2 Samsung USB 2.0 PHY adaptation layer
3 ====================================
4
5 1. Description
6 --------------
7
8 The architecture of the USB 2.0 PHY module in
9 among many SoCs. In spite of the similarities
10 create a one driver that would fit all these P
11 the differences were minor and were found in p
12 registers of the PHY. In some rare cases the o
13 the PHY powering up process had to be altered.
14 a compromise between having separate drivers a
15 with added support for many special cases.
16
17 2. Files description
18 --------------------
19
20 - phy-samsung-usb2.c
21 This is the main file of the adaptation lay
22 the probe function and provides two callbac
23 Framework. This two callbacks are used to p
24 phy. They carry out the common work that ha
25 of the PHY module. Depending on which SoC w
26 specific callbacks. The specific SoC versio
27 the appropriate compatible string. In addit
28 struct of_device_id definitions for particu
29
30 - phy-samsung-usb2.h
31 This is the include file. It declares the s
32 driver. In addition it should contain exter
33 structures that describe particular SoCs.
34
35 3. Supporting SoCs
36 ------------------
37
38 To support a new SoC a new file should be adde
39 directory. Each SoC's configuration is stored
40 struct samsung_usb2_phy_config::
41
42 struct samsung_usb2_phy_config {
43 const struct samsung_usb2_common_phy *
44 int (*rate_to_clk)(unsigned long, u32
45 unsigned int num_phys;
46 bool has_mode_switch;
47 };
48
49 The num_phys is the number of phys handled by
50 array that contains the configuration for each
51 property is a boolean flag that determines whe
52 and device on a single pair of pins. If so, a
53 be modified to change the internal routing of
54 device or host module.
55
56 For example the configuration for Exynos 4210
57
58 const struct samsung_usb2_phy_config exynos4
59 .has_mode_switch = 0,
60 .num_phys = EXYNOS4210_N
61 .phys = exynos4210_p
62 .rate_to_clk = exynos4210_r
63 }
64
65 - `int (*rate_to_clk)(unsigned long, u32 *)`
66
67 The rate_to_clk callback is to convert
68 used as the reference clock for the PH
69 that should be written in the hardware
70
71 The exynos4210_phys configuration array is as
72
73 static const struct samsung_usb2_common_phy
74 {
75 .label = "device",
76 .id = EXYNOS4210_D
77 .power_on = exynos4210_p
78 .power_off = exynos4210_p
79 },
80 {
81 .label = "host",
82 .id = EXYNOS4210_H
83 .power_on = exynos4210_p
84 .power_off = exynos4210_p
85 },
86 {
87 .label = "hsic0",
88 .id = EXYNOS4210_H
89 .power_on = exynos4210_p
90 .power_off = exynos4210_p
91 },
92 {
93 .label = "hsic1",
94 .id = EXYNOS4210_H
95 .power_on = exynos4210_p
96 .power_off = exynos4210_p
97 },
98 {},
99 };
100
101 - `int (*power_on)(struct samsung_usb2_phy_ins
102 `int (*power_off)(struct samsung_usb2_phy_in
103
104 These two callbacks are used to power
105 by modifying appropriate registers.
106
107 Final change to the driver is adding appropria
108 phy-samsung-usb2.c file. In case of Exynos 421
109 added to the struct of_device_id samsung_usb2_
110
111 #ifdef CONFIG_PHY_EXYNOS4210_USB2
112 {
113 .compatible = "samsung,exynos4
114 .data = &exynos4210_usb2_phy_c
115 },
116 #endif
117
118 To add further flexibility to the driver the K
119 include support for selected SoCs in the compi
120 entry for Exynos 4210 is following::
121
122 config PHY_EXYNOS4210_USB2
123 bool "Support for Exynos 4210"
124 depends on PHY_SAMSUNG_USB2
125 depends on CPU_EXYNOS4210
126 help
127 Enable USB PHY support for Exynos 42
128 Samsung USB 2.0 PHY driver is enable
129 particular SoC is compiled in the dr
130 phys are available - device, host, H
131
132 The newly created file that supports the new S
133 Makefile. In case of Exynos 4210 the added lin
134
135 obj-$(CONFIG_PHY_EXYNOS4210_USB2) += p
136
137 After completing these steps the support for t
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