1 ========================= 1 =========================
2 Audio Stream in SoundWire 2 Audio Stream in SoundWire
3 ========================= 3 =========================
4 4
5 An audio stream is a logical or virtual connec 5 An audio stream is a logical or virtual connection created between
6 6
7 (1) System memory buffer(s) and Codec(s) 7 (1) System memory buffer(s) and Codec(s)
8 8
9 (2) DSP memory buffer(s) and Codec(s) 9 (2) DSP memory buffer(s) and Codec(s)
10 10
11 (3) FIFO(s) and Codec(s) 11 (3) FIFO(s) and Codec(s)
12 12
13 (4) Codec(s) and Codec(s) 13 (4) Codec(s) and Codec(s)
14 14
15 which is typically driven by a DMA(s) channel 15 which is typically driven by a DMA(s) channel through the data link. An
16 audio stream contains one or more channels of 16 audio stream contains one or more channels of data. All channels within
17 stream must have same sample rate and same sam 17 stream must have same sample rate and same sample size.
18 18
19 Assume a stream with two channels (Left & Righ 19 Assume a stream with two channels (Left & Right) is opened using SoundWire
20 interface. Below are some ways a stream can be 20 interface. Below are some ways a stream can be represented in SoundWire.
21 21
22 Stream Sample in memory (System memory, DSP me 22 Stream Sample in memory (System memory, DSP memory or FIFOs) ::
23 23
24 ------------------------- 24 -------------------------
25 | L | R | L | R | L | R | 25 | L | R | L | R | L | R |
26 ------------------------- 26 -------------------------
27 27
28 Example 1: Stereo Stream with L and R channels 28 Example 1: Stereo Stream with L and R channels is rendered from Master to
29 Slave. Both Master and Slave is using single p 29 Slave. Both Master and Slave is using single port. ::
30 30
31 +---------------+ C 31 +---------------+ Clock Signal +---------------+
32 | Master +--------------------- 32 | Master +----------------------------------+ Slave |
33 | Interface | 33 | Interface | | Interface |
34 | | 34 | | | 1 |
35 | | 35 | | Data Signal | |
36 | L + R +--------------------- 36 | L + R +----------------------------------+ L + R |
37 | (Data) | Data Direction 37 | (Data) | Data Direction | (Data) |
38 +---------------+ +------------------ 38 +---------------+ +-----------------------> +---------------+
39 39
40 40
41 Example 2: Stereo Stream with L and R channels 41 Example 2: Stereo Stream with L and R channels is captured from Slave to
42 Master. Both Master and Slave is using single 42 Master. Both Master and Slave is using single port. ::
43 43
44 44
45 +---------------+ C 45 +---------------+ Clock Signal +---------------+
46 | Master +--------------------- 46 | Master +----------------------------------+ Slave |
47 | Interface | 47 | Interface | | Interface |
48 | | 48 | | | 1 |
49 | | 49 | | Data Signal | |
50 | L + R +--------------------- 50 | L + R +----------------------------------+ L + R |
51 | (Data) | Data Direction 51 | (Data) | Data Direction | (Data) |
52 +---------------+ <------------------ 52 +---------------+ <-----------------------+ +---------------+
53 53
54 54
55 Example 3: Stereo Stream with L and R channels 55 Example 3: Stereo Stream with L and R channels is rendered by Master. Each
56 of the L and R channel is received by two diff 56 of the L and R channel is received by two different Slaves. Master and both
57 Slaves are using single port. :: 57 Slaves are using single port. ::
58 58
59 +---------------+ C 59 +---------------+ Clock Signal +---------------+
60 | Master +---------+----------- 60 | Master +---------+------------------------+ Slave |
61 | Interface | | 61 | Interface | | | Interface |
62 | | | 62 | | | | 1 |
63 | | | 63 | | | Data Signal | |
64 | L + R +---+----------------- 64 | L + R +---+------------------------------+ L |
65 | (Data) | | | Data Di 65 | (Data) | | | Data Direction | (Data) |
66 +---------------+ | | +------- 66 +---------------+ | | +-------------> +---------------+
67 | | 67 | |
68 | | 68 | |
69 | | 69 | | +---------------+
70 | +----------- 70 | +----------------------> | Slave |
71 | 71 | | Interface |
72 | 72 | | 2 |
73 | 73 | | |
74 +----------------- 74 +----------------------------> | R |
75 75 | (Data) |
76 76 +---------------+
77 77
78 Example 4: Stereo Stream with L and R channels <<
79 Master. Both of the L and R channels are recei <<
80 Slaves. Master and both Slaves are using singl <<
81 L+R. Each Slave device processes the L + R dat <<
82 based on static configuration or dynamic orien <<
83 one or more speakers. :: <<
84 <<
85 +---------------+ C <<
86 | Master +---------+----------- <<
87 | Interface | | <<
88 | | | <<
89 | | | <<
90 | L + R +---+----------------- <<
91 | (Data) | | | Data Di <<
92 +---------------+ | | +------- <<
93 | | <<
94 | | <<
95 | | <<
96 | +----------- <<
97 | <<
98 | <<
99 | <<
100 +----------------- <<
101 <<
102 <<
103 78
104 Example 5: Stereo Stream with L and R channel !! 79 Example 4: Stereo Stream with L and R channel is rendered by two different
105 Ports of the Master and is received by only si 80 Ports of the Master and is received by only single Port of the Slave
106 interface. :: 81 interface. ::
107 82
108 +--------------------+ 83 +--------------------+
109 | | 84 | |
110 | +--------------+ 85 | +--------------+ +----------------+
111 | | || 86 | | || | |
112 | | Data Port || L Channel 87 | | Data Port || L Channel | |
113 | | 1 |------------+ 88 | | 1 |------------+ | |
114 | | L Channel || | 89 | | L Channel || | +-----+----+ |
115 | | (Data) || | L 90 | | (Data) || | L + R Channel || Data | |
116 | Master +----------+ | +-- 91 | Master +----------+ | +---+---------> || Port | |
117 | Interface | | 92 | Interface | | || 1 | |
118 | +--------------+ | 93 | +--------------+ | || | |
119 | | || | 94 | | || | +----------+ |
120 | | Data Port |------------+ 95 | | Data Port |------------+ | |
121 | | 2 || R Channel 96 | | 2 || R Channel | Slave |
122 | | R Channel || 97 | | R Channel || | Interface |
123 | | (Data) || 98 | | (Data) || | 1 |
124 | +--------------+ Clock S 99 | +--------------+ Clock Signal | L + R |
125 | +---------------- 100 | +---------------------------> | (Data) |
126 +--------------------+ 101 +--------------------+ | |
127 102 +----------------+
128 103
129 Example 6: Stereo Stream with L and R channel <<
130 rendering one channel, and is received by two <<
131 receiving one channel. Both Masters and both S <<
132 <<
133 +---------------+ C <<
134 | Master +--------------------- <<
135 | Interface | <<
136 | 1 | <<
137 | | <<
138 | L +--------------------- <<
139 | (Data) | Data Direction <<
140 +---------------+ +------------------ <<
141 <<
142 +---------------+ C <<
143 | Master +--------------------- <<
144 | Interface | <<
145 | 2 | <<
146 | | <<
147 | R +--------------------- <<
148 | (Data) | Data Direction <<
149 +---------------+ +------------------ <<
150 <<
151 Example 7: Stereo Stream with L and R channel <<
152 Masters, each rendering both channels. Each Sl <<
153 is the same application as Example 4 but with <<
154 separate links. :: <<
155 <<
156 +---------------+ C <<
157 | Master +--------------------- <<
158 | Interface | <<
159 | 1 | <<
160 | | <<
161 | L + R +--------------------- <<
162 | (Data) | Data Direction <<
163 +---------------+ +------------------ <<
164 <<
165 +---------------+ C <<
166 | Master +--------------------- <<
167 | Interface | <<
168 | 2 | <<
169 | | <<
170 | L + R +--------------------- <<
171 | (Data) | Data Direction <<
172 +---------------+ +------------------ <<
173 <<
174 Example 8: 4-channel Stream is rendered by 2 M <<
175 2 channels. Each Slave receives 2 channels. :: <<
176 <<
177 +---------------+ C <<
178 | Master +--------------------- <<
179 | Interface | <<
180 | 1 | <<
181 | | <<
182 | L1 + R1 +--------------------- <<
183 | (Data) | Data Direction <<
184 +---------------+ +------------------ <<
185 <<
186 +---------------+ C <<
187 | Master +--------------------- <<
188 | Interface | <<
189 | 2 | <<
190 | | <<
191 | L2 + R2 +--------------------- <<
192 | (Data) | Data Direction <<
193 +---------------+ +------------------ <<
194 <<
195 Note1: In multi-link cases like above, to lock <<
196 lock and then go on locking bus instances. But <<
197 framework(ASoC DPCM) guarantees that stream op <<
198 always serialized. So, there is no race condit <<
199 global lock. <<
200 <<
201 Note2: A Slave device may be configured to rec <<
202 transmitted on a link for a given Stream (Exam <<
203 of the data (Example 3). The configuration of <<
204 handled by a SoundWire subsystem API, but inst <<
205 snd_soc_dai_set_tdm_slot() API. The platform o <<
206 typically configure which of the slots are use <<
207 same slots would be used by all Devices, while <<
208 Device1 would use e.g. Slot 0 and Slave device <<
209 <<
210 Note3: Multiple Sink ports can extract the sam <<
211 same bitSlots in the SoundWire frame, however <<
212 shall be configured with different bitSlot con <<
213 same limitation as with I2S/PCM TDM usages. <<
214 <<
215 SoundWire Stream Management flow 104 SoundWire Stream Management flow
216 ================================ 105 ================================
217 106
218 Stream definitions 107 Stream definitions
219 ------------------ 108 ------------------
220 109
221 (1) Current stream: This is classified as th 110 (1) Current stream: This is classified as the stream on which operation has
222 to be performed like prepare, enable, di 111 to be performed like prepare, enable, disable, de-prepare etc.
223 112
224 (2) Active stream: This is classified as the 113 (2) Active stream: This is classified as the stream which is already active
225 on Bus other than current stream. There 114 on Bus other than current stream. There can be multiple active streams
226 on the Bus. 115 on the Bus.
227 116
228 SoundWire Bus manages stream operations for ea 117 SoundWire Bus manages stream operations for each stream getting
229 rendered/captured on the SoundWire Bus. This s 118 rendered/captured on the SoundWire Bus. This section explains Bus operations
230 done for each of the stream allocated/released 119 done for each of the stream allocated/released on Bus. Following are the
231 stream states maintained by the Bus for each o 120 stream states maintained by the Bus for each of the audio stream.
232 121
233 122
234 SoundWire stream states 123 SoundWire stream states
235 ----------------------- 124 -----------------------
236 125
237 Below shows the SoundWire stream states and st 126 Below shows the SoundWire stream states and state transition diagram. ::
238 127
239 +-----------+ +------------+ + 128 +-----------+ +------------+ +----------+ +----------+
240 | ALLOCATED +---->| CONFIGURED +---->| 129 | ALLOCATED +---->| CONFIGURED +---->| PREPARED +---->| ENABLED |
241 | STATE | | STATE | | 130 | STATE | | STATE | | STATE | | STATE |
242 +-----------+ +------------+ + !! 131 +-----------+ +------------+ +----------+ +----+-----+
243 !! 132 ^
244 !! 133 |
245 !! 134 |
246 !! 135 v
247 !! 136 +----------+ +------------+ +----+-----+
248 +----------+ +----- <<
249 | RELEASED |<----------+ DEPR 137 | RELEASED |<----------+ DEPREPARED |<-------+ DISABLED |
250 | STATE | | ST 138 | STATE | | STATE | | STATE |
251 +----------+ +----- 139 +----------+ +------------+ +----------+
252 140
253 NOTE: State transitions between ``SDW_STREAM_E !! 141 NOTE: State transition between prepare and deprepare is supported in Spec
254 ``SDW_STREAM_DISABLED`` are only relevant when !! 142 but not in the software (subsystem)
255 supported at the ALSA/ASoC level. Likewise the !! 143
256 ``SDW_DISABLED_STATE`` and ``SDW_PREPARED_STAT !! 144 NOTE2: Stream state transition checks need to be handled by caller
257 INFO_RESUME flag. !! 145 framework, for example ALSA/ASoC. No checks for stream transition exist in
258 !! 146 SoundWire subsystem.
259 NOTE2: The framework implements basic state tr <<
260 does not e.g. check if a transition from DISAB <<
261 on a specific platform. Such tests need to be <<
262 level. <<
263 147
264 Stream State Operations 148 Stream State Operations
265 ----------------------- 149 -----------------------
266 150
267 Below section explains the operations done by 151 Below section explains the operations done by the Bus on Master(s) and
268 Slave(s) as part of stream state transitions. 152 Slave(s) as part of stream state transitions.
269 153
270 SDW_STREAM_ALLOCATED 154 SDW_STREAM_ALLOCATED
271 ~~~~~~~~~~~~~~~~~~~~ 155 ~~~~~~~~~~~~~~~~~~~~
272 156
273 Allocation state for stream. This is the entry 157 Allocation state for stream. This is the entry state
274 of the stream. Operations performed before ent 158 of the stream. Operations performed before entering in this state:
275 159
276 (1) A stream runtime is allocated for the st 160 (1) A stream runtime is allocated for the stream. This stream
277 runtime is used as a reference for all t 161 runtime is used as a reference for all the operations performed
278 on the stream. 162 on the stream.
279 163
280 (2) The resources required for holding strea 164 (2) The resources required for holding stream runtime information are
281 allocated and initialized. This holds al 165 allocated and initialized. This holds all stream related information
282 such as stream type (PCM/PDM) and parame 166 such as stream type (PCM/PDM) and parameters, Master and Slave
283 interface associated with the stream, st 167 interface associated with the stream, stream state etc.
284 168
285 After all above operations are successful, str 169 After all above operations are successful, stream state is set to
286 ``SDW_STREAM_ALLOCATED``. 170 ``SDW_STREAM_ALLOCATED``.
287 171
288 Bus implements below API for allocate a stream 172 Bus implements below API for allocate a stream which needs to be called once
289 per stream. From ASoC DPCM framework, this str 173 per stream. From ASoC DPCM framework, this stream state maybe linked to
290 .startup() operation. 174 .startup() operation.
291 175
292 .. code-block:: c !! 176 .. code-block:: c
293 <<
294 int sdw_alloc_stream(char * stream_name); 177 int sdw_alloc_stream(char * stream_name);
295 178
296 The SoundWire core provides a sdw_startup_stre <<
297 typically called during a dailink .startup() c <<
298 stream allocation and sets the stream pointer <<
299 connected to a stream. <<
300 179
301 SDW_STREAM_CONFIGURED 180 SDW_STREAM_CONFIGURED
302 ~~~~~~~~~~~~~~~~~~~~~ 181 ~~~~~~~~~~~~~~~~~~~~~
303 182
304 Configuration state of stream. Operations perf 183 Configuration state of stream. Operations performed before entering in
305 this state: 184 this state:
306 185
307 (1) The resources allocated for stream infor 186 (1) The resources allocated for stream information in SDW_STREAM_ALLOCATED
308 state are updated here. This includes st 187 state are updated here. This includes stream parameters, Master(s)
309 and Slave(s) runtime information associa 188 and Slave(s) runtime information associated with current stream.
310 189
311 (2) All the Master(s) and Slave(s) associate 190 (2) All the Master(s) and Slave(s) associated with current stream provide
312 the port information to Bus which includ 191 the port information to Bus which includes port numbers allocated by
313 Master(s) and Slave(s) for current strea 192 Master(s) and Slave(s) for current stream and their channel mask.
314 193
315 After all above operations are successful, str 194 After all above operations are successful, stream state is set to
316 ``SDW_STREAM_CONFIGURED``. 195 ``SDW_STREAM_CONFIGURED``.
317 196
318 Bus implements below APIs for CONFIG state whi 197 Bus implements below APIs for CONFIG state which needs to be called by
319 the respective Master(s) and Slave(s) associat 198 the respective Master(s) and Slave(s) associated with stream. These APIs can
320 only be invoked once by respective Master(s) a 199 only be invoked once by respective Master(s) and Slave(s). From ASoC DPCM
321 framework, this stream state is linked to .hw_ 200 framework, this stream state is linked to .hw_params() operation.
322 201
323 .. code-block:: c !! 202 .. code-block:: c
324 <<
325 int sdw_stream_add_master(struct sdw_bus * b 203 int sdw_stream_add_master(struct sdw_bus * bus,
326 struct sdw_stream_config * str 204 struct sdw_stream_config * stream_config,
327 const struct sdw_ports_config !! 205 struct sdw_ports_config * ports_config,
328 struct sdw_stream_runtime * st 206 struct sdw_stream_runtime * stream);
329 207
330 int sdw_stream_add_slave(struct sdw_slave * 208 int sdw_stream_add_slave(struct sdw_slave * slave,
331 struct sdw_stream_config * str 209 struct sdw_stream_config * stream_config,
332 const struct sdw_ports_config !! 210 struct sdw_ports_config * ports_config,
333 struct sdw_stream_runtime * st 211 struct sdw_stream_runtime * stream);
334 212
335 213
336 SDW_STREAM_PREPARED 214 SDW_STREAM_PREPARED
337 ~~~~~~~~~~~~~~~~~~~ 215 ~~~~~~~~~~~~~~~~~~~
338 216
339 Prepare state of stream. Operations performed 217 Prepare state of stream. Operations performed before entering in this state:
340 218
341 (0) Steps 1 and 2 are omitted in the case of <<
342 where the bus bandwidth is known. <<
343 <<
344 (1) Bus parameters such as bandwidth, frame 219 (1) Bus parameters such as bandwidth, frame shape, clock frequency,
345 are computed based on current stream as 220 are computed based on current stream as well as already active
346 stream(s) on Bus. Re-computation is requ 221 stream(s) on Bus. Re-computation is required to accommodate current
347 stream on the Bus. 222 stream on the Bus.
348 223
349 (2) Transport and port parameters of all Mas 224 (2) Transport and port parameters of all Master(s) and Slave(s) port(s) are
350 computed for the current as well as alre 225 computed for the current as well as already active stream based on frame
351 shape and clock frequency computed in st 226 shape and clock frequency computed in step 1.
352 227
353 (3) Computed Bus and transport parameters ar 228 (3) Computed Bus and transport parameters are programmed in Master(s) and
354 Slave(s) registers. The banked registers 229 Slave(s) registers. The banked registers programming is done on the
355 alternate bank (bank currently unused). 230 alternate bank (bank currently unused). Port(s) are enabled for the
356 already active stream(s) on the alternat 231 already active stream(s) on the alternate bank (bank currently unused).
357 This is done in order to not disrupt alr 232 This is done in order to not disrupt already active stream(s).
358 233
359 (4) Once all the values are programmed, Bus 234 (4) Once all the values are programmed, Bus initiates switch to alternate
360 bank where all new values programmed get 235 bank where all new values programmed gets into effect.
361 236
362 (5) Ports of Master(s) and Slave(s) for curr 237 (5) Ports of Master(s) and Slave(s) for current stream are prepared by
363 programming PrepareCtrl register. 238 programming PrepareCtrl register.
364 239
365 After all above operations are successful, str 240 After all above operations are successful, stream state is set to
366 ``SDW_STREAM_PREPARED``. 241 ``SDW_STREAM_PREPARED``.
367 242
368 Bus implements below API for PREPARE state whi !! 243 Bus implements below API for PREPARE state which needs to be called once per
369 once per stream. From ASoC DPCM framework, thi !! 244 stream. From ASoC DPCM framework, this stream state is linked to
370 to .prepare() operation. Since the .trigger() !! 245 .prepare() operation.
371 follow the .prepare(), a direct transition fro <<
372 ``SDW_STREAM_PREPARED`` to ``SDW_STREAM_DEPREP <<
373 <<
374 .. code-block:: c <<
375 246
>> 247 .. code-block:: c
376 int sdw_prepare_stream(struct sdw_stream_run 248 int sdw_prepare_stream(struct sdw_stream_runtime * stream);
377 249
378 250
379 SDW_STREAM_ENABLED 251 SDW_STREAM_ENABLED
380 ~~~~~~~~~~~~~~~~~~ 252 ~~~~~~~~~~~~~~~~~~
381 253
382 Enable state of stream. The data port(s) are e 254 Enable state of stream. The data port(s) are enabled upon entering this state.
383 Operations performed before entering in this s 255 Operations performed before entering in this state:
384 256
385 (1) All the values computed in SDW_STREAM_PR 257 (1) All the values computed in SDW_STREAM_PREPARED state are programmed
386 in alternate bank (bank currently unused 258 in alternate bank (bank currently unused). It includes programming of
387 already active stream(s) as well. 259 already active stream(s) as well.
388 260
389 (2) All the Master(s) and Slave(s) port(s) f 261 (2) All the Master(s) and Slave(s) port(s) for the current stream are
390 enabled on alternate bank (bank currentl 262 enabled on alternate bank (bank currently unused) by programming
391 ChannelEn register. 263 ChannelEn register.
392 264
393 (3) Once all the values are programmed, Bus 265 (3) Once all the values are programmed, Bus initiates switch to alternate
394 bank where all new values programmed get 266 bank where all new values programmed gets into effect and port(s)
395 associated with current stream are enabl 267 associated with current stream are enabled.
396 268
397 After all above operations are successful, str 269 After all above operations are successful, stream state is set to
398 ``SDW_STREAM_ENABLED``. 270 ``SDW_STREAM_ENABLED``.
399 271
400 Bus implements below API for ENABLE state whic 272 Bus implements below API for ENABLE state which needs to be called once per
401 stream. From ASoC DPCM framework, this stream 273 stream. From ASoC DPCM framework, this stream state is linked to
402 .trigger() start operation. 274 .trigger() start operation.
403 275
404 .. code-block:: c !! 276 .. code-block:: c
405 <<
406 int sdw_enable_stream(struct sdw_stream_runt 277 int sdw_enable_stream(struct sdw_stream_runtime * stream);
407 278
408 SDW_STREAM_DISABLED 279 SDW_STREAM_DISABLED
409 ~~~~~~~~~~~~~~~~~~~ 280 ~~~~~~~~~~~~~~~~~~~
410 281
411 Disable state of stream. The data port(s) are 282 Disable state of stream. The data port(s) are disabled upon exiting this state.
412 Operations performed before entering in this s 283 Operations performed before entering in this state:
413 284
414 (1) All the Master(s) and Slave(s) port(s) f 285 (1) All the Master(s) and Slave(s) port(s) for the current stream are
415 disabled on alternate bank (bank current 286 disabled on alternate bank (bank currently unused) by programming
416 ChannelEn register. 287 ChannelEn register.
417 288
418 (2) All the current configuration of Bus and 289 (2) All the current configuration of Bus and active stream(s) are programmed
419 into alternate bank (bank currently unus 290 into alternate bank (bank currently unused).
420 291
421 (3) Once all the values are programmed, Bus 292 (3) Once all the values are programmed, Bus initiates switch to alternate
422 bank where all new values programmed get 293 bank where all new values programmed gets into effect and port(s) associated
423 with current stream are disabled. 294 with current stream are disabled.
424 295
425 After all above operations are successful, str 296 After all above operations are successful, stream state is set to
426 ``SDW_STREAM_DISABLED``. 297 ``SDW_STREAM_DISABLED``.
427 298
428 Bus implements below API for DISABLED state wh 299 Bus implements below API for DISABLED state which needs to be called once
429 per stream. From ASoC DPCM framework, this str 300 per stream. From ASoC DPCM framework, this stream state is linked to
430 .trigger() stop operation. 301 .trigger() stop operation.
431 302
432 When the INFO_PAUSE flag is supported, a direc !! 303 .. code-block:: c
433 ``SDW_STREAM_ENABLED`` is allowed. <<
434 <<
435 For resume operations where ASoC will use the <<
436 stream can transition from ``SDW_STREAM_DISABL <<
437 ``SDW_STREAM_PREPARED``, with all required set <<
438 without updating the bandwidth and bit allocat <<
439 <<
440 .. code-block:: c <<
441 <<
442 int sdw_disable_stream(struct sdw_stream_run 304 int sdw_disable_stream(struct sdw_stream_runtime * stream);
443 305
444 306
445 SDW_STREAM_DEPREPARED 307 SDW_STREAM_DEPREPARED
446 ~~~~~~~~~~~~~~~~~~~~~ 308 ~~~~~~~~~~~~~~~~~~~~~
447 309
448 De-prepare state of stream. Operations perform 310 De-prepare state of stream. Operations performed before entering in this
449 state: 311 state:
450 312
451 (1) All the port(s) of Master(s) and Slave(s 313 (1) All the port(s) of Master(s) and Slave(s) for current stream are
452 de-prepared by programming PrepareCtrl r 314 de-prepared by programming PrepareCtrl register.
453 315
454 (2) The payload bandwidth of current stream 316 (2) The payload bandwidth of current stream is reduced from the total
455 bandwidth requirement of bus and new par 317 bandwidth requirement of bus and new parameters calculated and
456 applied by performing bank switch etc. 318 applied by performing bank switch etc.
457 319
458 After all above operations are successful, str 320 After all above operations are successful, stream state is set to
459 ``SDW_STREAM_DEPREPARED``. 321 ``SDW_STREAM_DEPREPARED``.
460 322
461 Bus implements below API for DEPREPARED state !! 323 Bus implements below API for DEPREPARED state which needs to be called once
462 once per stream. ALSA/ASoC do not have a conce !! 324 per stream. From ASoC DPCM framework, this stream state is linked to
463 the mapping from this stream state to ALSA/ASo !! 325 .trigger() stop operation.
464 implementation specific. <<
465 <<
466 When the INFO_PAUSE flag is supported, the str <<
467 the .hw_free() operation - the stream is not d <<
468 TRIGGER_STOP. <<
469 <<
470 Other implementations may transition to the `` <<
471 state on TRIGGER_STOP, should they require a t <<
472 ``SDW_STREAM_PREPARED`` state. <<
473 <<
474 .. code-block:: c <<
475 326
>> 327 .. code-block:: c
476 int sdw_deprepare_stream(struct sdw_stream_r 328 int sdw_deprepare_stream(struct sdw_stream_runtime * stream);
477 329
478 330
479 SDW_STREAM_RELEASED 331 SDW_STREAM_RELEASED
480 ~~~~~~~~~~~~~~~~~~~ 332 ~~~~~~~~~~~~~~~~~~~
481 333
482 Release state of stream. Operations performed 334 Release state of stream. Operations performed before entering in this state:
483 335
484 (1) Release port resources for all Master(s) 336 (1) Release port resources for all Master(s) and Slave(s) port(s)
485 associated with current stream. 337 associated with current stream.
486 338
487 (2) Release Master(s) and Slave(s) runtime r 339 (2) Release Master(s) and Slave(s) runtime resources associated with
488 current stream. 340 current stream.
489 341
490 (3) Release stream runtime resources associa 342 (3) Release stream runtime resources associated with current stream.
491 343
492 After all above operations are successful, str 344 After all above operations are successful, stream state is set to
493 ``SDW_STREAM_RELEASED``. 345 ``SDW_STREAM_RELEASED``.
494 346
495 Bus implements below APIs for RELEASE state wh 347 Bus implements below APIs for RELEASE state which needs to be called by
496 all the Master(s) and Slave(s) associated with 348 all the Master(s) and Slave(s) associated with stream. From ASoC DPCM
497 framework, this stream state is linked to .hw_ 349 framework, this stream state is linked to .hw_free() operation.
498 350
499 .. code-block:: c !! 351 .. code-block:: c
500 <<
501 int sdw_stream_remove_master(struct sdw_bus 352 int sdw_stream_remove_master(struct sdw_bus * bus,
502 struct sdw_stream_runtime * st 353 struct sdw_stream_runtime * stream);
503 int sdw_stream_remove_slave(struct sdw_slave 354 int sdw_stream_remove_slave(struct sdw_slave * slave,
504 struct sdw_stream_runtime * st 355 struct sdw_stream_runtime * stream);
505 356
506 357
507 The .shutdown() ASoC DPCM operation calls belo 358 The .shutdown() ASoC DPCM operation calls below Bus API to release
508 stream assigned as part of ALLOCATED state. 359 stream assigned as part of ALLOCATED state.
509 360
510 In .shutdown() the data structure maintaining 361 In .shutdown() the data structure maintaining stream state are freed up.
511 362
512 .. code-block:: c !! 363 .. code-block:: c
513 <<
514 void sdw_release_stream(struct sdw_stream_ru 364 void sdw_release_stream(struct sdw_stream_runtime * stream);
515 365
516 The SoundWire core provides a sdw_shutdown_str <<
517 typically called during a dailink .shutdown() <<
518 the stream pointer for all DAIS connected to a <<
519 memory allocated for the stream. <<
520 <<
521 Not Supported 366 Not Supported
522 ============= 367 =============
523 368
524 1. A single port with multiple channels suppor 369 1. A single port with multiple channels supported cannot be used between two
525 streams or across stream. For example a por !! 370 streams or across stream. For example a port with 4 channels cannot be used
526 to handle 2 independent stereo streams even !! 371 to handle 2 independent stereo streams even though it's possible in theory
527 in SoundWire. !! 372 in SoundWire.
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.