1 ========================= 1 =========================
2 Audio Stream in SoundWire 2 Audio Stream in SoundWire
3 ========================= 3 =========================
4 4
5 An audio stream is a logical or virtual connec 5 An audio stream is a logical or virtual connection created between
6 6
7 (1) System memory buffer(s) and Codec(s) 7 (1) System memory buffer(s) and Codec(s)
8 8
9 (2) DSP memory buffer(s) and Codec(s) 9 (2) DSP memory buffer(s) and Codec(s)
10 10
11 (3) FIFO(s) and Codec(s) 11 (3) FIFO(s) and Codec(s)
12 12
13 (4) Codec(s) and Codec(s) 13 (4) Codec(s) and Codec(s)
14 14
15 which is typically driven by a DMA(s) channel 15 which is typically driven by a DMA(s) channel through the data link. An
16 audio stream contains one or more channels of 16 audio stream contains one or more channels of data. All channels within
17 stream must have same sample rate and same sam 17 stream must have same sample rate and same sample size.
18 18
19 Assume a stream with two channels (Left & Righ 19 Assume a stream with two channels (Left & Right) is opened using SoundWire
20 interface. Below are some ways a stream can be 20 interface. Below are some ways a stream can be represented in SoundWire.
21 21
22 Stream Sample in memory (System memory, DSP me 22 Stream Sample in memory (System memory, DSP memory or FIFOs) ::
23 23
24 ------------------------- 24 -------------------------
25 | L | R | L | R | L | R | 25 | L | R | L | R | L | R |
26 ------------------------- 26 -------------------------
27 27
28 Example 1: Stereo Stream with L and R channels 28 Example 1: Stereo Stream with L and R channels is rendered from Master to
29 Slave. Both Master and Slave is using single p 29 Slave. Both Master and Slave is using single port. ::
30 30
31 +---------------+ C 31 +---------------+ Clock Signal +---------------+
32 | Master +--------------------- 32 | Master +----------------------------------+ Slave |
33 | Interface | 33 | Interface | | Interface |
34 | | 34 | | | 1 |
35 | | 35 | | Data Signal | |
36 | L + R +--------------------- 36 | L + R +----------------------------------+ L + R |
37 | (Data) | Data Direction 37 | (Data) | Data Direction | (Data) |
38 +---------------+ +------------------ 38 +---------------+ +-----------------------> +---------------+
39 39
40 40
41 Example 2: Stereo Stream with L and R channels 41 Example 2: Stereo Stream with L and R channels is captured from Slave to
42 Master. Both Master and Slave is using single 42 Master. Both Master and Slave is using single port. ::
43 43
44 44
45 +---------------+ C 45 +---------------+ Clock Signal +---------------+
46 | Master +--------------------- 46 | Master +----------------------------------+ Slave |
47 | Interface | 47 | Interface | | Interface |
48 | | 48 | | | 1 |
49 | | 49 | | Data Signal | |
50 | L + R +--------------------- 50 | L + R +----------------------------------+ L + R |
51 | (Data) | Data Direction 51 | (Data) | Data Direction | (Data) |
52 +---------------+ <------------------ 52 +---------------+ <-----------------------+ +---------------+
53 53
54 54
55 Example 3: Stereo Stream with L and R channels 55 Example 3: Stereo Stream with L and R channels is rendered by Master. Each
56 of the L and R channel is received by two diff 56 of the L and R channel is received by two different Slaves. Master and both
57 Slaves are using single port. :: 57 Slaves are using single port. ::
58 58
59 +---------------+ C 59 +---------------+ Clock Signal +---------------+
60 | Master +---------+----------- 60 | Master +---------+------------------------+ Slave |
61 | Interface | | 61 | Interface | | | Interface |
62 | | | 62 | | | | 1 |
63 | | | 63 | | | Data Signal | |
64 | L + R +---+----------------- 64 | L + R +---+------------------------------+ L |
65 | (Data) | | | Data Di 65 | (Data) | | | Data Direction | (Data) |
66 +---------------+ | | +------- 66 +---------------+ | | +-------------> +---------------+
67 | | 67 | |
68 | | 68 | |
69 | | 69 | | +---------------+
70 | +----------- 70 | +----------------------> | Slave |
71 | 71 | | Interface |
72 | 72 | | 2 |
73 | 73 | | |
74 +----------------- 74 +----------------------------> | R |
75 75 | (Data) |
76 76 +---------------+
77 77
78 Example 4: Stereo Stream with L and R channels <<
79 Master. Both of the L and R channels are recei <<
80 Slaves. Master and both Slaves are using singl <<
81 L+R. Each Slave device processes the L + R dat <<
82 based on static configuration or dynamic orien <<
83 one or more speakers. :: <<
84 78
85 +---------------+ C !! 79 Example 4: Stereo Stream with L and R channel is rendered by two different
86 | Master +---------+----------- <<
87 | Interface | | <<
88 | | | <<
89 | | | <<
90 | L + R +---+----------------- <<
91 | (Data) | | | Data Di <<
92 +---------------+ | | +------- <<
93 | | <<
94 | | <<
95 | | <<
96 | +----------- <<
97 | <<
98 | <<
99 | <<
100 +----------------- <<
101 <<
102 <<
103 <<
104 Example 5: Stereo Stream with L and R channel <<
105 Ports of the Master and is received by only si 80 Ports of the Master and is received by only single Port of the Slave
106 interface. :: 81 interface. ::
107 82
108 +--------------------+ 83 +--------------------+
109 | | 84 | |
110 | +--------------+ 85 | +--------------+ +----------------+
111 | | || 86 | | || | |
112 | | Data Port || L Channel 87 | | Data Port || L Channel | |
113 | | 1 |------------+ 88 | | 1 |------------+ | |
114 | | L Channel || | 89 | | L Channel || | +-----+----+ |
115 | | (Data) || | L 90 | | (Data) || | L + R Channel || Data | |
116 | Master +----------+ | +-- 91 | Master +----------+ | +---+---------> || Port | |
117 | Interface | | 92 | Interface | | || 1 | |
118 | +--------------+ | 93 | +--------------+ | || | |
119 | | || | 94 | | || | +----------+ |
120 | | Data Port |------------+ 95 | | Data Port |------------+ | |
121 | | 2 || R Channel 96 | | 2 || R Channel | Slave |
122 | | R Channel || 97 | | R Channel || | Interface |
123 | | (Data) || 98 | | (Data) || | 1 |
124 | +--------------+ Clock S 99 | +--------------+ Clock Signal | L + R |
125 | +---------------- 100 | +---------------------------> | (Data) |
126 +--------------------+ 101 +--------------------+ | |
127 102 +----------------+
128 103
129 Example 6: Stereo Stream with L and R channel !! 104 Example 5: Stereo Stream with L and R channel is rendered by 2 Masters, each
130 rendering one channel, and is received by two 105 rendering one channel, and is received by two different Slaves, each
131 receiving one channel. Both Masters and both S 106 receiving one channel. Both Masters and both Slaves are using single port. ::
132 107
133 +---------------+ C 108 +---------------+ Clock Signal +---------------+
134 | Master +--------------------- 109 | Master +----------------------------------+ Slave |
135 | Interface | 110 | Interface | | Interface |
136 | 1 | 111 | 1 | | 1 |
137 | | 112 | | Data Signal | |
138 | L +--------------------- 113 | L +----------------------------------+ L |
139 | (Data) | Data Direction 114 | (Data) | Data Direction | (Data) |
140 +---------------+ +------------------ 115 +---------------+ +-----------------------> +---------------+
141 116
142 +---------------+ C 117 +---------------+ Clock Signal +---------------+
143 | Master +--------------------- 118 | Master +----------------------------------+ Slave |
144 | Interface | 119 | Interface | | Interface |
145 | 2 | 120 | 2 | | 2 |
146 | | 121 | | Data Signal | |
147 | R +--------------------- 122 | R +----------------------------------+ R |
148 | (Data) | Data Direction 123 | (Data) | Data Direction | (Data) |
149 +---------------+ +------------------ 124 +---------------+ +-----------------------> +---------------+
150 125
151 Example 7: Stereo Stream with L and R channel !! 126 Note: In multi-link cases like above, to lock, one would acquire a global
152 Masters, each rendering both channels. Each Sl <<
153 is the same application as Example 4 but with <<
154 separate links. :: <<
155 <<
156 +---------------+ C <<
157 | Master +--------------------- <<
158 | Interface | <<
159 | 1 | <<
160 | | <<
161 | L + R +--------------------- <<
162 | (Data) | Data Direction <<
163 +---------------+ +------------------ <<
164 <<
165 +---------------+ C <<
166 | Master +--------------------- <<
167 | Interface | <<
168 | 2 | <<
169 | | <<
170 | L + R +--------------------- <<
171 | (Data) | Data Direction <<
172 +---------------+ +------------------ <<
173 <<
174 Example 8: 4-channel Stream is rendered by 2 M <<
175 2 channels. Each Slave receives 2 channels. :: <<
176 <<
177 +---------------+ C <<
178 | Master +--------------------- <<
179 | Interface | <<
180 | 1 | <<
181 | | <<
182 | L1 + R1 +--------------------- <<
183 | (Data) | Data Direction <<
184 +---------------+ +------------------ <<
185 <<
186 +---------------+ C <<
187 | Master +--------------------- <<
188 | Interface | <<
189 | 2 | <<
190 | | <<
191 | L2 + R2 +--------------------- <<
192 | (Data) | Data Direction <<
193 +---------------+ +------------------ <<
194 <<
195 Note1: In multi-link cases like above, to lock <<
196 lock and then go on locking bus instances. But 127 lock and then go on locking bus instances. But, in this case the caller
197 framework(ASoC DPCM) guarantees that stream op 128 framework(ASoC DPCM) guarantees that stream operations on a card are
198 always serialized. So, there is no race condit 129 always serialized. So, there is no race condition and hence no need for
199 global lock. 130 global lock.
200 131
201 Note2: A Slave device may be configured to rec <<
202 transmitted on a link for a given Stream (Exam <<
203 of the data (Example 3). The configuration of <<
204 handled by a SoundWire subsystem API, but inst <<
205 snd_soc_dai_set_tdm_slot() API. The platform o <<
206 typically configure which of the slots are use <<
207 same slots would be used by all Devices, while <<
208 Device1 would use e.g. Slot 0 and Slave device <<
209 <<
210 Note3: Multiple Sink ports can extract the sam <<
211 same bitSlots in the SoundWire frame, however <<
212 shall be configured with different bitSlot con <<
213 same limitation as with I2S/PCM TDM usages. <<
214 <<
215 SoundWire Stream Management flow 132 SoundWire Stream Management flow
216 ================================ 133 ================================
217 134
218 Stream definitions 135 Stream definitions
219 ------------------ 136 ------------------
220 137
221 (1) Current stream: This is classified as th 138 (1) Current stream: This is classified as the stream on which operation has
222 to be performed like prepare, enable, di 139 to be performed like prepare, enable, disable, de-prepare etc.
223 140
224 (2) Active stream: This is classified as the 141 (2) Active stream: This is classified as the stream which is already active
225 on Bus other than current stream. There 142 on Bus other than current stream. There can be multiple active streams
226 on the Bus. 143 on the Bus.
227 144
228 SoundWire Bus manages stream operations for ea 145 SoundWire Bus manages stream operations for each stream getting
229 rendered/captured on the SoundWire Bus. This s 146 rendered/captured on the SoundWire Bus. This section explains Bus operations
230 done for each of the stream allocated/released 147 done for each of the stream allocated/released on Bus. Following are the
231 stream states maintained by the Bus for each o 148 stream states maintained by the Bus for each of the audio stream.
232 149
233 150
234 SoundWire stream states 151 SoundWire stream states
235 ----------------------- 152 -----------------------
236 153
237 Below shows the SoundWire stream states and st 154 Below shows the SoundWire stream states and state transition diagram. ::
238 155
239 +-----------+ +------------+ + 156 +-----------+ +------------+ +----------+ +----------+
240 | ALLOCATED +---->| CONFIGURED +---->| 157 | ALLOCATED +---->| CONFIGURED +---->| PREPARED +---->| ENABLED |
241 | STATE | | STATE | | 158 | STATE | | STATE | | STATE | | STATE |
242 +-----------+ +------------+ + 159 +-----------+ +------------+ +---+--+---+ +----+-----+
243 160 ^ ^ ^
244 161 | | |
245 162 __| |___________ |
246 163 | | |
247 164 v | v
248 +----------+ +----- 165 +----------+ +-----+------+ +-+--+-----+
249 | RELEASED |<----------+ DEPR 166 | RELEASED |<----------+ DEPREPARED |<-------+ DISABLED |
250 | STATE | | ST 167 | STATE | | STATE | | STATE |
251 +----------+ +----- 168 +----------+ +------------+ +----------+
252 169
253 NOTE: State transitions between ``SDW_STREAM_E 170 NOTE: State transitions between ``SDW_STREAM_ENABLED`` and
254 ``SDW_STREAM_DISABLED`` are only relevant when 171 ``SDW_STREAM_DISABLED`` are only relevant when then INFO_PAUSE flag is
255 supported at the ALSA/ASoC level. Likewise the 172 supported at the ALSA/ASoC level. Likewise the transition between
256 ``SDW_DISABLED_STATE`` and ``SDW_PREPARED_STAT 173 ``SDW_DISABLED_STATE`` and ``SDW_PREPARED_STATE`` depends on the
257 INFO_RESUME flag. 174 INFO_RESUME flag.
258 175
259 NOTE2: The framework implements basic state tr 176 NOTE2: The framework implements basic state transition checks, but
260 does not e.g. check if a transition from DISAB 177 does not e.g. check if a transition from DISABLED to ENABLED is valid
261 on a specific platform. Such tests need to be 178 on a specific platform. Such tests need to be added at the ALSA/ASoC
262 level. 179 level.
263 180
264 Stream State Operations 181 Stream State Operations
265 ----------------------- 182 -----------------------
266 183
267 Below section explains the operations done by 184 Below section explains the operations done by the Bus on Master(s) and
268 Slave(s) as part of stream state transitions. 185 Slave(s) as part of stream state transitions.
269 186
270 SDW_STREAM_ALLOCATED 187 SDW_STREAM_ALLOCATED
271 ~~~~~~~~~~~~~~~~~~~~ 188 ~~~~~~~~~~~~~~~~~~~~
272 189
273 Allocation state for stream. This is the entry 190 Allocation state for stream. This is the entry state
274 of the stream. Operations performed before ent 191 of the stream. Operations performed before entering in this state:
275 192
276 (1) A stream runtime is allocated for the st 193 (1) A stream runtime is allocated for the stream. This stream
277 runtime is used as a reference for all t 194 runtime is used as a reference for all the operations performed
278 on the stream. 195 on the stream.
279 196
280 (2) The resources required for holding strea 197 (2) The resources required for holding stream runtime information are
281 allocated and initialized. This holds al 198 allocated and initialized. This holds all stream related information
282 such as stream type (PCM/PDM) and parame 199 such as stream type (PCM/PDM) and parameters, Master and Slave
283 interface associated with the stream, st 200 interface associated with the stream, stream state etc.
284 201
285 After all above operations are successful, str 202 After all above operations are successful, stream state is set to
286 ``SDW_STREAM_ALLOCATED``. 203 ``SDW_STREAM_ALLOCATED``.
287 204
288 Bus implements below API for allocate a stream 205 Bus implements below API for allocate a stream which needs to be called once
289 per stream. From ASoC DPCM framework, this str 206 per stream. From ASoC DPCM framework, this stream state maybe linked to
290 .startup() operation. 207 .startup() operation.
291 208
292 .. code-block:: c 209 .. code-block:: c
293 210
294 int sdw_alloc_stream(char * stream_name); 211 int sdw_alloc_stream(char * stream_name);
295 212
296 The SoundWire core provides a sdw_startup_stre <<
297 typically called during a dailink .startup() c <<
298 stream allocation and sets the stream pointer <<
299 connected to a stream. <<
300 213
301 SDW_STREAM_CONFIGURED 214 SDW_STREAM_CONFIGURED
302 ~~~~~~~~~~~~~~~~~~~~~ 215 ~~~~~~~~~~~~~~~~~~~~~
303 216
304 Configuration state of stream. Operations perf 217 Configuration state of stream. Operations performed before entering in
305 this state: 218 this state:
306 219
307 (1) The resources allocated for stream infor 220 (1) The resources allocated for stream information in SDW_STREAM_ALLOCATED
308 state are updated here. This includes st 221 state are updated here. This includes stream parameters, Master(s)
309 and Slave(s) runtime information associa 222 and Slave(s) runtime information associated with current stream.
310 223
311 (2) All the Master(s) and Slave(s) associate 224 (2) All the Master(s) and Slave(s) associated with current stream provide
312 the port information to Bus which includ 225 the port information to Bus which includes port numbers allocated by
313 Master(s) and Slave(s) for current strea 226 Master(s) and Slave(s) for current stream and their channel mask.
314 227
315 After all above operations are successful, str 228 After all above operations are successful, stream state is set to
316 ``SDW_STREAM_CONFIGURED``. 229 ``SDW_STREAM_CONFIGURED``.
317 230
318 Bus implements below APIs for CONFIG state whi 231 Bus implements below APIs for CONFIG state which needs to be called by
319 the respective Master(s) and Slave(s) associat 232 the respective Master(s) and Slave(s) associated with stream. These APIs can
320 only be invoked once by respective Master(s) a 233 only be invoked once by respective Master(s) and Slave(s). From ASoC DPCM
321 framework, this stream state is linked to .hw_ 234 framework, this stream state is linked to .hw_params() operation.
322 235
323 .. code-block:: c 236 .. code-block:: c
324 237
325 int sdw_stream_add_master(struct sdw_bus * b 238 int sdw_stream_add_master(struct sdw_bus * bus,
326 struct sdw_stream_config * str 239 struct sdw_stream_config * stream_config,
327 const struct sdw_ports_config !! 240 struct sdw_ports_config * ports_config,
328 struct sdw_stream_runtime * st 241 struct sdw_stream_runtime * stream);
329 242
330 int sdw_stream_add_slave(struct sdw_slave * 243 int sdw_stream_add_slave(struct sdw_slave * slave,
331 struct sdw_stream_config * str 244 struct sdw_stream_config * stream_config,
332 const struct sdw_ports_config !! 245 struct sdw_ports_config * ports_config,
333 struct sdw_stream_runtime * st 246 struct sdw_stream_runtime * stream);
334 247
335 248
336 SDW_STREAM_PREPARED 249 SDW_STREAM_PREPARED
337 ~~~~~~~~~~~~~~~~~~~ 250 ~~~~~~~~~~~~~~~~~~~
338 251
339 Prepare state of stream. Operations performed 252 Prepare state of stream. Operations performed before entering in this state:
340 253
341 (0) Steps 1 and 2 are omitted in the case of 254 (0) Steps 1 and 2 are omitted in the case of a resume operation,
342 where the bus bandwidth is known. 255 where the bus bandwidth is known.
343 256
344 (1) Bus parameters such as bandwidth, frame 257 (1) Bus parameters such as bandwidth, frame shape, clock frequency,
345 are computed based on current stream as 258 are computed based on current stream as well as already active
346 stream(s) on Bus. Re-computation is requ 259 stream(s) on Bus. Re-computation is required to accommodate current
347 stream on the Bus. 260 stream on the Bus.
348 261
349 (2) Transport and port parameters of all Mas 262 (2) Transport and port parameters of all Master(s) and Slave(s) port(s) are
350 computed for the current as well as alre 263 computed for the current as well as already active stream based on frame
351 shape and clock frequency computed in st 264 shape and clock frequency computed in step 1.
352 265
353 (3) Computed Bus and transport parameters ar 266 (3) Computed Bus and transport parameters are programmed in Master(s) and
354 Slave(s) registers. The banked registers 267 Slave(s) registers. The banked registers programming is done on the
355 alternate bank (bank currently unused). 268 alternate bank (bank currently unused). Port(s) are enabled for the
356 already active stream(s) on the alternat 269 already active stream(s) on the alternate bank (bank currently unused).
357 This is done in order to not disrupt alr 270 This is done in order to not disrupt already active stream(s).
358 271
359 (4) Once all the values are programmed, Bus 272 (4) Once all the values are programmed, Bus initiates switch to alternate
360 bank where all new values programmed get 273 bank where all new values programmed gets into effect.
361 274
362 (5) Ports of Master(s) and Slave(s) for curr 275 (5) Ports of Master(s) and Slave(s) for current stream are prepared by
363 programming PrepareCtrl register. 276 programming PrepareCtrl register.
364 277
365 After all above operations are successful, str 278 After all above operations are successful, stream state is set to
366 ``SDW_STREAM_PREPARED``. 279 ``SDW_STREAM_PREPARED``.
367 280
368 Bus implements below API for PREPARE state whi 281 Bus implements below API for PREPARE state which needs to be called
369 once per stream. From ASoC DPCM framework, thi 282 once per stream. From ASoC DPCM framework, this stream state is linked
370 to .prepare() operation. Since the .trigger() 283 to .prepare() operation. Since the .trigger() operations may not
371 follow the .prepare(), a direct transition fro 284 follow the .prepare(), a direct transition from
372 ``SDW_STREAM_PREPARED`` to ``SDW_STREAM_DEPREP 285 ``SDW_STREAM_PREPARED`` to ``SDW_STREAM_DEPREPARED`` is allowed.
373 286
374 .. code-block:: c 287 .. code-block:: c
375 288
376 int sdw_prepare_stream(struct sdw_stream_run 289 int sdw_prepare_stream(struct sdw_stream_runtime * stream);
377 290
378 291
379 SDW_STREAM_ENABLED 292 SDW_STREAM_ENABLED
380 ~~~~~~~~~~~~~~~~~~ 293 ~~~~~~~~~~~~~~~~~~
381 294
382 Enable state of stream. The data port(s) are e 295 Enable state of stream. The data port(s) are enabled upon entering this state.
383 Operations performed before entering in this s 296 Operations performed before entering in this state:
384 297
385 (1) All the values computed in SDW_STREAM_PR 298 (1) All the values computed in SDW_STREAM_PREPARED state are programmed
386 in alternate bank (bank currently unused 299 in alternate bank (bank currently unused). It includes programming of
387 already active stream(s) as well. 300 already active stream(s) as well.
388 301
389 (2) All the Master(s) and Slave(s) port(s) f 302 (2) All the Master(s) and Slave(s) port(s) for the current stream are
390 enabled on alternate bank (bank currentl 303 enabled on alternate bank (bank currently unused) by programming
391 ChannelEn register. 304 ChannelEn register.
392 305
393 (3) Once all the values are programmed, Bus 306 (3) Once all the values are programmed, Bus initiates switch to alternate
394 bank where all new values programmed get 307 bank where all new values programmed gets into effect and port(s)
395 associated with current stream are enabl 308 associated with current stream are enabled.
396 309
397 After all above operations are successful, str 310 After all above operations are successful, stream state is set to
398 ``SDW_STREAM_ENABLED``. 311 ``SDW_STREAM_ENABLED``.
399 312
400 Bus implements below API for ENABLE state whic 313 Bus implements below API for ENABLE state which needs to be called once per
401 stream. From ASoC DPCM framework, this stream 314 stream. From ASoC DPCM framework, this stream state is linked to
402 .trigger() start operation. 315 .trigger() start operation.
403 316
404 .. code-block:: c 317 .. code-block:: c
405 318
406 int sdw_enable_stream(struct sdw_stream_runt 319 int sdw_enable_stream(struct sdw_stream_runtime * stream);
407 320
408 SDW_STREAM_DISABLED 321 SDW_STREAM_DISABLED
409 ~~~~~~~~~~~~~~~~~~~ 322 ~~~~~~~~~~~~~~~~~~~
410 323
411 Disable state of stream. The data port(s) are 324 Disable state of stream. The data port(s) are disabled upon exiting this state.
412 Operations performed before entering in this s 325 Operations performed before entering in this state:
413 326
414 (1) All the Master(s) and Slave(s) port(s) f 327 (1) All the Master(s) and Slave(s) port(s) for the current stream are
415 disabled on alternate bank (bank current 328 disabled on alternate bank (bank currently unused) by programming
416 ChannelEn register. 329 ChannelEn register.
417 330
418 (2) All the current configuration of Bus and 331 (2) All the current configuration of Bus and active stream(s) are programmed
419 into alternate bank (bank currently unus 332 into alternate bank (bank currently unused).
420 333
421 (3) Once all the values are programmed, Bus 334 (3) Once all the values are programmed, Bus initiates switch to alternate
422 bank where all new values programmed get 335 bank where all new values programmed gets into effect and port(s) associated
423 with current stream are disabled. 336 with current stream are disabled.
424 337
425 After all above operations are successful, str 338 After all above operations are successful, stream state is set to
426 ``SDW_STREAM_DISABLED``. 339 ``SDW_STREAM_DISABLED``.
427 340
428 Bus implements below API for DISABLED state wh 341 Bus implements below API for DISABLED state which needs to be called once
429 per stream. From ASoC DPCM framework, this str 342 per stream. From ASoC DPCM framework, this stream state is linked to
430 .trigger() stop operation. 343 .trigger() stop operation.
431 344
432 When the INFO_PAUSE flag is supported, a direc 345 When the INFO_PAUSE flag is supported, a direct transition to
433 ``SDW_STREAM_ENABLED`` is allowed. 346 ``SDW_STREAM_ENABLED`` is allowed.
434 347
435 For resume operations where ASoC will use the 348 For resume operations where ASoC will use the .prepare() callback, the
436 stream can transition from ``SDW_STREAM_DISABL 349 stream can transition from ``SDW_STREAM_DISABLED`` to
437 ``SDW_STREAM_PREPARED``, with all required set 350 ``SDW_STREAM_PREPARED``, with all required settings restored but
438 without updating the bandwidth and bit allocat 351 without updating the bandwidth and bit allocation.
439 352
440 .. code-block:: c 353 .. code-block:: c
441 354
442 int sdw_disable_stream(struct sdw_stream_run 355 int sdw_disable_stream(struct sdw_stream_runtime * stream);
443 356
444 357
445 SDW_STREAM_DEPREPARED 358 SDW_STREAM_DEPREPARED
446 ~~~~~~~~~~~~~~~~~~~~~ 359 ~~~~~~~~~~~~~~~~~~~~~
447 360
448 De-prepare state of stream. Operations perform 361 De-prepare state of stream. Operations performed before entering in this
449 state: 362 state:
450 363
451 (1) All the port(s) of Master(s) and Slave(s 364 (1) All the port(s) of Master(s) and Slave(s) for current stream are
452 de-prepared by programming PrepareCtrl r 365 de-prepared by programming PrepareCtrl register.
453 366
454 (2) The payload bandwidth of current stream 367 (2) The payload bandwidth of current stream is reduced from the total
455 bandwidth requirement of bus and new par 368 bandwidth requirement of bus and new parameters calculated and
456 applied by performing bank switch etc. 369 applied by performing bank switch etc.
457 370
458 After all above operations are successful, str 371 After all above operations are successful, stream state is set to
459 ``SDW_STREAM_DEPREPARED``. 372 ``SDW_STREAM_DEPREPARED``.
460 373
461 Bus implements below API for DEPREPARED state 374 Bus implements below API for DEPREPARED state which needs to be called
462 once per stream. ALSA/ASoC do not have a conce 375 once per stream. ALSA/ASoC do not have a concept of 'deprepare', and
463 the mapping from this stream state to ALSA/ASo 376 the mapping from this stream state to ALSA/ASoC operation may be
464 implementation specific. 377 implementation specific.
465 378
466 When the INFO_PAUSE flag is supported, the str 379 When the INFO_PAUSE flag is supported, the stream state is linked to
467 the .hw_free() operation - the stream is not d 380 the .hw_free() operation - the stream is not deprepared on a
468 TRIGGER_STOP. 381 TRIGGER_STOP.
469 382
470 Other implementations may transition to the `` 383 Other implementations may transition to the ``SDW_STREAM_DEPREPARED``
471 state on TRIGGER_STOP, should they require a t 384 state on TRIGGER_STOP, should they require a transition through the
472 ``SDW_STREAM_PREPARED`` state. 385 ``SDW_STREAM_PREPARED`` state.
473 386
474 .. code-block:: c 387 .. code-block:: c
475 388
476 int sdw_deprepare_stream(struct sdw_stream_r 389 int sdw_deprepare_stream(struct sdw_stream_runtime * stream);
477 390
478 391
479 SDW_STREAM_RELEASED 392 SDW_STREAM_RELEASED
480 ~~~~~~~~~~~~~~~~~~~ 393 ~~~~~~~~~~~~~~~~~~~
481 394
482 Release state of stream. Operations performed 395 Release state of stream. Operations performed before entering in this state:
483 396
484 (1) Release port resources for all Master(s) 397 (1) Release port resources for all Master(s) and Slave(s) port(s)
485 associated with current stream. 398 associated with current stream.
486 399
487 (2) Release Master(s) and Slave(s) runtime r 400 (2) Release Master(s) and Slave(s) runtime resources associated with
488 current stream. 401 current stream.
489 402
490 (3) Release stream runtime resources associa 403 (3) Release stream runtime resources associated with current stream.
491 404
492 After all above operations are successful, str 405 After all above operations are successful, stream state is set to
493 ``SDW_STREAM_RELEASED``. 406 ``SDW_STREAM_RELEASED``.
494 407
495 Bus implements below APIs for RELEASE state wh 408 Bus implements below APIs for RELEASE state which needs to be called by
496 all the Master(s) and Slave(s) associated with 409 all the Master(s) and Slave(s) associated with stream. From ASoC DPCM
497 framework, this stream state is linked to .hw_ 410 framework, this stream state is linked to .hw_free() operation.
498 411
499 .. code-block:: c 412 .. code-block:: c
500 413
501 int sdw_stream_remove_master(struct sdw_bus 414 int sdw_stream_remove_master(struct sdw_bus * bus,
502 struct sdw_stream_runtime * st 415 struct sdw_stream_runtime * stream);
503 int sdw_stream_remove_slave(struct sdw_slave 416 int sdw_stream_remove_slave(struct sdw_slave * slave,
504 struct sdw_stream_runtime * st 417 struct sdw_stream_runtime * stream);
505 418
506 419
507 The .shutdown() ASoC DPCM operation calls belo 420 The .shutdown() ASoC DPCM operation calls below Bus API to release
508 stream assigned as part of ALLOCATED state. 421 stream assigned as part of ALLOCATED state.
509 422
510 In .shutdown() the data structure maintaining 423 In .shutdown() the data structure maintaining stream state are freed up.
511 424
512 .. code-block:: c 425 .. code-block:: c
513 426
514 void sdw_release_stream(struct sdw_stream_ru 427 void sdw_release_stream(struct sdw_stream_runtime * stream);
515 428
516 The SoundWire core provides a sdw_shutdown_str <<
517 typically called during a dailink .shutdown() <<
518 the stream pointer for all DAIS connected to a <<
519 memory allocated for the stream. <<
520 <<
521 Not Supported 429 Not Supported
522 ============= 430 =============
523 431
524 1. A single port with multiple channels suppor 432 1. A single port with multiple channels supported cannot be used between two
525 streams or across stream. For example a por !! 433 streams or across stream. For example a port with 4 channels cannot be used
526 to handle 2 independent stereo streams even !! 434 to handle 2 independent stereo streams even though it's possible in theory
527 in SoundWire. !! 435 in SoundWire.
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