1 .. SPDX-License-Identifier: GPL-2.0 1 .. SPDX-License-Identifier: GPL-2.0
2 2
3 ===================== 3 =====================
4 Chrome OS ACPI Device 4 Chrome OS ACPI Device
5 ===================== 5 =====================
6 6
7 Hardware functionality specific to Chrome OS i 7 Hardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
8 The plug and play ID of a Chrome OS ACPI devic 8 The plug and play ID of a Chrome OS ACPI device is GGL0001 and the hardware ID is
9 GOOG0016. The following ACPI objects are supp 9 GOOG0016. The following ACPI objects are supported:
10 10
11 .. flat-table:: Supported ACPI Objects 11 .. flat-table:: Supported ACPI Objects
12 :widths: 1 2 12 :widths: 1 2
13 :header-rows: 1 13 :header-rows: 1
14 14
15 * - Object 15 * - Object
16 - Description 16 - Description
17 17
18 * - CHSW 18 * - CHSW
19 - Chrome OS switch positions 19 - Chrome OS switch positions
20 20
21 * - HWID 21 * - HWID
22 - Chrome OS hardware ID 22 - Chrome OS hardware ID
23 23
24 * - FWID 24 * - FWID
25 - Chrome OS firmware version 25 - Chrome OS firmware version
26 26
27 * - FRID 27 * - FRID
28 - Chrome OS read-only firmware version 28 - Chrome OS read-only firmware version
29 29
30 * - BINF 30 * - BINF
31 - Chrome OS boot information 31 - Chrome OS boot information
32 32
33 * - GPIO 33 * - GPIO
34 - Chrome OS GPIO assignments 34 - Chrome OS GPIO assignments
35 35
36 * - VBNV 36 * - VBNV
37 - Chrome OS NVRAM locations 37 - Chrome OS NVRAM locations
38 38
39 * - VDTA 39 * - VDTA
40 - Chrome OS verified boot data 40 - Chrome OS verified boot data
41 41
42 * - FMAP 42 * - FMAP
43 - Chrome OS flashmap base address 43 - Chrome OS flashmap base address
44 44
45 * - MLST 45 * - MLST
46 - Chrome OS method list 46 - Chrome OS method list
47 47
48 CHSW (Chrome OS switch positions) 48 CHSW (Chrome OS switch positions)
49 ================================= 49 =================================
50 This control method returns the switch positio 50 This control method returns the switch positions for Chrome OS specific hardware switches.
51 51
52 Arguments: 52 Arguments:
53 ---------- 53 ----------
54 None 54 None
55 55
56 Result code: 56 Result code:
57 ------------ 57 ------------
58 An integer containing the switch positions as 58 An integer containing the switch positions as bitfields:
59 59
60 .. flat-table:: 60 .. flat-table::
61 :widths: 1 2 61 :widths: 1 2
62 62
63 * - 0x00000002 63 * - 0x00000002
64 - Recovery button was pressed when x86 fi 64 - Recovery button was pressed when x86 firmware booted.
65 65
66 * - 0x00000004 66 * - 0x00000004
67 - Recovery button was pressed when EC fir 67 - Recovery button was pressed when EC firmware booted. (required if EC EEPROM is
68 rewritable; otherwise optional) 68 rewritable; otherwise optional)
69 69
70 * - 0x00000020 70 * - 0x00000020
71 - Developer switch was enabled when x86 f 71 - Developer switch was enabled when x86 firmware booted.
72 72
73 * - 0x00000200 73 * - 0x00000200
74 - Firmware write protection was disabled 74 - Firmware write protection was disabled when x86 firmware booted. (required if
75 firmware write protection is controlled 75 firmware write protection is controlled through x86 BIOS; otherwise optional)
76 76
77 All other bits are reserved and should be set 77 All other bits are reserved and should be set to 0.
78 78
79 HWID (Chrome OS hardware ID) 79 HWID (Chrome OS hardware ID)
80 ============================ 80 ============================
81 This control method returns the hardware ID fo 81 This control method returns the hardware ID for the Chromebook.
82 82
83 Arguments: 83 Arguments:
84 ---------- 84 ----------
85 None 85 None
86 86
87 Result code: 87 Result code:
88 ------------ 88 ------------
89 A null-terminated ASCII string containing the 89 A null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of
90 EEPROM. 90 EEPROM.
91 91
92 Note that the hardware ID can be up to 256 cha 92 Note that the hardware ID can be up to 256 characters long, including the terminating null.
93 93
94 FWID (Chrome OS firmware version) 94 FWID (Chrome OS firmware version)
95 ================================= 95 =================================
96 This control method returns the firmware versi 96 This control method returns the firmware version for the rewritable portion of the main
97 processor firmware. 97 processor firmware.
98 98
99 Arguments: 99 Arguments:
100 ---------- 100 ----------
101 None 101 None
102 102
103 Result code: 103 Result code:
104 ------------ 104 ------------
105 A null-terminated ASCII string containing the 105 A null-terminated ASCII string containing the complete firmware version for the rewritable
106 portion of the main processor firmware. 106 portion of the main processor firmware.
107 107
108 FRID (Chrome OS read-only firmware version) 108 FRID (Chrome OS read-only firmware version)
109 =========================================== 109 ===========================================
110 This control method returns the firmware versi 110 This control method returns the firmware version for the read-only portion of the main
111 processor firmware. 111 processor firmware.
112 112
113 Arguments: 113 Arguments:
114 ---------- 114 ----------
115 None 115 None
116 116
117 Result code: 117 Result code:
118 ------------ 118 ------------
119 A null-terminated ASCII string containing the 119 A null-terminated ASCII string containing the complete firmware version for the read-only
120 (bootstrap + recovery ) portion of the main pr 120 (bootstrap + recovery ) portion of the main processor firmware.
121 121
122 BINF (Chrome OS boot information) 122 BINF (Chrome OS boot information)
123 ================================= 123 =================================
124 This control method returns information about 124 This control method returns information about the current boot.
125 125
126 Arguments: 126 Arguments:
127 ---------- 127 ----------
128 None 128 None
129 129
130 Result code: 130 Result code:
131 ------------ 131 ------------
132 132
133 .. code-block:: 133 .. code-block::
134 134
135 Package { 135 Package {
136 Reserved1 136 Reserved1
137 Reserved2 137 Reserved2
138 Active EC Firmware 138 Active EC Firmware
139 Active Main Firmware Type 139 Active Main Firmware Type
140 Reserved5 140 Reserved5
141 } 141 }
142 142
143 .. flat-table:: 143 .. flat-table::
144 :widths: 1 1 2 144 :widths: 1 1 2
145 :header-rows: 1 145 :header-rows: 1
146 146
147 * - Field 147 * - Field
148 - Format 148 - Format
149 - Description 149 - Description
150 150
151 * - Reserved1 151 * - Reserved1
152 - DWORD 152 - DWORD
153 - Set to 256 (0x100). This indicates this 153 - Set to 256 (0x100). This indicates this field is no longer used.
154 154
155 * - Reserved2 155 * - Reserved2
156 - DWORD 156 - DWORD
157 - Set to 256 (0x100). This indicates this 157 - Set to 256 (0x100). This indicates this field is no longer used.
158 158
159 * - Active EC firmware 159 * - Active EC firmware
160 - DWORD 160 - DWORD
161 - The EC firmware which was used during b 161 - The EC firmware which was used during boot.
162 162
163 - 0 - Read-only (recovery) firmware 163 - 0 - Read-only (recovery) firmware
164 - 1 - Rewritable firmware. 164 - 1 - Rewritable firmware.
165 165
166 Set to 0 if EC firmware is always read- 166 Set to 0 if EC firmware is always read-only.
167 167
168 * - Active Main Firmware Type 168 * - Active Main Firmware Type
169 - DWORD 169 - DWORD
170 - The main firmware type which was used d 170 - The main firmware type which was used during boot.
171 171
172 - 0 - Recovery 172 - 0 - Recovery
173 - 1 - Normal 173 - 1 - Normal
174 - 2 - Developer 174 - 2 - Developer
175 - 3 - netboot (factory installation onl 175 - 3 - netboot (factory installation only)
176 176
177 Other values are reserved. 177 Other values are reserved.
178 178
179 * - Reserved5 179 * - Reserved5
180 - DWORD 180 - DWORD
181 - Set to 256 (0x100). This indicates this 181 - Set to 256 (0x100). This indicates this field is no longer used.
182 182
183 GPIO (Chrome OS GPIO assignments) 183 GPIO (Chrome OS GPIO assignments)
184 ================================= 184 =================================
185 This control method returns information about 185 This control method returns information about Chrome OS specific GPIO assignments for
186 Chrome OS hardware, so the kernel can directly 186 Chrome OS hardware, so the kernel can directly control that hardware.
187 187
188 Arguments: 188 Arguments:
189 ---------- 189 ----------
190 None 190 None
191 191
192 Result code: 192 Result code:
193 ------------ 193 ------------
194 .. code-block:: 194 .. code-block::
195 195
196 Package { 196 Package {
197 Package { 197 Package {
198 // First GPIO assignme 198 // First GPIO assignment
199 Signal Type //D 199 Signal Type //DWORD
200 Attributes //D 200 Attributes //DWORD
201 Controller Offset //D 201 Controller Offset //DWORD
202 Controller Name //A 202 Controller Name //ASCIIZ
203 }, 203 },
204 ... 204 ...
205 Package { 205 Package {
206 // Last GPIO assignmen 206 // Last GPIO assignment
207 Signal Type //D 207 Signal Type //DWORD
208 Attributes //D 208 Attributes //DWORD
209 Controller Offset //D 209 Controller Offset //DWORD
210 Controller Name //A 210 Controller Name //ASCIIZ
211 } 211 }
212 } 212 }
213 213
214 Where ASCIIZ means a null-terminated ASCII str 214 Where ASCIIZ means a null-terminated ASCII string.
215 215
216 .. flat-table:: 216 .. flat-table::
217 :widths: 1 1 2 217 :widths: 1 1 2
218 :header-rows: 1 218 :header-rows: 1
219 219
220 * - Field 220 * - Field
221 - Format 221 - Format
222 - Description 222 - Description
223 223
224 * - Signal Type 224 * - Signal Type
225 - DWORD 225 - DWORD
226 - Type of GPIO signal 226 - Type of GPIO signal
227 227
228 - 0x00000001 - Recovery button 228 - 0x00000001 - Recovery button
229 - 0x00000002 - Developer mode switch 229 - 0x00000002 - Developer mode switch
230 - 0x00000003 - Firmware write protectio 230 - 0x00000003 - Firmware write protection switch
231 - 0x00000100 - Debug header GPIO 0 231 - 0x00000100 - Debug header GPIO 0
232 - ... 232 - ...
233 - 0x000001FF - Debug header GPIO 255 233 - 0x000001FF - Debug header GPIO 255
234 234
235 Other values are reserved. 235 Other values are reserved.
236 236
237 * - Attributes 237 * - Attributes
238 - DWORD 238 - DWORD
239 - Signal attributes as bitfields: 239 - Signal attributes as bitfields:
240 240
241 - 0x00000001 - Signal is active-high (f 241 - 0x00000001 - Signal is active-high (for button, a GPIO value
242 of 1 means the button is pressed; for 242 of 1 means the button is pressed; for switches, a GPIO value
243 of 1 means the switch is enabled). If 243 of 1 means the switch is enabled). If this bit is 0, the signal
244 is active low. Set to 0 for debug hea 244 is active low. Set to 0 for debug header GPIOs.
245 245
246 * - Controller Offset 246 * - Controller Offset
247 - DWORD 247 - DWORD
248 - GPIO number on the specified controller 248 - GPIO number on the specified controller.
249 249
250 * - Controller Name 250 * - Controller Name
251 - ASCIIZ 251 - ASCIIZ
252 - Name of the controller for the GPIO. 252 - Name of the controller for the GPIO.
253 Currently supported names: 253 Currently supported names:
254 "NM10" - Intel NM10 chip 254 "NM10" - Intel NM10 chip
255 255
256 VBNV (Chrome OS NVRAM locations) 256 VBNV (Chrome OS NVRAM locations)
257 ================================ 257 ================================
258 This control method returns information about 258 This control method returns information about the NVRAM (CMOS) locations used to
259 communicate with the BIOS. 259 communicate with the BIOS.
260 260
261 Arguments: 261 Arguments:
262 ---------- 262 ----------
263 None 263 None
264 264
265 Result code: 265 Result code:
266 ------------ 266 ------------
267 .. code-block:: 267 .. code-block::
268 268
269 Package { 269 Package {
270 NV Storage Block Offset //DWO 270 NV Storage Block Offset //DWORD
271 NV Storage Block Size //DWO 271 NV Storage Block Size //DWORD
272 } 272 }
273 273
274 .. flat-table:: 274 .. flat-table::
275 :widths: 1 1 2 275 :widths: 1 1 2
276 :header-rows: 1 276 :header-rows: 1
277 277
278 * - Field 278 * - Field
279 - Format 279 - Format
280 - Description 280 - Description
281 281
282 * - NV Storage Block Offset 282 * - NV Storage Block Offset
283 - DWORD 283 - DWORD
284 - Offset in CMOS bank 0 of the verified b 284 - Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from
285 the first writable CMOS byte (that is, 285 the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of
286 clock data). 286 clock data).
287 287
288 * - NV Storage Block Size 288 * - NV Storage Block Size
289 - DWORD 289 - DWORD
290 - Size in bytes of the verified boot non- 290 - Size in bytes of the verified boot non-volatile storage block.
291 291
292 FMAP (Chrome OS flashmap address) 292 FMAP (Chrome OS flashmap address)
293 ================================= 293 =================================
294 This control method returns the physical memor 294 This control method returns the physical memory address of the start of the main processor
295 firmware flashmap. 295 firmware flashmap.
296 296
297 Arguments: 297 Arguments:
298 ---------- 298 ----------
299 None 299 None
300 300
301 NoneResult code: 301 NoneResult code:
302 ---------------- 302 ----------------
303 A DWORD containing the physical memory address 303 A DWORD containing the physical memory address of the start of the main processor firmware
304 flashmap. 304 flashmap.
305 305
306 VDTA (Chrome OS verified boot data) 306 VDTA (Chrome OS verified boot data)
307 =================================== 307 ===================================
308 This control method returns the verified boot 308 This control method returns the verified boot data block shared between the firmware
309 verification step and the kernel verification 309 verification step and the kernel verification step.
310 310
311 Arguments: 311 Arguments:
312 ---------- 312 ----------
313 None 313 None
314 314
315 Result code: 315 Result code:
316 ------------ 316 ------------
317 A buffer containing the verified boot data blo 317 A buffer containing the verified boot data block.
318 318
319 MECK (Management Engine Checksum) 319 MECK (Management Engine Checksum)
320 ================================= 320 =================================
321 This control method returns the SHA-1 or SHA-2 321 This control method returns the SHA-1 or SHA-256 hash that is read out of the Management
322 Engine extended registers during boot. The has 322 Engine extended registers during boot. The hash is exported via ACPI so the OS can verify that
323 the ME firmware has not changed. If Management 323 the ME firmware has not changed. If Management Engine is not present, or if the firmware was
324 unable to read the extended registers, this bu 324 unable to read the extended registers, this buffer can be zero.
325 325
326 Arguments: 326 Arguments:
327 ---------- 327 ----------
328 None 328 None
329 329
330 Result code: 330 Result code:
331 ------------ 331 ------------
332 A buffer containing the ME hash. 332 A buffer containing the ME hash.
333 333
334 MLST (Chrome OS method list) 334 MLST (Chrome OS method list)
335 ============================ 335 ============================
336 This control method returns a list of the othe 336 This control method returns a list of the other control methods supported by the Chrome OS
337 hardware device. 337 hardware device.
338 338
339 Arguments: 339 Arguments:
340 ---------- 340 ----------
341 None 341 None
342 342
343 Result code: 343 Result code:
344 ------------ 344 ------------
345 A package containing a list of null-terminated 345 A package containing a list of null-terminated ASCII strings, one for each control method
346 supported by the Chrome OS hardware device, no 346 supported by the Chrome OS hardware device, not including the MLST method itself.
347 For this version of the specification, the res 347 For this version of the specification, the result is:
348 348
349 .. code-block:: 349 .. code-block::
350 350
351 Package { 351 Package {
352 "CHSW", 352 "CHSW",
353 "FWID", 353 "FWID",
354 "HWID", 354 "HWID",
355 "FRID", 355 "FRID",
356 "BINF", 356 "BINF",
357 "GPIO", 357 "GPIO",
358 "VBNV", 358 "VBNV",
359 "FMAP", 359 "FMAP",
360 "VDTA", 360 "VDTA",
361 "MECK" 361 "MECK"
362 } 362 }
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