1 :orphan: 1 :orphan:
2 2
3 ===================== 3 =====================
4 MSM Crash Dump Format 4 MSM Crash Dump Format
5 ===================== 5 =====================
6 6
7 Following a GPU hang the MSM driver outputs de 7 Following a GPU hang the MSM driver outputs debugging information via
8 /sys/kernel/dri/X/show or via devcoredump (/sy 8 /sys/kernel/dri/X/show or via devcoredump (/sys/class/devcoredump/dcdX/data).
9 This document describes how the output is form 9 This document describes how the output is formatted.
10 10
11 Each entry is in the form key: value. Sections 11 Each entry is in the form key: value. Sections headers will not have a value
12 and all the contents of a section will be inde 12 and all the contents of a section will be indented two spaces from the header.
13 Each section might have multiple array entries 13 Each section might have multiple array entries the start of which is designated
14 by a (-). 14 by a (-).
15 15
16 Mappings 16 Mappings
17 -------- 17 --------
18 18
19 kernel 19 kernel
20 The kernel version that generated the 20 The kernel version that generated the dump (UTS_RELEASE).
21 21
22 module 22 module
23 The module that generated the crashdum 23 The module that generated the crashdump.
24 24
25 time 25 time
26 The kernel time at crash formatted as !! 26 The kernel time at crash formated as seconds.microseconds.
27 27
28 comm 28 comm
29 Comm string for the binary that genera 29 Comm string for the binary that generated the fault.
30 30
31 cmdline 31 cmdline
32 Command line for the binary that gener 32 Command line for the binary that generated the fault.
33 33
34 revision 34 revision
35 ID of the GPU that generated the crash 35 ID of the GPU that generated the crash formatted as
36 core.major.minor.patchlevel separated 36 core.major.minor.patchlevel separated by dots.
37 37
38 rbbm-status 38 rbbm-status
39 The current value of RBBM_STATUS which 39 The current value of RBBM_STATUS which shows what top level GPU
40 components are in use at the time of c 40 components are in use at the time of crash.
41 41
42 ringbuffer 42 ringbuffer
43 Section containing the contents of eac 43 Section containing the contents of each ringbuffer. Each ringbuffer is
44 identified with an id number. 44 identified with an id number.
45 45
46 id 46 id
47 Ringbuffer ID (0 based index). 47 Ringbuffer ID (0 based index). Each ringbuffer in the section
48 will have its own unique id. 48 will have its own unique id.
49 iova 49 iova
50 GPU address of the ringbuffer. 50 GPU address of the ringbuffer.
51 51
52 last-fence 52 last-fence
53 The last fence that was issued 53 The last fence that was issued on the ringbuffer
54 54
55 retired-fence 55 retired-fence
56 The last fence retired on the 56 The last fence retired on the ringbuffer.
57 57
58 rptr 58 rptr
59 The current read pointer (rptr 59 The current read pointer (rptr) for the ringbuffer.
60 60
61 wptr 61 wptr
62 The current write pointer (wpt 62 The current write pointer (wptr) for the ringbuffer.
63 63
64 size 64 size
65 Maximum size of the ringbuffer 65 Maximum size of the ringbuffer programmed in the hardware.
66 66
67 data 67 data
68 The contents of the ring encod 68 The contents of the ring encoded as ascii85. Only the used
69 portions of the ring will be p 69 portions of the ring will be printed.
70 70
71 bo 71 bo
72 List of buffers from the hanging submi 72 List of buffers from the hanging submission if available.
73 Each buffer object will have a uinque 73 Each buffer object will have a uinque iova.
74 74
75 iova 75 iova
76 GPU address of the buffer obje 76 GPU address of the buffer object.
77 77
78 size 78 size
79 Allocated size of the buffer o 79 Allocated size of the buffer object.
80 80
81 data 81 data
82 The contents of the buffer obj 82 The contents of the buffer object encoded with ascii85. Only
83 Trailing zeros at the end of t 83 Trailing zeros at the end of the buffer will be skipped.
84 84
85 registers 85 registers
86 Set of registers values. Each entry is 86 Set of registers values. Each entry is on its own line enclosed
87 by brackets { }. 87 by brackets { }.
88 88
89 offset 89 offset
90 Byte offset of the register fr 90 Byte offset of the register from the start of the
91 GPU memory region. 91 GPU memory region.
92 92
93 value 93 value
94 Hexadecimal value of the regis 94 Hexadecimal value of the register.
95 95
96 registers-hlsq 96 registers-hlsq
97 (5xx only) Register values fro 97 (5xx only) Register values from the HLSQ aperture.
98 Same format as the register se 98 Same format as the register section.
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