1 ==============================================
2 drm/tegra NVIDIA Tegra GPU and display driver
3 ==============================================
4
5 NVIDIA Tegra SoCs support a set of display, gr
6 the host1x controller. host1x supplies command
7 buffer provided directly by the CPU, to its cl
8 or blocks amongst themselves, can use syncpoin
9
10 Up until, but not including, Tegra124 (aka Teg
11 supports the built-in GPU, comprised of the gr
12 with Tegra124 the GPU is based on the NVIDIA d
13 supported by the drm/nouveau driver.
14
15 The drm/tegra driver supports NVIDIA Tegra SoC
16 has three parts:
17
18 - A host1x driver that provides infrastructu
19 services.
20
21 - A KMS driver that supports the display con
22 outputs, such as RGB, HDMI, DSI, and Displ
23
24 - A set of custom userspace IOCTLs that can
25 GPU and video engines via host1x.
26
27 Driver Infrastructure
28 =====================
29
30 The various host1x clients need to be bound to
31 order to expose their functionality to users.
32 this is implemented in the host1x driver. When
33 infrastructure it provides a list of compatibl
34 that it needs. The infrastructure creates a lo
35 tree for matching device nodes, adding the req
36 for individual clients register with the infra
37 to the logical host1x device.
38
39 Once all clients are available, the infrastruc
40 device using a driver-provided function which
41 the subsystem and in turn initialize each of i
42
43 Similarly, when one of the clients is unregist
44 destroy the logical device by calling back int
45 the subsystem specific bits are torn down and
46
47 Host1x Infrastructure Reference
48 -------------------------------
49
50 .. kernel-doc:: include/linux/host1x.h
51
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
53 :export:
54
55 Host1x Syncpoint Reference
56 --------------------------
57
58 .. kernel-doc:: drivers/gpu/host1x/syncpt.c
59 :export:
60
61 KMS driver
62 ==========
63
64 The display hardware has remained mostly backw
65 Tegra SoC generations, up until Tegra186 which
66 make it difficult to support with a parameteri
67
68 Display Controllers
69 -------------------
70
71 Tegra SoCs have two display controllers, each
72 zero or more outputs. Outputs can also share a
73 only if they run with compatible display timin
74 also share a single framebuffer, allowing clon
75 on two outputs don't match. A display controll
76 terms.
77
78 On Tegra186, the number of display controllers
79 display controller can no longer drive all of
80 controllers can drive both DSI outputs and bot
81 drive any DSI.
82
83 Windows
84 ~~~~~~~
85
86 A display controller controls a set of windows
87 multiple buffers onto the screen. While it is
88 ordering to individual windows (by programming
89 registers), this is currently not supported by
90 assume a fixed Z ordering of the windows (wind
91 is, the lowest, while windows B and C are over
92 overlay windows support multiple pixel formats
93 from YUV to RGB at scanout time. This makes th
94 content. In KMS, each window is modelled as a
95 has a hardware cursor that is exposed as a cur
96
97 Outputs
98 -------
99
100 The type and number of supported outputs varie
101 All generations support at least HDMI. While e
102 very simple RGB interfaces (one per display co
103 longer do and instead provide standard interfa
104
105 Outputs are modelled as a composite encoder/co
106
107 RGB/LVDS
108 ~~~~~~~~
109
110 This interface is no longer available since Te
111 the more standard DSI and eDP interfaces.
112
113 HDMI
114 ~~~~
115
116 HDMI is supported on all Tegra SoCs. Starting
117 by the versatile SOR output, which supports eD
118 to support HDMI 2.0, though support for this i
119
120 DSI
121 ~~~
122
123 Although Tegra has supported DSI since Tegra30
124 several ways in Tegra114. Since none of the pu
125 boards prior to Dalmore (Tegra114) have made u
126 later are supported by the drm/tegra driver.
127
128 eDP/DP
129 ~~~~~~
130
131 eDP was first introduced in Tegra124 where it
132 panel for notebook form factors. Tegra210 adde
133 support, though this is currently not implemen
134
135 Userspace Interface
136 ===================
137
138 The userspace interface provided by drm/tegra
139 GEM buffers, access and control syncpoints as
140 to host1x.
141
142 GEM Buffers
143 -----------
144
145 The ``DRM_IOCTL_TEGRA_GEM_CREATE`` IOCTL is us
146 with Tegra-specific flags. This is useful for
147 that are to be scanned out upside down (useful
148
149 After a GEM buffer object has been created, it
150 application using the mmap offset returned by
151 IOCTL.
152
153 Syncpoints
154 ----------
155
156 The current value of a syncpoint can be obtain
157 ``DRM_IOCTL_TEGRA_SYNCPT_READ`` IOCTL. Increme
158 using the ``DRM_IOCTL_TEGRA_SYNCPT_INCR`` IOCT
159
160 Userspace can also request blocking on a syncp
161 execute the ``DRM_IOCTL_TEGRA_SYNCPT_WAIT`` IO
162 the syncpoint to wait for. The kernel will rel
163 syncpoint reaches that value or after a specif
164
165 Command Stream Submission
166 -------------------------
167
168 Before an application can submit command strea
169 channel to an engine using the ``DRM_IOCTL_TEG
170 IDs are used to identify the target of the cha
171 longer needed, it can be closed using the ``DR
172 IOCTL. To retrieve the syncpoint associated wi
173 can use the ``DRM_IOCTL_TEGRA_GET_SYNCPT``.
174
175 After opening a channel, submitting command st
176 writes commands into the memory backing a GEM
177 to the ``DRM_IOCTL_TEGRA_SUBMIT`` IOCTL along
178 such as the syncpoints or relocations used in
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