1 .. SPDX-License-Identifier: GPL-2.0
2
3 Kernel driver max16601
4 ======================
5
6 Supported chips:
7
8 * Maxim MAX16508
9
10 Prefix: 'max16508'
11
12 Addresses scanned: -
13
14 Datasheet: Not published
15
16 * Maxim MAX16600
17
18 Prefix: 'max16600'
19
20 Addresses scanned: -
21
22 Datasheet: Not published
23
24 * Maxim MAX16601
25
26 Prefix: 'max16601'
27
28 Addresses scanned: -
29
30 Datasheet: Not published
31
32 * Maxim MAX16602
33
34 Prefix: 'max16602'
35
36 Addresses scanned: -
37
38 Datasheet: https://datasheets.maximintegra
39
40 Author: Guenter Roeck <linux@roeck-us.net>
41
42
43 Description
44 -----------
45
46 This driver supports the MAX16508 VR13 Dual-Ou
47 as well as the MAX16600, MAX16601, and MAX1660
48 Voltage Regulator chipsets.
49
50 The driver is a client driver to the core PMBu
51 Please see Documentation/hwmon/pmbus.rst for d
52
53
54 Usage Notes
55 -----------
56
57 This driver does not auto-detect devices. You
58 devices explicitly. Please see Documentation/i
59 details.
60
61
62 Platform data support
63 ---------------------
64
65 The driver supports standard PMBus driver plat
66
67
68 Sysfs entries
69 -------------
70
71 The following attributes are supported.
72
73 =============================== ==============
74 in1_label "vin1"
75 in1_input VCORE input vo
76 in1_alarm Input voltage
77
78 in2_label "vout1"
79 in2_input VCORE output v
80 in2_alarm Output voltage
81
82 curr1_label "iin1"
83 curr1_input VCORE input cu
84 and output cur
85 curr1_max Maximum input
86 curr1_max_alarm Current high a
87
88 curr[P+2]_label "iin1.P"
89 curr[P+2]_input VCORE phase P
90
91 curr[N+2]_label "iin2"
92 curr[N+2]_input VCORE input cu
93 element.
94 'N' is the num
95
96 curr[N+3]_label "iin3"
97 curr[N+3]_input VSA input curr
98
99 curr[N+4]_label "iout1"
100 curr[N+4]_input VCORE output c
101 curr[N+4]_crit Critical outpu
102 curr[N+4]_crit_alarm Output current
103 curr[N+4]_max Maximum output
104 curr[N+4]_max_alarm Output current
105
106 curr[N+P+5]_label "iout1.P"
107 curr[N+P+5]_input VCORE phase P
108
109 curr[2*N+5]_label "iout3"
110 curr[2*N+5]_input VSA output cur
111 curr[2*N+5]_highest Historical max
112 curr[2*N+5]_reset_history Write any valu
113 curr[2*N+5]_crit Critical outpu
114 curr[2*N+5]_crit_alarm Output current
115 curr[2*N+5]_max Maximum output
116 curr[2*N+5]_max_alarm Output current
117
118 power1_label "pin1"
119 power1_input Input power, d
120 current.
121 power1_alarm Input power al
122
123 power2_label "pin2"
124 power2_input Input power, d
125
126 power3_label "pout"
127 power3_input Output power.
128
129 temp1_input VCORE temperat
130 temp1_crit Critical high
131 temp1_crit_alarm Chip temperatu
132 temp1_max Maximum temper
133 temp1_max_alarm Chip temperatu
134
135 temp2_input TSENSE_0 tempe
136 temp3_input TSENSE_1 tempe
137 temp4_input TSENSE_2 tempe
138 temp5_input TSENSE_3 tempe
139
140 temp6_input VSA temperatur
141 temp6_crit Critical high
142 temp6_crit_alarm Chip temperatu
143 temp6_max Maximum temper
144 temp6_max_alarm Chip temperatu
145 =============================== ==============
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