1 .. SPDX-License-Identifier: GPL-2.0 1 .. SPDX-License-Identifier: GPL-2.0
2 2
3 Kernel driver max16601 3 Kernel driver max16601
4 ====================== 4 ======================
5 5
6 Supported chips: 6 Supported chips:
7 7
8 * Maxim MAX16508 <<
9 <<
10 Prefix: 'max16508' <<
11 <<
12 Addresses scanned: - <<
13 <<
14 Datasheet: Not published <<
15 <<
16 * Maxim MAX16600 <<
17 <<
18 Prefix: 'max16600' <<
19 <<
20 Addresses scanned: - <<
21 <<
22 Datasheet: Not published <<
23 <<
24 * Maxim MAX16601 8 * Maxim MAX16601
25 9
26 Prefix: 'max16601' 10 Prefix: 'max16601'
27 11
28 Addresses scanned: - 12 Addresses scanned: -
29 13
30 Datasheet: Not published 14 Datasheet: Not published
31 15
32 * Maxim MAX16602 <<
33 <<
34 Prefix: 'max16602' <<
35 <<
36 Addresses scanned: - <<
37 <<
38 Datasheet: https://datasheets.maximintegra <<
39 <<
40 Author: Guenter Roeck <linux@roeck-us.net> 16 Author: Guenter Roeck <linux@roeck-us.net>
41 17
42 18
43 Description 19 Description
44 ----------- 20 -----------
45 21
46 This driver supports the MAX16508 VR13 Dual-Ou !! 22 This driver supports the MAX16601 VR13.HC Dual-Output Voltage Regulator
47 as well as the MAX16600, MAX16601, and MAX1660 !! 23 Chipset.
48 Voltage Regulator chipsets. <<
49 24
50 The driver is a client driver to the core PMBu 25 The driver is a client driver to the core PMBus driver.
51 Please see Documentation/hwmon/pmbus.rst for d 26 Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers.
52 27
53 28
54 Usage Notes 29 Usage Notes
55 ----------- 30 -----------
56 31
57 This driver does not auto-detect devices. You 32 This driver does not auto-detect devices. You will have to instantiate the
58 devices explicitly. Please see Documentation/i 33 devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for
59 details. 34 details.
60 35
61 36
62 Platform data support 37 Platform data support
63 --------------------- 38 ---------------------
64 39
65 The driver supports standard PMBus driver plat 40 The driver supports standard PMBus driver platform data.
66 41
67 42
68 Sysfs entries 43 Sysfs entries
69 ------------- 44 -------------
70 45
71 The following attributes are supported. 46 The following attributes are supported.
72 47
73 =============================== ============== !! 48 ======================= =======================================================
74 in1_label "vin1" !! 49 in1_label "vin1"
75 in1_input VCORE input vo !! 50 in1_input VCORE input voltage.
76 in1_alarm Input voltage !! 51 in1_alarm Input voltage alarm.
77 !! 52
78 in2_label "vout1" !! 53 in2_label "vout1"
79 in2_input VCORE output v !! 54 in2_input VCORE output voltage.
80 in2_alarm Output voltage !! 55 in2_alarm Output voltage alarm.
81 !! 56
82 curr1_label "iin1" !! 57 curr1_label "iin1"
83 curr1_input VCORE input cu !! 58 curr1_input VCORE input current, derived from duty cycle and output
84 and output cur !! 59 current.
85 curr1_max Maximum input !! 60 curr1_max Maximum input current.
86 curr1_max_alarm Current high a !! 61 curr1_max_alarm Current high alarm.
87 !! 62
88 curr[P+2]_label "iin1.P" !! 63 curr2_label "iin1.0"
89 curr[P+2]_input VCORE phase P !! 64 curr2_input VCORE phase 0 input current.
90 !! 65
91 curr[N+2]_label "iin2" !! 66 curr3_label "iin1.1"
92 curr[N+2]_input VCORE input cu !! 67 curr3_input VCORE phase 1 input current.
93 element. !! 68
94 'N' is the num !! 69 curr4_label "iin1.2"
95 !! 70 curr4_input VCORE phase 2 input current.
96 curr[N+3]_label "iin3" !! 71
97 curr[N+3]_input VSA input curr !! 72 curr5_label "iin1.3"
98 !! 73 curr5_input VCORE phase 3 input current.
99 curr[N+4]_label "iout1" !! 74
100 curr[N+4]_input VCORE output c !! 75 curr6_label "iin1.4"
101 curr[N+4]_crit Critical outpu !! 76 curr6_input VCORE phase 4 input current.
102 curr[N+4]_crit_alarm Output current !! 77
103 curr[N+4]_max Maximum output !! 78 curr7_label "iin1.5"
104 curr[N+4]_max_alarm Output current !! 79 curr7_input VCORE phase 5 input current.
105 !! 80
106 curr[N+P+5]_label "iout1.P" !! 81 curr8_label "iin1.6"
107 curr[N+P+5]_input VCORE phase P !! 82 curr8_input VCORE phase 6 input current.
108 !! 83
109 curr[2*N+5]_label "iout3" !! 84 curr9_label "iin1.7"
110 curr[2*N+5]_input VSA output cur !! 85 curr9_input VCORE phase 7 input current.
111 curr[2*N+5]_highest Historical max !! 86
112 curr[2*N+5]_reset_history Write any valu !! 87 curr10_label "iin2"
113 curr[2*N+5]_crit Critical outpu !! 88 curr10_input VCORE input current, derived from sensor element.
114 curr[2*N+5]_crit_alarm Output current !! 89
115 curr[2*N+5]_max Maximum output !! 90 curr11_label "iin3"
116 curr[2*N+5]_max_alarm Output current !! 91 curr11_input VSA input current.
117 !! 92
118 power1_label "pin1" !! 93 curr12_label "iout1"
119 power1_input Input power, d !! 94 curr12_input VCORE output current.
120 current. !! 95 curr12_crit Critical output current.
121 power1_alarm Input power al !! 96 curr12_crit_alarm Output current critical alarm.
122 !! 97 curr12_max Maximum output current.
123 power2_label "pin2" !! 98 curr12_max_alarm Output current high alarm.
124 power2_input Input power, d !! 99
125 !! 100 curr13_label "iout1.0"
126 power3_label "pout" !! 101 curr13_input VCORE phase 0 output current.
127 power3_input Output power. !! 102
128 !! 103 curr14_label "iout1.1"
129 temp1_input VCORE temperat !! 104 curr14_input VCORE phase 1 output current.
130 temp1_crit Critical high !! 105
131 temp1_crit_alarm Chip temperatu !! 106 curr15_label "iout1.2"
132 temp1_max Maximum temper !! 107 curr15_input VCORE phase 2 output current.
133 temp1_max_alarm Chip temperatu !! 108
134 !! 109 curr16_label "iout1.3"
135 temp2_input TSENSE_0 tempe !! 110 curr16_input VCORE phase 3 output current.
136 temp3_input TSENSE_1 tempe !! 111
137 temp4_input TSENSE_2 tempe !! 112 curr17_label "iout1.4"
138 temp5_input TSENSE_3 tempe !! 113 curr17_input VCORE phase 4 output current.
139 !! 114
140 temp6_input VSA temperatur !! 115 curr18_label "iout1.5"
141 temp6_crit Critical high !! 116 curr18_input VCORE phase 5 output current.
142 temp6_crit_alarm Chip temperatu !! 117
143 temp6_max Maximum temper !! 118 curr19_label "iout1.6"
144 temp6_max_alarm Chip temperatu !! 119 curr19_input VCORE phase 6 output current.
145 =============================== ============== !! 120
>> 121 curr20_label "iout1.7"
>> 122 curr20_input VCORE phase 7 output current.
>> 123
>> 124 curr21_label "iout3"
>> 125 curr21_input VSA output current.
>> 126 curr21_highest Historical maximum VSA output current.
>> 127 curr21_reset_history Write any value to reset curr21_highest.
>> 128 curr21_crit Critical output current.
>> 129 curr21_crit_alarm Output current critical alarm.
>> 130 curr21_max Maximum output current.
>> 131 curr21_max_alarm Output current high alarm.
>> 132
>> 133 power1_label "pin1"
>> 134 power1_input Input power, derived from duty cycle and output current.
>> 135 power1_alarm Input power alarm.
>> 136
>> 137 power2_label "pin2"
>> 138 power2_input Input power, derived from input current sensor.
>> 139
>> 140 power3_label "pout"
>> 141 power3_input Output power.
>> 142
>> 143 temp1_input VCORE temperature.
>> 144 temp1_crit Critical high temperature.
>> 145 temp1_crit_alarm Chip temperature critical high alarm.
>> 146 temp1_max Maximum temperature.
>> 147 temp1_max_alarm Chip temperature high alarm.
>> 148
>> 149 temp2_input TSENSE_0 temperature
>> 150 temp3_input TSENSE_1 temperature
>> 151 temp4_input TSENSE_2 temperature
>> 152 temp5_input TSENSE_3 temperature
>> 153
>> 154 temp6_input VSA temperature.
>> 155 temp6_crit Critical high temperature.
>> 156 temp6_crit_alarm Chip temperature critical high alarm.
>> 157 temp6_max Maximum temperature.
>> 158 temp6_max_alarm Chip temperature high alarm.
>> 159 ======================= =======================================================
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