1 ================================ 1 ================================
2 I2C muxes and complex topologies 2 I2C muxes and complex topologies
3 ================================ 3 ================================
4 4
5 There are a couple of reasons for building mor 5 There are a couple of reasons for building more complex I2C topologies
6 than a straight-forward I2C bus with one adapt 6 than a straight-forward I2C bus with one adapter and one or more devices.
7 7
8 Some example use cases are: 8 Some example use cases are:
9 9
10 1. A mux may be needed on the bus to prevent a 10 1. A mux may be needed on the bus to prevent address collisions.
11 11
12 2. The bus may be accessible from some externa 12 2. The bus may be accessible from some external bus master, and arbitration
13 may be needed to determine if it is ok to a 13 may be needed to determine if it is ok to access the bus.
14 14
15 3. A device (particularly RF tuners) may want 15 3. A device (particularly RF tuners) may want to avoid the digital noise
16 from the I2C bus, at least most of the time 16 from the I2C bus, at least most of the time, and sits behind a gate
17 that has to be operated before the device c 17 that has to be operated before the device can be accessed.
18 18
19 Several types of hardware components such as I 19 Several types of hardware components such as I2C muxes, I2C gates and I2C
20 arbitrators allow to handle such needs. 20 arbitrators allow to handle such needs.
21 21
22 These components are represented as I2C adapte 22 These components are represented as I2C adapter trees by Linux, where
23 each adapter has a parent adapter (except the 23 each adapter has a parent adapter (except the root adapter) and zero or
24 more child adapters. The root adapter is the a 24 more child adapters. The root adapter is the actual adapter that issues
25 I2C transfers, and all adapters with a parent 25 I2C transfers, and all adapters with a parent are part of an "i2c-mux"
26 object (quoted, since it can also be an arbitr 26 object (quoted, since it can also be an arbitrator or a gate).
27 27
28 Depending of the particular mux driver, someth 28 Depending of the particular mux driver, something happens when there is
29 an I2C transfer on one of its child adapters. 29 an I2C transfer on one of its child adapters. The mux driver can
30 obviously operate a mux, but it can also do ar 30 obviously operate a mux, but it can also do arbitration with an external
31 bus master or open a gate. The mux driver has 31 bus master or open a gate. The mux driver has two operations for this,
32 select and deselect. select is called before t 32 select and deselect. select is called before the transfer and (the
33 optional) deselect is called after the transfe 33 optional) deselect is called after the transfer.
34 34
35 35
36 Locking 36 Locking
37 ======= 37 =======
38 38
39 There are two variants of locking available to 39 There are two variants of locking available to I2C muxes, they can be
40 mux-locked or parent-locked muxes. 40 mux-locked or parent-locked muxes.
41 41
42 42
43 Mux-locked muxes 43 Mux-locked muxes
44 ---------------- 44 ----------------
45 45
46 Mux-locked muxes does not lock the entire pare 46 Mux-locked muxes does not lock the entire parent adapter during the
47 full select-transfer-deselect transaction, onl 47 full select-transfer-deselect transaction, only the muxes on the parent
48 adapter are locked. Mux-locked muxes are mostl 48 adapter are locked. Mux-locked muxes are mostly interesting if the
49 select and/or deselect operations must use I2C 49 select and/or deselect operations must use I2C transfers to complete
50 their tasks. Since the parent adapter is not f 50 their tasks. Since the parent adapter is not fully locked during the
51 full transaction, unrelated I2C transfers may 51 full transaction, unrelated I2C transfers may interleave the different
52 stages of the transaction. This has the benefi 52 stages of the transaction. This has the benefit that the mux driver
53 may be easier and cleaner to implement, but it 53 may be easier and cleaner to implement, but it has some caveats.
54 54
55 Mux-locked Example 55 Mux-locked Example
56 ~~~~~~~~~~~~~~~~~~ 56 ~~~~~~~~~~~~~~~~~~
57 57
58 :: 58 ::
59 59
60 .----------. .--------. 60 .----------. .--------.
61 .--------. | mux- |-----| dev D1 | 61 .--------. | mux- |-----| dev D1 |
62 | root |--+--| locked | '--------' 62 | root |--+--| locked | '--------'
63 '--------' | | mux M1 |--. .--------. 63 '--------' | | mux M1 |--. .--------.
64 | '----------' '--| dev D2 | 64 | '----------' '--| dev D2 |
65 | .--------. '--------' 65 | .--------. '--------'
66 '--| dev D3 | 66 '--| dev D3 |
67 '--------' 67 '--------'
68 68
69 When there is an access to D1, this happens: 69 When there is an access to D1, this happens:
70 70
71 1. Someone issues an I2C transfer to D1. 71 1. Someone issues an I2C transfer to D1.
72 2. M1 locks muxes on its parent (the root ada 72 2. M1 locks muxes on its parent (the root adapter in this case).
73 3. M1 calls ->select to ready the mux. 73 3. M1 calls ->select to ready the mux.
74 4. M1 (presumably) does some I2C transfers as 74 4. M1 (presumably) does some I2C transfers as part of its select.
75 These transfers are normal I2C transfers t 75 These transfers are normal I2C transfers that locks the parent
76 adapter. 76 adapter.
77 5. M1 feeds the I2C transfer from step 1 to i 77 5. M1 feeds the I2C transfer from step 1 to its parent adapter as a
78 normal I2C transfer that locks the parent 78 normal I2C transfer that locks the parent adapter.
79 6. M1 calls ->deselect, if it has one. 79 6. M1 calls ->deselect, if it has one.
80 7. Same rules as in step 4, but for ->deselec 80 7. Same rules as in step 4, but for ->deselect.
81 8. M1 unlocks muxes on its parent. 81 8. M1 unlocks muxes on its parent.
82 82
83 This means that accesses to D2 are lockout out 83 This means that accesses to D2 are lockout out for the full duration
84 of the entire operation. But accesses to D3 ar 84 of the entire operation. But accesses to D3 are possibly interleaved
85 at any point. 85 at any point.
86 86
87 Mux-locked caveats 87 Mux-locked caveats
88 ~~~~~~~~~~~~~~~~~~ 88 ~~~~~~~~~~~~~~~~~~
89 89
90 When using a mux-locked mux, be aware of the f 90 When using a mux-locked mux, be aware of the following restrictions:
91 91
92 [ML1] 92 [ML1]
93 If you build a topology with a mux-locked mu 93 If you build a topology with a mux-locked mux being the parent
94 of a parent-locked mux, this might break the 94 of a parent-locked mux, this might break the expectation from the
95 parent-locked mux that the root adapter is l 95 parent-locked mux that the root adapter is locked during the
96 transaction. 96 transaction.
97 97
98 [ML2] 98 [ML2]
99 It is not safe to build arbitrary topologies 99 It is not safe to build arbitrary topologies with two (or more)
100 mux-locked muxes that are not siblings, when 100 mux-locked muxes that are not siblings, when there are address
101 collisions between the devices on the child 101 collisions between the devices on the child adapters of these
102 non-sibling muxes. 102 non-sibling muxes.
103 103
104 I.e. the select-transfer-deselect transactio 104 I.e. the select-transfer-deselect transaction targeting e.g. device
105 address 0x42 behind mux-one may be interleav 105 address 0x42 behind mux-one may be interleaved with a similar
106 operation targeting device address 0x42 behi 106 operation targeting device address 0x42 behind mux-two. The
107 intent with such a topology would in this hy 107 intent with such a topology would in this hypothetical example
108 be that mux-one and mux-two should not be se 108 be that mux-one and mux-two should not be selected simultaneously,
109 but mux-locked muxes do not guarantee that i 109 but mux-locked muxes do not guarantee that in all topologies.
110 110
111 [ML3] 111 [ML3]
112 A mux-locked mux cannot be used by a driver 112 A mux-locked mux cannot be used by a driver for auto-closing
113 gates/muxes, i.e. something that closes auto 113 gates/muxes, i.e. something that closes automatically after a given
114 number (one, in most cases) of I2C transfers 114 number (one, in most cases) of I2C transfers. Unrelated I2C transfers
115 may creep in and close prematurely. 115 may creep in and close prematurely.
116 116
117 [ML4] 117 [ML4]
118 If any non-I2C operation in the mux driver c 118 If any non-I2C operation in the mux driver changes the I2C mux state,
119 the driver has to lock the root adapter duri 119 the driver has to lock the root adapter during that operation.
120 Otherwise garbage may appear on the bus as s 120 Otherwise garbage may appear on the bus as seen from devices
121 behind the mux, when an unrelated I2C transf 121 behind the mux, when an unrelated I2C transfer is in flight during
122 the non-I2C mux-changing operation. 122 the non-I2C mux-changing operation.
123 123
124 124
125 Parent-locked muxes 125 Parent-locked muxes
126 ------------------- 126 -------------------
127 127
128 Parent-locked muxes lock the parent adapter du 128 Parent-locked muxes lock the parent adapter during the full select-
129 transfer-deselect transaction. The implication 129 transfer-deselect transaction. The implication is that the mux driver
130 has to ensure that any and all I2C transfers t 130 has to ensure that any and all I2C transfers through that parent
131 adapter during the transaction are unlocked I2 131 adapter during the transaction are unlocked I2C transfers (using e.g.
132 __i2c_transfer), or a deadlock will follow. 132 __i2c_transfer), or a deadlock will follow.
133 133
134 Parent-locked Example 134 Parent-locked Example
135 ~~~~~~~~~~~~~~~~~~~~~ 135 ~~~~~~~~~~~~~~~~~~~~~
136 136
137 :: 137 ::
138 138
139 .----------. .--------. 139 .----------. .--------.
140 .--------. | parent- |-----| dev D1 | 140 .--------. | parent- |-----| dev D1 |
141 | root |--+--| locked | '--------' 141 | root |--+--| locked | '--------'
142 '--------' | | mux M1 |--. .--------. 142 '--------' | | mux M1 |--. .--------.
143 | '----------' '--| dev D2 | 143 | '----------' '--| dev D2 |
144 | .--------. '--------' 144 | .--------. '--------'
145 '--| dev D3 | 145 '--| dev D3 |
146 '--------' 146 '--------'
147 147
148 When there is an access to D1, this happens: 148 When there is an access to D1, this happens:
149 149
150 1. Someone issues an I2C transfer to D1. 150 1. Someone issues an I2C transfer to D1.
151 2. M1 locks muxes on its parent (the root ad 151 2. M1 locks muxes on its parent (the root adapter in this case).
152 3. M1 locks its parent adapter. 152 3. M1 locks its parent adapter.
153 4. M1 calls ->select to ready the mux. 153 4. M1 calls ->select to ready the mux.
154 5. If M1 does any I2C transfers (on this roo 154 5. If M1 does any I2C transfers (on this root adapter) as part of
155 its select, those transfers must be unloc 155 its select, those transfers must be unlocked I2C transfers so
156 that they do not deadlock the root adapte 156 that they do not deadlock the root adapter.
157 6. M1 feeds the I2C transfer from step 1 to 157 6. M1 feeds the I2C transfer from step 1 to the root adapter as an
158 unlocked I2C transfer, so that it does no 158 unlocked I2C transfer, so that it does not deadlock the parent
159 adapter. 159 adapter.
160 7. M1 calls ->deselect, if it has one. 160 7. M1 calls ->deselect, if it has one.
161 8. Same rules as in step 5, but for ->desele 161 8. Same rules as in step 5, but for ->deselect.
162 9. M1 unlocks its parent adapter. 162 9. M1 unlocks its parent adapter.
163 10. M1 unlocks muxes on its parent. 163 10. M1 unlocks muxes on its parent.
164 164
165 This means that accesses to both D2 and D3 are 165 This means that accesses to both D2 and D3 are locked out for the full
166 duration of the entire operation. 166 duration of the entire operation.
167 167
168 Parent-locked Caveats 168 Parent-locked Caveats
169 ~~~~~~~~~~~~~~~~~~~~~ 169 ~~~~~~~~~~~~~~~~~~~~~
170 170
171 When using a parent-locked mux, be aware of th 171 When using a parent-locked mux, be aware of the following restrictions:
172 172
173 [PL1] 173 [PL1]
174 If you build a topology with a parent-locked 174 If you build a topology with a parent-locked mux being the child
175 of another mux, this might break a possible 175 of another mux, this might break a possible assumption from the
176 child mux that the root adapter is unused be 176 child mux that the root adapter is unused between its select op
177 and the actual transfer (e.g. if the child m 177 and the actual transfer (e.g. if the child mux is auto-closing
178 and the parent mux issues I2C transfers as p 178 and the parent mux issues I2C transfers as part of its select).
179 This is especially the case if the parent mu 179 This is especially the case if the parent mux is mux-locked, but
180 it may also happen if the parent mux is pare 180 it may also happen if the parent mux is parent-locked.
181 181
182 [PL2] 182 [PL2]
183 If select/deselect calls out to other subsys 183 If select/deselect calls out to other subsystems such as gpio,
184 pinctrl, regmap or iio, it is essential that 184 pinctrl, regmap or iio, it is essential that any I2C transfers
185 caused by these subsystems are unlocked. Thi 185 caused by these subsystems are unlocked. This can be convoluted to
186 accomplish, maybe even impossible if an acce 186 accomplish, maybe even impossible if an acceptably clean solution
187 is sought. 187 is sought.
188 188
189 189
190 Complex Examples 190 Complex Examples
191 ================ 191 ================
192 192
193 Parent-locked mux as parent of parent-locked m 193 Parent-locked mux as parent of parent-locked mux
194 ---------------------------------------------- 194 ------------------------------------------------
195 195
196 This is a useful topology, but it can be bad:: 196 This is a useful topology, but it can be bad::
197 197
198 .----------. .--------- 198 .----------. .----------. .--------.
199 .--------. | parent- |-----| parent- 199 .--------. | parent- |-----| parent- |-----| dev D1 |
200 | root |--+--| locked | | locked 200 | root |--+--| locked | | locked | '--------'
201 '--------' | | mux M1 |--. | mux M2 201 '--------' | | mux M1 |--. | mux M2 |--. .--------.
202 | '----------' | '--------- 202 | '----------' | '----------' '--| dev D2 |
203 | .--------. | .--------. 203 | .--------. | .--------. '--------'
204 '--| dev D4 | '--| dev D3 | 204 '--| dev D4 | '--| dev D3 |
205 '--------' '--------' 205 '--------' '--------'
206 206
207 When any device is accessed, all other devices 207 When any device is accessed, all other devices are locked out for
208 the full duration of the operation (both muxes 208 the full duration of the operation (both muxes lock their parent,
209 and specifically when M2 requests its parent t 209 and specifically when M2 requests its parent to lock, M1 passes
210 the buck to the root adapter). 210 the buck to the root adapter).
211 211
212 This topology is bad if M2 is an auto-closing 212 This topology is bad if M2 is an auto-closing mux and M1->select
213 issues any unlocked I2C transfers on the root 213 issues any unlocked I2C transfers on the root adapter that may leak
214 through and be seen by the M2 adapter, thus cl 214 through and be seen by the M2 adapter, thus closing M2 prematurely.
215 215
216 216
217 Mux-locked mux as parent of mux-locked mux 217 Mux-locked mux as parent of mux-locked mux
218 ------------------------------------------ 218 ------------------------------------------
219 219
220 This is a good topology:: 220 This is a good topology::
221 221
222 .----------. .--------- 222 .----------. .----------. .--------.
223 .--------. | mux- |-----| mux- 223 .--------. | mux- |-----| mux- |-----| dev D1 |
224 | root |--+--| locked | | locked 224 | root |--+--| locked | | locked | '--------'
225 '--------' | | mux M1 |--. | mux M2 225 '--------' | | mux M1 |--. | mux M2 |--. .--------.
226 | '----------' | '--------- 226 | '----------' | '----------' '--| dev D2 |
227 | .--------. | .--------. 227 | .--------. | .--------. '--------'
228 '--| dev D4 | '--| dev D3 | 228 '--| dev D4 | '--| dev D3 |
229 '--------' '--------' 229 '--------' '--------'
230 230
231 When device D1 is accessed, accesses to D2 are 231 When device D1 is accessed, accesses to D2 are locked out for the
232 full duration of the operation (muxes on the t 232 full duration of the operation (muxes on the top child adapter of M1
233 are locked). But accesses to D3 and D4 are pos 233 are locked). But accesses to D3 and D4 are possibly interleaved at
234 any point. 234 any point.
235 235
236 Accesses to D3 locks out D1 and D2, but access 236 Accesses to D3 locks out D1 and D2, but accesses to D4 are still possibly
237 interleaved. 237 interleaved.
238 238
239 239
240 Mux-locked mux as parent of parent-locked mux 240 Mux-locked mux as parent of parent-locked mux
241 --------------------------------------------- 241 ---------------------------------------------
242 242
243 This is probably a bad topology:: 243 This is probably a bad topology::
244 244
245 .----------. .--------- 245 .----------. .----------. .--------.
246 .--------. | mux- |-----| parent- 246 .--------. | mux- |-----| parent- |-----| dev D1 |
247 | root |--+--| locked | | locked 247 | root |--+--| locked | | locked | '--------'
248 '--------' | | mux M1 |--. | mux M2 248 '--------' | | mux M1 |--. | mux M2 |--. .--------.
249 | '----------' | '--------- 249 | '----------' | '----------' '--| dev D2 |
250 | .--------. | .--------. 250 | .--------. | .--------. '--------'
251 '--| dev D4 | '--| dev D3 | 251 '--| dev D4 | '--| dev D3 |
252 '--------' '--------' 252 '--------' '--------'
253 253
254 When device D1 is accessed, accesses to D2 and 254 When device D1 is accessed, accesses to D2 and D3 are locked out
255 for the full duration of the operation (M1 loc 255 for the full duration of the operation (M1 locks child muxes on the
256 root adapter). But accesses to D4 are possibly 256 root adapter). But accesses to D4 are possibly interleaved at any
257 point. 257 point.
258 258
259 This kind of topology is generally not suitabl 259 This kind of topology is generally not suitable and should probably
260 be avoided. The reason is that M2 probably ass 260 be avoided. The reason is that M2 probably assumes that there will
261 be no I2C transfers during its calls to ->sele 261 be no I2C transfers during its calls to ->select and ->deselect, and
262 if there are, any such transfers might appear 262 if there are, any such transfers might appear on the slave side of M2
263 as partial I2C transfers, i.e. garbage or wors 263 as partial I2C transfers, i.e. garbage or worse. This might cause
264 device lockups and/or other problems. 264 device lockups and/or other problems.
265 265
266 The topology is especially troublesome if M2 i 266 The topology is especially troublesome if M2 is an auto-closing
267 mux. In that case, any interleaved accesses to 267 mux. In that case, any interleaved accesses to D4 might close M2
268 prematurely, as might any I2C transfers part o 268 prematurely, as might any I2C transfers part of M1->select.
269 269
270 But if M2 is not making the above stated assum 270 But if M2 is not making the above stated assumption, and if M2 is not
271 auto-closing, the topology is fine. 271 auto-closing, the topology is fine.
272 272
273 273
274 Parent-locked mux as parent of mux-locked mux 274 Parent-locked mux as parent of mux-locked mux
275 --------------------------------------------- 275 ---------------------------------------------
276 276
277 This is a good topology:: 277 This is a good topology::
278 278
279 .----------. .--------- 279 .----------. .----------. .--------.
280 .--------. | parent- |-----| mux- 280 .--------. | parent- |-----| mux- |-----| dev D1 |
281 | root |--+--| locked | | locked 281 | root |--+--| locked | | locked | '--------'
282 '--------' | | mux M1 |--. | mux M2 282 '--------' | | mux M1 |--. | mux M2 |--. .--------.
283 | '----------' | '--------- 283 | '----------' | '----------' '--| dev D2 |
284 | .--------. | .--------. 284 | .--------. | .--------. '--------'
285 '--| dev D4 | '--| dev D3 | 285 '--| dev D4 | '--| dev D3 |
286 '--------' '--------' 286 '--------' '--------'
287 287
288 When D1 is accessed, accesses to D2 are locked 288 When D1 is accessed, accesses to D2 are locked out for the full
289 duration of the operation (muxes on the top ch 289 duration of the operation (muxes on the top child adapter of M1
290 are locked). Accesses to D3 and D4 are possibl 290 are locked). Accesses to D3 and D4 are possibly interleaved at
291 any point, just as is expected for mux-locked 291 any point, just as is expected for mux-locked muxes.
292 292
293 When D3 or D4 are accessed, everything else is 293 When D3 or D4 are accessed, everything else is locked out. For D3
294 accesses, M1 locks the root adapter. For D4 ac 294 accesses, M1 locks the root adapter. For D4 accesses, the root
295 adapter is locked directly. 295 adapter is locked directly.
296 296
297 297
298 Two mux-locked sibling muxes 298 Two mux-locked sibling muxes
299 ---------------------------- 299 ----------------------------
300 300
301 This is a good topology:: 301 This is a good topology::
302 302
303 .--------. 303 .--------.
304 .----------. .--| dev D1 | 304 .----------. .--| dev D1 |
305 | mux- |--' '--------' 305 | mux- |--' '--------'
306 .--| locked | .--------. 306 .--| locked | .--------.
307 | | mux M1 |-----| dev D2 | 307 | | mux M1 |-----| dev D2 |
308 | '----------' '--------' 308 | '----------' '--------'
309 | .----------. .--------. 309 | .----------. .--------.
310 .--------. | | mux- |-----| dev D3 | 310 .--------. | | mux- |-----| dev D3 |
311 | root |--+--| locked | '--------' 311 | root |--+--| locked | '--------'
312 '--------' | | mux M2 |--. .--------. 312 '--------' | | mux M2 |--. .--------.
313 | '----------' '--| dev D4 | 313 | '----------' '--| dev D4 |
314 | .--------. '--------' 314 | .--------. '--------'
315 '--| dev D5 | 315 '--| dev D5 |
316 '--------' 316 '--------'
317 317
318 When D1 is accessed, accesses to D2, D3 and D4 318 When D1 is accessed, accesses to D2, D3 and D4 are locked out. But
319 accesses to D5 may be interleaved at any time. 319 accesses to D5 may be interleaved at any time.
320 320
321 321
322 Two parent-locked sibling muxes 322 Two parent-locked sibling muxes
323 ------------------------------- 323 -------------------------------
324 324
325 This is a good topology:: 325 This is a good topology::
326 326
327 .--------. 327 .--------.
328 .----------. .--| dev D1 | 328 .----------. .--| dev D1 |
329 | parent- |--' '--------' 329 | parent- |--' '--------'
330 .--| locked | .--------. 330 .--| locked | .--------.
331 | | mux M1 |-----| dev D2 | 331 | | mux M1 |-----| dev D2 |
332 | '----------' '--------' 332 | '----------' '--------'
333 | .----------. .--------. 333 | .----------. .--------.
334 .--------. | | parent- |-----| dev D3 | 334 .--------. | | parent- |-----| dev D3 |
335 | root |--+--| locked | '--------' 335 | root |--+--| locked | '--------'
336 '--------' | | mux M2 |--. .--------. 336 '--------' | | mux M2 |--. .--------.
337 | '----------' '--| dev D4 | 337 | '----------' '--| dev D4 |
338 | .--------. '--------' 338 | .--------. '--------'
339 '--| dev D5 | 339 '--| dev D5 |
340 '--------' 340 '--------'
341 341
342 When any device is accessed, accesses to all o 342 When any device is accessed, accesses to all other devices are locked
343 out. 343 out.
344 344
345 345
346 Mux-locked and parent-locked sibling muxes 346 Mux-locked and parent-locked sibling muxes
347 ------------------------------------------ 347 ------------------------------------------
348 348
349 This is a good topology:: 349 This is a good topology::
350 350
351 .--------. 351 .--------.
352 .----------. .--| dev D1 | 352 .----------. .--| dev D1 |
353 | mux- |--' '--------' 353 | mux- |--' '--------'
354 .--| locked | .--------. 354 .--| locked | .--------.
355 | | mux M1 |-----| dev D2 | 355 | | mux M1 |-----| dev D2 |
356 | '----------' '--------' 356 | '----------' '--------'
357 | .----------. .--------. 357 | .----------. .--------.
358 .--------. | | parent- |-----| dev D3 | 358 .--------. | | parent- |-----| dev D3 |
359 | root |--+--| locked | '--------' 359 | root |--+--| locked | '--------'
360 '--------' | | mux M2 |--. .--------. 360 '--------' | | mux M2 |--. .--------.
361 | '----------' '--| dev D4 | 361 | '----------' '--| dev D4 |
362 | .--------. '--------' 362 | .--------. '--------'
363 '--| dev D5 | 363 '--| dev D5 |
364 '--------' 364 '--------'
365 365
366 When D1 or D2 are accessed, accesses to D3 and 366 When D1 or D2 are accessed, accesses to D3 and D4 are locked out while
367 accesses to D5 may interleave. When D3 or D4 a 367 accesses to D5 may interleave. When D3 or D4 are accessed, accesses to
368 all other devices are locked out. 368 all other devices are locked out.
369 369
370 370
371 Mux type of existing device drivers 371 Mux type of existing device drivers
372 =================================== 372 ===================================
373 373
374 Whether a device is mux-locked or parent-locke 374 Whether a device is mux-locked or parent-locked depends on its
375 implementation. The following list was correct 375 implementation. The following list was correct at the time of writing:
376 376
377 In drivers/i2c/muxes/: 377 In drivers/i2c/muxes/:
378 378
379 ====================== ==================== 379 ====================== =============================================
380 i2c-arb-gpio-challenge Parent-locked 380 i2c-arb-gpio-challenge Parent-locked
381 i2c-mux-gpio Normally parent-lock 381 i2c-mux-gpio Normally parent-locked, mux-locked iff
382 all involved gpio pi 382 all involved gpio pins are controlled by the
383 same I2C root adapte 383 same I2C root adapter that they mux.
384 i2c-mux-gpmux Normally parent-lock 384 i2c-mux-gpmux Normally parent-locked, mux-locked iff
385 specified in device- 385 specified in device-tree.
386 i2c-mux-ltc4306 Mux-locked 386 i2c-mux-ltc4306 Mux-locked
387 i2c-mux-mlxcpld Parent-locked 387 i2c-mux-mlxcpld Parent-locked
388 i2c-mux-pca9541 Parent-locked 388 i2c-mux-pca9541 Parent-locked
389 i2c-mux-pca954x Parent-locked 389 i2c-mux-pca954x Parent-locked
390 i2c-mux-pinctrl Normally parent-lock 390 i2c-mux-pinctrl Normally parent-locked, mux-locked iff
391 all involved pinctrl 391 all involved pinctrl devices are controlled
392 by the same I2C root 392 by the same I2C root adapter that they mux.
393 i2c-mux-reg Parent-locked 393 i2c-mux-reg Parent-locked
394 ====================== ==================== 394 ====================== =============================================
395 395
396 In drivers/iio/: 396 In drivers/iio/:
397 397
398 ====================== ==================== 398 ====================== =============================================
399 gyro/mpu3050 Mux-locked 399 gyro/mpu3050 Mux-locked
400 imu/inv_mpu6050/ Mux-locked 400 imu/inv_mpu6050/ Mux-locked
401 ====================== ==================== 401 ====================== =============================================
402 402
403 In drivers/media/: 403 In drivers/media/:
404 404
405 ======================= ==================== 405 ======================= =============================================
406 dvb-frontends/lgdt3306a Mux-locked 406 dvb-frontends/lgdt3306a Mux-locked
407 dvb-frontends/m88ds3103 Parent-locked 407 dvb-frontends/m88ds3103 Parent-locked
408 dvb-frontends/rtl2830 Parent-locked 408 dvb-frontends/rtl2830 Parent-locked
409 dvb-frontends/rtl2832 Mux-locked 409 dvb-frontends/rtl2832 Mux-locked
410 dvb-frontends/si2168 Mux-locked 410 dvb-frontends/si2168 Mux-locked
411 usb/cx231xx/ Parent-locked 411 usb/cx231xx/ Parent-locked
412 ======================= ==================== 412 ======================= =============================================
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