1 .. SPDX-License-Identifier: GPL-2.0-only 1 .. SPDX-License-Identifier: GPL-2.0-only
2 2
3 ============= 3 =============
4 AD4695 driver 4 AD4695 driver
5 ============= 5 =============
6 6
7 ADC driver for Analog Devices Inc. AD4695 and 7 ADC driver for Analog Devices Inc. AD4695 and similar devices. The module name
8 is ``ad4695``. 8 is ``ad4695``.
9 9
10 10
11 Supported devices 11 Supported devices
12 ================= 12 =================
13 13
14 The following chips are supported by this driv 14 The following chips are supported by this driver:
15 15
16 * `AD4695 <https://www.analog.com/AD4695>`_ 16 * `AD4695 <https://www.analog.com/AD4695>`_
17 * `AD4696 <https://www.analog.com/AD4696>`_ 17 * `AD4696 <https://www.analog.com/AD4696>`_
18 * `AD4697 <https://www.analog.com/AD4697>`_ 18 * `AD4697 <https://www.analog.com/AD4697>`_
19 * `AD4698 <https://www.analog.com/AD4698>`_ 19 * `AD4698 <https://www.analog.com/AD4698>`_
20 20
21 21
22 Supported features 22 Supported features
23 ================== 23 ==================
24 24
25 SPI wiring modes 25 SPI wiring modes
26 ---------------- 26 ----------------
27 27
28 The driver currently supports the following SP 28 The driver currently supports the following SPI wiring configuration:
29 29
30 4-wire mode 30 4-wire mode
31 ^^^^^^^^^^^ 31 ^^^^^^^^^^^
32 32
33 In this mode, CNV and CS are tied together and 33 In this mode, CNV and CS are tied together and there is a single SDO line.
34 34
35 .. code-block:: 35 .. code-block::
36 36
37 +-------------+ +-------------+ 37 +-------------+ +-------------+
38 | CS |<-+------| CS | 38 | CS |<-+------| CS |
39 | CNV |<-+ | | 39 | CNV |<-+ | |
40 | ADC | | HOST | 40 | ADC | | HOST |
41 | | | | 41 | | | |
42 | SDI |<--------| SDO | 42 | SDI |<--------| SDO |
43 | SDO |-------->| SDI | 43 | SDO |-------->| SDI |
44 | SCLK |<--------| SCLK | 44 | SCLK |<--------| SCLK |
45 +-------------+ +-------------+ 45 +-------------+ +-------------+
46 46
47 To use this mode, in the device tree, omit the 47 To use this mode, in the device tree, omit the ``cnv-gpios`` and
48 ``spi-rx-bus-width`` properties. 48 ``spi-rx-bus-width`` properties.
49 49
50 Channel configuration 50 Channel configuration
51 --------------------- 51 ---------------------
52 52
53 Since the chip supports multiple ways to confi 53 Since the chip supports multiple ways to configure each channel, this must be
54 described in the device tree based on what is 54 described in the device tree based on what is actually wired up to the inputs.
55 55
56 There are three typical configurations: 56 There are three typical configurations:
57 57
58 An ``INx`` pin is used as the positive input w 58 An ``INx`` pin is used as the positive input with the ``REFGND``, ``COM`` or
59 the next ``INx`` pin as the negative input. 59 the next ``INx`` pin as the negative input.
60 60
61 Pairing with REFGND 61 Pairing with REFGND
62 ^^^^^^^^^^^^^^^^^^^ 62 ^^^^^^^^^^^^^^^^^^^
63 63
64 Each ``INx`` pin can be used as a pseudo-diffe 64 Each ``INx`` pin can be used as a pseudo-differential input in conjunction with
65 the ``REFGND`` pin. The device tree will look 65 the ``REFGND`` pin. The device tree will look like this:
66 66
67 .. code-block:: 67 .. code-block::
68 68
69 channel@0 { 69 channel@0 {
70 reg = <0>; /* IN0 */ 70 reg = <0>; /* IN0 */
71 }; 71 };
72 72
73 If no other channel properties are needed (e.g 73 If no other channel properties are needed (e.g. ``adi,no-high-z``), the channel
74 node can be omitted entirely. 74 node can be omitted entirely.
75 75
76 This will appear on the IIO bus as the ``volta 76 This will appear on the IIO bus as the ``voltage0`` channel. The processed value
77 (*raw × scale*) will be the voltage present o 77 (*raw × scale*) will be the voltage present on the ``IN0`` pin relative to
78 ``REFGND``. (Offset is always 0 when pairing w 78 ``REFGND``. (Offset is always 0 when pairing with ``REFGND``.)
79 79
80 Pairing with COM 80 Pairing with COM
81 ^^^^^^^^^^^^^^^^ 81 ^^^^^^^^^^^^^^^^
82 82
83 Each ``INx`` pin can be used as a pseudo-diffe 83 Each ``INx`` pin can be used as a pseudo-differential input in conjunction with
84 the ``COM`` pin. The device tree will look lik 84 the ``COM`` pin. The device tree will look like this:
85 85
86 .. code-block:: 86 .. code-block::
87 87
88 com-supply = <&vref_div_2>; 88 com-supply = <&vref_div_2>;
89 89
90 channel@1 { 90 channel@1 {
91 reg = <1>; /* IN1 */ 91 reg = <1>; /* IN1 */
92 common-mode-channel = <AD4695_COMMON_M 92 common-mode-channel = <AD4695_COMMON_MODE_COM>;
93 bipolar; 93 bipolar;
94 }; 94 };
95 95
96 This will appear on the IIO bus as the ``volta 96 This will appear on the IIO bus as the ``voltage1`` channel. The processed value
97 (*(raw + offset) × scale*) will be the voltag 97 (*(raw + offset) × scale*) will be the voltage measured on the ``IN1`` pin
98 relative to ``REFGND``. (The offset is determi 98 relative to ``REFGND``. (The offset is determined by the ``com-supply`` voltage.)
99 99
100 The macro comes from: 100 The macro comes from:
101 101
102 .. code-block:: 102 .. code-block::
103 103
104 #include <dt-bindings/iio/adi,ad4695.h> 104 #include <dt-bindings/iio/adi,ad4695.h>
105 105
106 Pairing two INx pins 106 Pairing two INx pins
107 ^^^^^^^^^^^^^^^^^^^^ 107 ^^^^^^^^^^^^^^^^^^^^
108 108
109 An even-numbered ``INx`` pin and the following 109 An even-numbered ``INx`` pin and the following odd-numbered ``INx`` pin can be
110 used as a pseudo-differential input. The devic 110 used as a pseudo-differential input. The device tree for using ``IN2`` as the
111 positive input and ``IN3`` as the negative inp 111 positive input and ``IN3`` as the negative input will look like this:
112 112
113 .. code-block:: 113 .. code-block::
114 114
115 in3-supply = <&vref_div_2>; 115 in3-supply = <&vref_div_2>;
116 116
117 channel@2 { 117 channel@2 {
118 reg = <2>; /* IN2 */ 118 reg = <2>; /* IN2 */
119 common-mode-channel = <3>; /* IN3 */ 119 common-mode-channel = <3>; /* IN3 */
120 bipolar; 120 bipolar;
121 }; 121 };
122 122
123 This will appear on the IIO bus as the ``volta 123 This will appear on the IIO bus as the ``voltage2`` channel. The processed value
124 (*(raw + offset) × scale*) will be the voltag 124 (*(raw + offset) × scale*) will be the voltage measured on the ``IN1`` pin
125 relative to ``REFGND``. (Offset is determined 125 relative to ``REFGND``. (Offset is determined by the ``in3-supply`` voltage.)
126 126
127 VCC supply 127 VCC supply
128 ---------- 128 ----------
129 129
130 The chip supports being powered by an external 130 The chip supports being powered by an external LDO via the ``VCC`` input or an
131 internal LDO via the ``LDO_IN`` input. The dri 131 internal LDO via the ``LDO_IN`` input. The driver looks at the device tree to
132 determine which is being used. If ``ldo-supply 132 determine which is being used. If ``ldo-supply`` is present, then the internal
133 LDO is used. If ``vcc-supply`` is present, the 133 LDO is used. If ``vcc-supply`` is present, then the external LDO is used and
134 the internal LDO is disabled. 134 the internal LDO is disabled.
135 135
136 Reference voltage 136 Reference voltage
137 ----------------- 137 -----------------
138 138
139 The chip supports an external reference voltag 139 The chip supports an external reference voltage via the ``REF`` input or an
140 internal buffered reference voltage via the `` 140 internal buffered reference voltage via the ``REFIN`` input. The driver looks
141 at the device tree to determine which is being 141 at the device tree to determine which is being used. If ``ref-supply`` is
142 present, then the external reference voltage i 142 present, then the external reference voltage is used and the internal buffer is
143 disabled. If ``refin-supply`` is present, then 143 disabled. If ``refin-supply`` is present, then the internal buffered reference
144 voltage is used. 144 voltage is used.
145 145
146 Gain/offset calibration 146 Gain/offset calibration
147 ----------------------- 147 -----------------------
148 148
149 System calibration is supported using the chan 149 System calibration is supported using the channel gain and offset registers via
150 the ``calibscale`` and ``calibbias`` attribute 150 the ``calibscale`` and ``calibbias`` attributes respectively.
151 151
152 Unimplemented features 152 Unimplemented features
153 ---------------------- 153 ----------------------
154 154
155 - Additional wiring modes 155 - Additional wiring modes
156 - Threshold events 156 - Threshold events
157 - Oversampling 157 - Oversampling
158 - GPIO support 158 - GPIO support
159 - CRC support 159 - CRC support
160 160
161 Device buffers 161 Device buffers
162 ============== 162 ==============
163 163
164 This driver supports hardware triggered buffer 164 This driver supports hardware triggered buffers. This uses the "advanced
165 sequencer" feature of the chip to trigger a bu 165 sequencer" feature of the chip to trigger a burst of conversions.
166 166
167 Also see :doc:`iio_devbuf` for more general in 167 Also see :doc:`iio_devbuf` for more general information.
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