1 ===================== 1 ============================
2 LINUX KERNEL MEMORY B 2 LINUX KERNEL MEMORY BARRIERS
3 ===================== 3 ============================
4 4
5 By: David Howells <dhowells@redhat.com> 5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.ibm.com> !! 6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
7 Will Deacon <will.deacon@arm.com> 7 Will Deacon <will.deacon@arm.com>
8 Peter Zijlstra <peterz@infradead.org> 8 Peter Zijlstra <peterz@infradead.org>
9 9
10 ========== 10 ==========
11 DISCLAIMER 11 DISCLAIMER
12 ========== 12 ==========
13 13
14 This document is not a specification; it is in 14 This document is not a specification; it is intentionally (for the sake of
15 brevity) and unintentionally (due to being hum 15 brevity) and unintentionally (due to being human) incomplete. This document is
16 meant as a guide to using the various memory b 16 meant as a guide to using the various memory barriers provided by Linux, but
17 in case of any doubt (and there are many) plea !! 17 in case of any doubt (and there are many) please ask.
18 resolved by referring to the formal memory con <<
19 documentation at tools/memory-model/. Neverth <<
20 model should be viewed as the collective opini <<
21 than as an infallible oracle. <<
22 18
23 To repeat, this document is not a specificatio 19 To repeat, this document is not a specification of what Linux expects from
24 hardware. 20 hardware.
25 21
26 The purpose of this document is twofold: 22 The purpose of this document is twofold:
27 23
28 (1) to specify the minimum functionality that 24 (1) to specify the minimum functionality that one can rely on for any
29 particular barrier, and 25 particular barrier, and
30 26
31 (2) to provide a guide as to how to use the b 27 (2) to provide a guide as to how to use the barriers that are available.
32 28
33 Note that an architecture can provide more tha 29 Note that an architecture can provide more than the minimum requirement
34 for any particular barrier, but if the archite !! 30 for any particular barrier, but if the architecure provides less than
35 that, that architecture is incorrect. 31 that, that architecture is incorrect.
36 32
37 Note also that it is possible that a barrier m 33 Note also that it is possible that a barrier may be a no-op for an
38 architecture because the way that arch works r 34 architecture because the way that arch works renders an explicit barrier
39 unnecessary in that case. 35 unnecessary in that case.
40 36
41 37
42 ======== 38 ========
43 CONTENTS 39 CONTENTS
44 ======== 40 ========
45 41
46 (*) Abstract memory access model. 42 (*) Abstract memory access model.
47 43
48 - Device operations. 44 - Device operations.
49 - Guarantees. 45 - Guarantees.
50 46
51 (*) What are memory barriers? 47 (*) What are memory barriers?
52 48
53 - Varieties of memory barrier. 49 - Varieties of memory barrier.
54 - What may not be assumed about memory ba 50 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical !! 51 - Data dependency barriers.
56 - Control dependencies. 52 - Control dependencies.
57 - SMP barrier pairing. 53 - SMP barrier pairing.
58 - Examples of memory barrier sequences. 54 - Examples of memory barrier sequences.
59 - Read memory barriers vs load speculatio 55 - Read memory barriers vs load speculation.
60 - Multicopy atomicity. !! 56 - Transitivity
61 57
62 (*) Explicit kernel barriers. 58 (*) Explicit kernel barriers.
63 59
64 - Compiler barrier. 60 - Compiler barrier.
65 - CPU memory barriers. 61 - CPU memory barriers.
>> 62 - MMIO write barrier.
66 63
67 (*) Implicit kernel memory barriers. 64 (*) Implicit kernel memory barriers.
68 65
69 - Lock acquisition functions. 66 - Lock acquisition functions.
70 - Interrupt disabling functions. 67 - Interrupt disabling functions.
71 - Sleep and wake-up functions. 68 - Sleep and wake-up functions.
72 - Miscellaneous functions. 69 - Miscellaneous functions.
73 70
74 (*) Inter-CPU acquiring barrier effects. 71 (*) Inter-CPU acquiring barrier effects.
75 72
76 - Acquires vs memory accesses. 73 - Acquires vs memory accesses.
>> 74 - Acquires vs I/O accesses.
77 75
78 (*) Where are memory barriers needed? 76 (*) Where are memory barriers needed?
79 77
80 - Interprocessor interaction. 78 - Interprocessor interaction.
81 - Atomic operations. 79 - Atomic operations.
82 - Accessing devices. 80 - Accessing devices.
83 - Interrupts. 81 - Interrupts.
84 82
85 (*) Kernel I/O barrier effects. 83 (*) Kernel I/O barrier effects.
86 84
87 (*) Assumed minimum execution ordering model. 85 (*) Assumed minimum execution ordering model.
88 86
89 (*) The effects of the cpu cache. 87 (*) The effects of the cpu cache.
90 88
91 - Cache coherency. 89 - Cache coherency.
92 - Cache coherency vs DMA. 90 - Cache coherency vs DMA.
93 - Cache coherency vs MMIO. 91 - Cache coherency vs MMIO.
94 92
95 (*) The things CPUs get up to. 93 (*) The things CPUs get up to.
96 94
97 - And then there's the Alpha. 95 - And then there's the Alpha.
98 - Virtual Machine Guests. 96 - Virtual Machine Guests.
99 97
100 (*) Example uses. 98 (*) Example uses.
101 99
102 - Circular buffers. 100 - Circular buffers.
103 101
104 (*) References. 102 (*) References.
105 103
106 104
107 ============================ 105 ============================
108 ABSTRACT MEMORY ACCESS MODEL 106 ABSTRACT MEMORY ACCESS MODEL
109 ============================ 107 ============================
110 108
111 Consider the following abstract model of the s 109 Consider the following abstract model of the system:
112 110
113 : : 111 : :
114 : : 112 : :
115 : : 113 : :
116 +-------+ : +--------+ : 114 +-------+ : +--------+ : +-------+
117 | | : | | : 115 | | : | | : | |
118 | | : | | : 116 | | : | | : | |
119 | CPU 1 |<----->| Memory |<--- 117 | CPU 1 |<----->| Memory |<----->| CPU 2 |
120 | | : | | : 118 | | : | | : | |
121 | | : | | : 119 | | : | | : | |
122 +-------+ : +--------+ : 120 +-------+ : +--------+ : +-------+
123 ^ : ^ : 121 ^ : ^ : ^
124 | : | : 122 | : | : |
125 | : | : 123 | : | : |
126 | : v : 124 | : v : |
127 | : +--------+ : 125 | : +--------+ : |
128 | : | | : 126 | : | | : |
129 | : | | : 127 | : | | : |
130 +---------->| Device |<--- 128 +---------->| Device |<----------+
131 : | | : 129 : | | :
132 : | | : 130 : | | :
133 : +--------+ : 131 : +--------+ :
134 : : 132 : :
135 133
136 Each CPU executes a program that generates mem 134 Each CPU executes a program that generates memory access operations. In the
137 abstract CPU, memory operation ordering is ver 135 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
138 perform the memory operations in any order it 136 perform the memory operations in any order it likes, provided program causality
139 appears to be maintained. Similarly, the comp 137 appears to be maintained. Similarly, the compiler may also arrange the
140 instructions it emits in any order it likes, p 138 instructions it emits in any order it likes, provided it doesn't affect the
141 apparent operation of the program. 139 apparent operation of the program.
142 140
143 So in the above diagram, the effects of the me 141 So in the above diagram, the effects of the memory operations performed by a
144 CPU are perceived by the rest of the system as 142 CPU are perceived by the rest of the system as the operations cross the
145 interface between the CPU and rest of the syst 143 interface between the CPU and rest of the system (the dotted lines).
146 144
147 145
148 For example, consider the following sequence o 146 For example, consider the following sequence of events:
149 147
150 CPU 1 CPU 2 148 CPU 1 CPU 2
151 =============== =============== 149 =============== ===============
152 { A == 1; B == 2 } 150 { A == 1; B == 2 }
153 A = 3; x = B; 151 A = 3; x = B;
154 B = 4; y = A; 152 B = 4; y = A;
155 153
156 The set of accesses as seen by the memory syst 154 The set of accesses as seen by the memory system in the middle can be arranged
157 in 24 different combinations: 155 in 24 different combinations:
158 156
159 STORE A=3, STORE B=4, y=LOAD 157 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
160 STORE A=3, STORE B=4, x=LOAD 158 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
161 STORE A=3, y=LOAD A->3, STORE 159 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
162 STORE A=3, y=LOAD A->3, x=LOAD 160 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
163 STORE A=3, x=LOAD B->2, STORE 161 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
164 STORE A=3, x=LOAD B->2, y=LOAD 162 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
165 STORE B=4, STORE A=3, y=LOAD 163 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
166 STORE B=4, ... 164 STORE B=4, ...
167 ... 165 ...
168 166
169 and can thus result in four different combinat 167 and can thus result in four different combinations of values:
170 168
171 x == 2, y == 1 169 x == 2, y == 1
172 x == 2, y == 3 170 x == 2, y == 3
173 x == 4, y == 1 171 x == 4, y == 1
174 x == 4, y == 3 172 x == 4, y == 3
175 173
176 174
177 Furthermore, the stores committed by a CPU to 175 Furthermore, the stores committed by a CPU to the memory system may not be
178 perceived by the loads made by another CPU in 176 perceived by the loads made by another CPU in the same order as the stores were
179 committed. 177 committed.
180 178
181 179
182 As a further example, consider this sequence o 180 As a further example, consider this sequence of events:
183 181
184 CPU 1 CPU 2 182 CPU 1 CPU 2
185 =============== =============== 183 =============== ===============
186 { A == 1, B == 2, C == 3, P == &A, Q = 184 { A == 1, B == 2, C == 3, P == &A, Q == &C }
187 B = 4; Q = P; 185 B = 4; Q = P;
188 P = &B; D = *Q; !! 186 P = &B D = *Q;
189 187
190 There is an obvious address dependency here, a !! 188 There is an obvious data dependency here, as the value loaded into D depends on
191 on the address retrieved from P by CPU 2. At !! 189 the address retrieved from P by CPU 2. At the end of the sequence, any of the
192 the following results are possible: !! 190 following results are possible:
193 191
194 (Q == &A) and (D == 1) 192 (Q == &A) and (D == 1)
195 (Q == &B) and (D == 2) 193 (Q == &B) and (D == 2)
196 (Q == &B) and (D == 4) 194 (Q == &B) and (D == 4)
197 195
198 Note that CPU 2 will never try and load C into 196 Note that CPU 2 will never try and load C into D because the CPU will load P
199 into Q before issuing the load of *Q. 197 into Q before issuing the load of *Q.
200 198
201 199
202 DEVICE OPERATIONS 200 DEVICE OPERATIONS
203 ----------------- 201 -----------------
204 202
205 Some devices present their control interfaces 203 Some devices present their control interfaces as collections of memory
206 locations, but the order in which the control 204 locations, but the order in which the control registers are accessed is very
207 important. For instance, imagine an ethernet 205 important. For instance, imagine an ethernet card with a set of internal
208 registers that are accessed through an address 206 registers that are accessed through an address port register (A) and a data
209 port register (D). To read internal register 207 port register (D). To read internal register 5, the following code might then
210 be used: 208 be used:
211 209
212 *A = 5; 210 *A = 5;
213 x = *D; 211 x = *D;
214 212
215 but this might show up as either of the follow 213 but this might show up as either of the following two sequences:
216 214
217 STORE *A = 5, x = LOAD *D 215 STORE *A = 5, x = LOAD *D
218 x = LOAD *D, STORE *A = 5 216 x = LOAD *D, STORE *A = 5
219 217
220 the second of which will almost certainly resu 218 the second of which will almost certainly result in a malfunction, since it set
221 the address _after_ attempting to read the reg 219 the address _after_ attempting to read the register.
222 220
223 221
224 GUARANTEES 222 GUARANTEES
225 ---------- 223 ----------
226 224
227 There are some minimal guarantees that may be 225 There are some minimal guarantees that may be expected of a CPU:
228 226
229 (*) On any given CPU, dependent memory access 227 (*) On any given CPU, dependent memory accesses will be issued in order, with
230 respect to itself. This means that for: 228 respect to itself. This means that for:
231 229
232 Q = READ_ONCE(P); D = READ_ONCE(*Q); !! 230 Q = READ_ONCE(P); smp_read_barrier_depends(); D = READ_ONCE(*Q);
233 231
234 the CPU will issue the following memory o 232 the CPU will issue the following memory operations:
235 233
236 Q = LOAD P, D = LOAD *Q 234 Q = LOAD P, D = LOAD *Q
237 235
238 and always in that order. However, on DE !! 236 and always in that order. On most systems, smp_read_barrier_depends()
239 emits a memory-barrier instruction, so th !! 237 does nothing, but it is required for DEC Alpha. The READ_ONCE()
240 instead issue the following memory operat !! 238 is required to prevent compiler mischief. Please note that you
241 !! 239 should normally use something like rcu_dereference() instead of
242 Q = LOAD P, MEMORY_BARRIER, D = LOAD * !! 240 open-coding smp_read_barrier_depends().
243 <<
244 Whether on DEC Alpha or not, the READ_ONC <<
245 mischief. <<
246 241
247 (*) Overlapping loads and stores within a par 242 (*) Overlapping loads and stores within a particular CPU will appear to be
248 ordered within that CPU. This means that 243 ordered within that CPU. This means that for:
249 244
250 a = READ_ONCE(*X); WRITE_ONCE(*X, b); 245 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
251 246
252 the CPU will only issue the following seq 247 the CPU will only issue the following sequence of memory operations:
253 248
254 a = LOAD *X, STORE *X = b 249 a = LOAD *X, STORE *X = b
255 250
256 And for: 251 And for:
257 252
258 WRITE_ONCE(*X, c); d = READ_ONCE(*X); 253 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
259 254
260 the CPU will only issue: 255 the CPU will only issue:
261 256
262 STORE *X = c, d = LOAD *X 257 STORE *X = c, d = LOAD *X
263 258
264 (Loads and stores overlap if they are tar 259 (Loads and stores overlap if they are targeted at overlapping pieces of
265 memory). 260 memory).
266 261
267 And there are a number of things that _must_ o 262 And there are a number of things that _must_ or _must_not_ be assumed:
268 263
269 (*) It _must_not_ be assumed that the compile 264 (*) It _must_not_ be assumed that the compiler will do what you want
270 with memory references that are not prote 265 with memory references that are not protected by READ_ONCE() and
271 WRITE_ONCE(). Without them, the compiler 266 WRITE_ONCE(). Without them, the compiler is within its rights to
272 do all sorts of "creative" transformation 267 do all sorts of "creative" transformations, which are covered in
273 the COMPILER BARRIER section. 268 the COMPILER BARRIER section.
274 269
275 (*) It _must_not_ be assumed that independent 270 (*) It _must_not_ be assumed that independent loads and stores will be issued
276 in the order given. This means that for: 271 in the order given. This means that for:
277 272
278 X = *A; Y = *B; *D = Z; 273 X = *A; Y = *B; *D = Z;
279 274
280 we may get any of the following sequences 275 we may get any of the following sequences:
281 276
282 X = LOAD *A, Y = LOAD *B, STORE *D = 277 X = LOAD *A, Y = LOAD *B, STORE *D = Z
283 X = LOAD *A, STORE *D = Z, Y = LOAD * 278 X = LOAD *A, STORE *D = Z, Y = LOAD *B
284 Y = LOAD *B, X = LOAD *A, STORE *D = 279 Y = LOAD *B, X = LOAD *A, STORE *D = Z
285 Y = LOAD *B, STORE *D = Z, X = LOAD * 280 Y = LOAD *B, STORE *D = Z, X = LOAD *A
286 STORE *D = Z, X = LOAD *A, Y = LOAD * 281 STORE *D = Z, X = LOAD *A, Y = LOAD *B
287 STORE *D = Z, Y = LOAD *B, X = LOAD * 282 STORE *D = Z, Y = LOAD *B, X = LOAD *A
288 283
289 (*) It _must_ be assumed that overlapping mem 284 (*) It _must_ be assumed that overlapping memory accesses may be merged or
290 discarded. This means that for: 285 discarded. This means that for:
291 286
292 X = *A; Y = *(A + 4); 287 X = *A; Y = *(A + 4);
293 288
294 we may get any one of the following seque 289 we may get any one of the following sequences:
295 290
296 X = LOAD *A; Y = LOAD *(A + 4); 291 X = LOAD *A; Y = LOAD *(A + 4);
297 Y = LOAD *(A + 4); X = LOAD *A; 292 Y = LOAD *(A + 4); X = LOAD *A;
298 {X, Y} = LOAD {*A, *(A + 4) }; 293 {X, Y} = LOAD {*A, *(A + 4) };
299 294
300 And for: 295 And for:
301 296
302 *A = X; *(A + 4) = Y; 297 *A = X; *(A + 4) = Y;
303 298
304 we may get any of: 299 we may get any of:
305 300
306 STORE *A = X; STORE *(A + 4) = Y; 301 STORE *A = X; STORE *(A + 4) = Y;
307 STORE *(A + 4) = Y; STORE *A = X; 302 STORE *(A + 4) = Y; STORE *A = X;
308 STORE {*A, *(A + 4) } = {X, Y}; 303 STORE {*A, *(A + 4) } = {X, Y};
309 304
310 And there are anti-guarantees: 305 And there are anti-guarantees:
311 306
312 (*) These guarantees do not apply to bitfield 307 (*) These guarantees do not apply to bitfields, because compilers often
313 generate code to modify these using non-a 308 generate code to modify these using non-atomic read-modify-write
314 sequences. Do not attempt to use bitfiel 309 sequences. Do not attempt to use bitfields to synchronize parallel
315 algorithms. 310 algorithms.
316 311
317 (*) Even in cases where bitfields are protect 312 (*) Even in cases where bitfields are protected by locks, all fields
318 in a given bitfield must be protected by 313 in a given bitfield must be protected by one lock. If two fields
319 in a given bitfield are protected by diff 314 in a given bitfield are protected by different locks, the compiler's
320 non-atomic read-modify-write sequences ca 315 non-atomic read-modify-write sequences can cause an update to one
321 field to corrupt the value of an adjacent 316 field to corrupt the value of an adjacent field.
322 317
323 (*) These guarantees apply only to properly a 318 (*) These guarantees apply only to properly aligned and sized scalar
324 variables. "Properly sized" currently me 319 variables. "Properly sized" currently means variables that are
325 the same size as "char", "short", "int" a 320 the same size as "char", "short", "int" and "long". "Properly
326 aligned" means the natural alignment, thu 321 aligned" means the natural alignment, thus no constraints for
327 "char", two-byte alignment for "short", f 322 "char", two-byte alignment for "short", four-byte alignment for
328 "int", and either four-byte or eight-byte 323 "int", and either four-byte or eight-byte alignment for "long",
329 on 32-bit and 64-bit systems, respectivel 324 on 32-bit and 64-bit systems, respectively. Note that these
330 guarantees were introduced into the C11 s 325 guarantees were introduced into the C11 standard, so beware when
331 using older pre-C11 compilers (for exampl 326 using older pre-C11 compilers (for example, gcc 4.6). The portion
332 of the standard containing this guarantee 327 of the standard containing this guarantee is Section 3.14, which
333 defines "memory location" as follows: 328 defines "memory location" as follows:
334 329
335 memory location 330 memory location
336 either an object of scalar typ 331 either an object of scalar type, or a maximal sequence
337 of adjacent bit-fields all hav 332 of adjacent bit-fields all having nonzero width
338 333
339 NOTE 1: Two threads of executi 334 NOTE 1: Two threads of execution can update and access
340 separate memory locations with 335 separate memory locations without interfering with
341 each other. 336 each other.
342 337
343 NOTE 2: A bit-field and an adj 338 NOTE 2: A bit-field and an adjacent non-bit-field member
344 are in separate memory locatio 339 are in separate memory locations. The same applies
345 to two bit-fields, if one is d 340 to two bit-fields, if one is declared inside a nested
346 structure declaration and the 341 structure declaration and the other is not, or if the two
347 are separated by a zero-length 342 are separated by a zero-length bit-field declaration,
348 or if they are separated by a 343 or if they are separated by a non-bit-field member
349 declaration. It is not safe to 344 declaration. It is not safe to concurrently update two
350 bit-fields in the same structu 345 bit-fields in the same structure if all members declared
351 between them are also bit-fiel 346 between them are also bit-fields, no matter what the
352 sizes of those intervening bit 347 sizes of those intervening bit-fields happen to be.
353 348
354 349
355 ========================= 350 =========================
356 WHAT ARE MEMORY BARRIERS? 351 WHAT ARE MEMORY BARRIERS?
357 ========================= 352 =========================
358 353
359 As can be seen above, independent memory opera 354 As can be seen above, independent memory operations are effectively performed
360 in random order, but this can be a problem for 355 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
361 What is required is some way of intervening to 356 What is required is some way of intervening to instruct the compiler and the
362 CPU to restrict the order. 357 CPU to restrict the order.
363 358
364 Memory barriers are such interventions. They 359 Memory barriers are such interventions. They impose a perceived partial
365 ordering over the memory operations on either 360 ordering over the memory operations on either side of the barrier.
366 361
367 Such enforcement is important because the CPUs 362 Such enforcement is important because the CPUs and other devices in a system
368 can use a variety of tricks to improve perform 363 can use a variety of tricks to improve performance, including reordering,
369 deferral and combination of memory operations; 364 deferral and combination of memory operations; speculative loads; speculative
370 branch prediction and various types of caching 365 branch prediction and various types of caching. Memory barriers are used to
371 override or suppress these tricks, allowing th 366 override or suppress these tricks, allowing the code to sanely control the
372 interaction of multiple CPUs and/or devices. 367 interaction of multiple CPUs and/or devices.
373 368
374 369
375 VARIETIES OF MEMORY BARRIER 370 VARIETIES OF MEMORY BARRIER
376 --------------------------- 371 ---------------------------
377 372
378 Memory barriers come in four basic varieties: 373 Memory barriers come in four basic varieties:
379 374
380 (1) Write (or store) memory barriers. 375 (1) Write (or store) memory barriers.
381 376
382 A write memory barrier gives a guarantee 377 A write memory barrier gives a guarantee that all the STORE operations
383 specified before the barrier will appear 378 specified before the barrier will appear to happen before all the STORE
384 operations specified after the barrier wi 379 operations specified after the barrier with respect to the other
385 components of the system. 380 components of the system.
386 381
387 A write barrier is a partial ordering on 382 A write barrier is a partial ordering on stores only; it is not required
388 to have any effect on loads. 383 to have any effect on loads.
389 384
390 A CPU can be viewed as committing a seque 385 A CPU can be viewed as committing a sequence of store operations to the
391 memory system as time progresses. All st !! 386 memory system as time progresses. All stores before a write barrier will
392 will occur _before_ all the stores after !! 387 occur in the sequence _before_ all the stores after the write barrier.
>> 388
>> 389 [!] Note that write barriers should normally be paired with read or data
>> 390 dependency barriers; see the "SMP barrier pairing" subsection.
393 391
394 [!] Note that write barriers should norma <<
395 address-dependency barriers; see the "SMP <<
396 392
>> 393 (2) Data dependency barriers.
397 394
398 (2) Address-dependency barriers (historical). !! 395 A data dependency barrier is a weaker form of read barrier. In the case
399 [!] This section is marked as HISTORICAL: !! 396 where two loads are performed such that the second depends on the result
400 smp_read_barrier_depends() macro, the sem !! 397 of the first (eg: the first load retrieves the address to which the second
401 implicit in all marked accesses. For mor !! 398 load will be directed), a data dependency barrier would be required to
402 including how compiler transformations ca !! 399 make sure that the target of the second load is updated before the address
403 dependencies, see Documentation/RCU/rcu_d !! 400 obtained by the first load is accessed.
404 !! 401
405 An address-dependency barrier is a weaker !! 402 A data dependency barrier is a partial ordering on interdependent loads
406 case where two loads are performed such t !! 403 only; it is not required to have any effect on stores, independent loads
407 result of the first (eg: the first load r !! 404 or overlapping loads.
408 the second load will be directed), an add <<
409 be required to make sure that the target <<
410 after the address obtained by the first l <<
411 <<
412 An address-dependency barrier is a partia <<
413 loads only; it is not required to have an <<
414 loads or overlapping loads. <<
415 405
416 As mentioned in (1), the other CPUs in th 406 As mentioned in (1), the other CPUs in the system can be viewed as
417 committing sequences of stores to the mem 407 committing sequences of stores to the memory system that the CPU being
418 considered can then perceive. An address !! 408 considered can then perceive. A data dependency barrier issued by the CPU
419 the CPU under consideration guarantees th !! 409 under consideration guarantees that for any load preceding it, if that
420 if that load touches one of a sequence of !! 410 load touches one of a sequence of stores from another CPU, then by the
421 by the time the barrier completes, the ef !! 411 time the barrier completes, the effects of all the stores prior to that
422 that touched by the load will be percepti !! 412 touched by the load will be perceptible to any loads issued after the data
423 the address-dependency barrier. !! 413 dependency barrier.
424 414
425 See the "Examples of memory barrier seque 415 See the "Examples of memory barrier sequences" subsection for diagrams
426 showing the ordering constraints. 416 showing the ordering constraints.
427 417
428 [!] Note that the first load really has t !! 418 [!] Note that the first load really has to have a _data_ dependency and
429 not a control dependency. If the address 419 not a control dependency. If the address for the second load is dependent
430 on the first load, but the dependency is 420 on the first load, but the dependency is through a conditional rather than
431 actually loading the address itself, then 421 actually loading the address itself, then it's a _control_ dependency and
432 a full read barrier or better is required 422 a full read barrier or better is required. See the "Control dependencies"
433 subsection for more information. 423 subsection for more information.
434 424
435 [!] Note that address-dependency barriers !! 425 [!] Note that data dependency barriers should normally be paired with
436 write barriers; see the "SMP barrier pair 426 write barriers; see the "SMP barrier pairing" subsection.
437 427
438 [!] Kernel release v5.9 removed kernel AP <<
439 dependency barriers. Nowadays, APIs for <<
440 variables such as READ_ONCE() and rcu_der <<
441 address-dependency barriers. <<
442 428
443 (3) Read (or load) memory barriers. 429 (3) Read (or load) memory barriers.
444 430
445 A read barrier is an address-dependency b !! 431 A read barrier is a data dependency barrier plus a guarantee that all the
446 the LOAD operations specified before the !! 432 LOAD operations specified before the barrier will appear to happen before
447 before all the LOAD operations specified !! 433 all the LOAD operations specified after the barrier with respect to the
448 the other components of the system. !! 434 other components of the system.
449 435
450 A read barrier is a partial ordering on l 436 A read barrier is a partial ordering on loads only; it is not required to
451 have any effect on stores. 437 have any effect on stores.
452 438
453 Read memory barriers imply address-depend !! 439 Read memory barriers imply data dependency barriers, and so can substitute
454 substitute for them. !! 440 for them.
455 441
456 [!] Note that read barriers should normal 442 [!] Note that read barriers should normally be paired with write barriers;
457 see the "SMP barrier pairing" subsection. 443 see the "SMP barrier pairing" subsection.
458 444
459 445
460 (4) General memory barriers. 446 (4) General memory barriers.
461 447
462 A general memory barrier gives a guarante 448 A general memory barrier gives a guarantee that all the LOAD and STORE
463 operations specified before the barrier w 449 operations specified before the barrier will appear to happen before all
464 the LOAD and STORE operations specified a 450 the LOAD and STORE operations specified after the barrier with respect to
465 the other components of the system. 451 the other components of the system.
466 452
467 A general memory barrier is a partial ord 453 A general memory barrier is a partial ordering over both loads and stores.
468 454
469 General memory barriers imply both read a 455 General memory barriers imply both read and write memory barriers, and so
470 can substitute for either. 456 can substitute for either.
471 457
472 458
473 And a couple of implicit varieties: 459 And a couple of implicit varieties:
474 460
475 (5) ACQUIRE operations. 461 (5) ACQUIRE operations.
476 462
477 This acts as a one-way permeable barrier. 463 This acts as a one-way permeable barrier. It guarantees that all memory
478 operations after the ACQUIRE operation wi 464 operations after the ACQUIRE operation will appear to happen after the
479 ACQUIRE operation with respect to the oth 465 ACQUIRE operation with respect to the other components of the system.
480 ACQUIRE operations include LOCK operation 466 ACQUIRE operations include LOCK operations and both smp_load_acquire()
481 and smp_cond_load_acquire() operations. !! 467 and smp_cond_acquire() operations. The later builds the necessary ACQUIRE
>> 468 semantics from relying on a control dependency and smp_rmb().
482 469
483 Memory operations that occur before an AC 470 Memory operations that occur before an ACQUIRE operation may appear to
484 happen after it completes. 471 happen after it completes.
485 472
486 An ACQUIRE operation should almost always 473 An ACQUIRE operation should almost always be paired with a RELEASE
487 operation. 474 operation.
488 475
489 476
490 (6) RELEASE operations. 477 (6) RELEASE operations.
491 478
492 This also acts as a one-way permeable bar 479 This also acts as a one-way permeable barrier. It guarantees that all
493 memory operations before the RELEASE oper 480 memory operations before the RELEASE operation will appear to happen
494 before the RELEASE operation with respect 481 before the RELEASE operation with respect to the other components of the
495 system. RELEASE operations include UNLOCK 482 system. RELEASE operations include UNLOCK operations and
496 smp_store_release() operations. 483 smp_store_release() operations.
497 484
498 Memory operations that occur after a RELE 485 Memory operations that occur after a RELEASE operation may appear to
499 happen before it completes. 486 happen before it completes.
500 487
501 The use of ACQUIRE and RELEASE operations 488 The use of ACQUIRE and RELEASE operations generally precludes the need
502 for other sorts of memory barrier. In ad !! 489 for other sorts of memory barrier (but note the exceptions mentioned in
503 -not- guaranteed to act as a full memory !! 490 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
504 ACQUIRE on a given variable, all memory a !! 491 pair is -not- guaranteed to act as a full memory barrier. However, after
>> 492 an ACQUIRE on a given variable, all memory accesses preceding any prior
505 RELEASE on that same variable are guarant 493 RELEASE on that same variable are guaranteed to be visible. In other
506 words, within a given variable's critical 494 words, within a given variable's critical section, all accesses of all
507 previous critical sections for that varia 495 previous critical sections for that variable are guaranteed to have
508 completed. 496 completed.
509 497
510 This means that ACQUIRE acts as a minimal 498 This means that ACQUIRE acts as a minimal "acquire" operation and
511 RELEASE acts as a minimal "release" opera 499 RELEASE acts as a minimal "release" operation.
512 500
513 A subset of the atomic operations described in !! 501 A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
514 RELEASE variants in addition to fully-ordered !! 502 and RELEASE variants in addition to fully-ordered and relaxed (no barrier
515 semantics) definitions. For compound atomics 503 semantics) definitions. For compound atomics performing both a load and a
516 store, ACQUIRE semantics apply only to the loa 504 store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
517 only to the store portion of the operation. 505 only to the store portion of the operation.
518 506
519 Memory barriers are only required where there' 507 Memory barriers are only required where there's a possibility of interaction
520 between two CPUs or between a CPU and a device 508 between two CPUs or between a CPU and a device. If it can be guaranteed that
521 there won't be any such interaction in any par 509 there won't be any such interaction in any particular piece of code, then
522 memory barriers are unnecessary in that piece 510 memory barriers are unnecessary in that piece of code.
523 511
524 512
525 Note that these are the _minimum_ guarantees. 513 Note that these are the _minimum_ guarantees. Different architectures may give
526 more substantial guarantees, but they may _not 514 more substantial guarantees, but they may _not_ be relied upon outside of arch
527 specific code. 515 specific code.
528 516
529 517
530 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS? 518 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
531 ---------------------------------------------- 519 ----------------------------------------------
532 520
533 There are certain things that the Linux kernel 521 There are certain things that the Linux kernel memory barriers do not guarantee:
534 522
535 (*) There is no guarantee that any of the mem 523 (*) There is no guarantee that any of the memory accesses specified before a
536 memory barrier will be _complete_ by the 524 memory barrier will be _complete_ by the completion of a memory barrier
537 instruction; the barrier can be considere 525 instruction; the barrier can be considered to draw a line in that CPU's
538 access queue that accesses of the appropr 526 access queue that accesses of the appropriate type may not cross.
539 527
540 (*) There is no guarantee that issuing a memo 528 (*) There is no guarantee that issuing a memory barrier on one CPU will have
541 any direct effect on another CPU or any o 529 any direct effect on another CPU or any other hardware in the system. The
542 indirect effect will be the order in whic 530 indirect effect will be the order in which the second CPU sees the effects
543 of the first CPU's accesses occur, but se 531 of the first CPU's accesses occur, but see the next point:
544 532
545 (*) There is no guarantee that a CPU will see 533 (*) There is no guarantee that a CPU will see the correct order of effects
546 from a second CPU's accesses, even _if_ t 534 from a second CPU's accesses, even _if_ the second CPU uses a memory
547 barrier, unless the first CPU _also_ uses 535 barrier, unless the first CPU _also_ uses a matching memory barrier (see
548 the subsection on "SMP Barrier Pairing"). 536 the subsection on "SMP Barrier Pairing").
549 537
550 (*) There is no guarantee that some interveni 538 (*) There is no guarantee that some intervening piece of off-the-CPU
551 hardware[*] will not reorder the memory a 539 hardware[*] will not reorder the memory accesses. CPU cache coherency
552 mechanisms should propagate the indirect 540 mechanisms should propagate the indirect effects of a memory barrier
553 between CPUs, but might not do so in orde 541 between CPUs, but might not do so in order.
554 542
555 [*] For information on bus mastering D 543 [*] For information on bus mastering DMA and coherency please read:
556 544
557 Documentation/driver-api/pci/pci.r !! 545 Documentation/PCI/pci.txt
558 Documentation/core-api/dma-api-how !! 546 Documentation/DMA-API-HOWTO.txt
559 Documentation/core-api/dma-api.rst !! 547 Documentation/DMA-API.txt
560 548
561 549
562 ADDRESS-DEPENDENCY BARRIERS (HISTORICAL) !! 550 DATA DEPENDENCY BARRIERS
563 ---------------------------------------- !! 551 ------------------------
564 [!] This section is marked as HISTORICAL: it c <<
565 smp_read_barrier_depends() macro, the semantic <<
566 in all marked accesses. For more up-to-date i <<
567 how compiler transformations can sometimes bre <<
568 see Documentation/RCU/rcu_dereference.rst. <<
569 <<
570 As of v4.15 of the Linux kernel, an smp_mb() w <<
571 DEC Alpha, which means that about the only peo <<
572 to this section are those working on DEC Alpha <<
573 and those working on READ_ONCE() itself. For <<
574 those who are interested in the history, here <<
575 address-dependency barriers. <<
576 <<
577 [!] While address dependencies are observed in <<
578 load-to-store relations, address-dependency ba <<
579 for load-to-store situations. <<
580 552
581 The requirement of address-dependency barriers !! 553 The usage requirements of data dependency barriers are a little subtle, and
582 it's not always obvious that they're needed. 554 it's not always obvious that they're needed. To illustrate, consider the
583 following sequence of events: 555 following sequence of events:
584 556
585 CPU 1 CPU 2 557 CPU 1 CPU 2
586 =============== =============== 558 =============== ===============
587 { A == 1, B == 2, C == 3, P == &A, Q = 559 { A == 1, B == 2, C == 3, P == &A, Q == &C }
588 B = 4; 560 B = 4;
589 <write barrier> 561 <write barrier>
590 WRITE_ONCE(P, &B); !! 562 WRITE_ONCE(P, &B)
591 Q = READ_ONCE_OL !! 563 Q = READ_ONCE(P);
592 D = *Q; 564 D = *Q;
593 565
594 [!] READ_ONCE_OLD() corresponds to READ_ONCE() !! 566 There's a clear data dependency here, and it would seem that by the end of the
595 doesn't imply an address-dependency barrier. !! 567 sequence, Q must be either &A or &B, and that:
596 <<
597 There's a clear address dependency here, and i <<
598 the sequence, Q must be either &A or &B, and t <<
599 568
600 (Q == &A) implies (D == 1) 569 (Q == &A) implies (D == 1)
601 (Q == &B) implies (D == 4) 570 (Q == &B) implies (D == 4)
602 571
603 But! CPU 2's perception of P may be updated _ 572 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
604 leading to the following situation: 573 leading to the following situation:
605 574
606 (Q == &B) and (D == 2) ???? 575 (Q == &B) and (D == 2) ????
607 576
608 While this may seem like a failure of coherenc !! 577 Whilst this may seem like a failure of coherency or causality maintenance, it
609 isn't, and this behaviour can be observed on c 578 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
610 Alpha). 579 Alpha).
611 580
612 To deal with this, READ_ONCE() provides an imp !! 581 To deal with this, a data dependency barrier or better must be inserted
613 since kernel release v4.15: !! 582 between the address load and the data load:
614 583
615 CPU 1 CPU 2 584 CPU 1 CPU 2
616 =============== =============== 585 =============== ===============
617 { A == 1, B == 2, C == 3, P == &A, Q = 586 { A == 1, B == 2, C == 3, P == &A, Q == &C }
618 B = 4; 587 B = 4;
619 <write barrier> 588 <write barrier>
620 WRITE_ONCE(P, &B); 589 WRITE_ONCE(P, &B);
621 Q = READ_ONCE(P) 590 Q = READ_ONCE(P);
622 <implicit addres !! 591 <data dependency barrier>
623 D = *Q; 592 D = *Q;
624 593
625 This enforces the occurrence of one of the two 594 This enforces the occurrence of one of the two implications, and prevents the
626 third possibility from arising. 595 third possibility from arising.
627 596
628 !! 597 A data-dependency barrier must also order against dependent writes:
629 [!] Note that this extremely counterintuitive <<
630 machines with split caches, so that, for examp <<
631 even-numbered cache lines and the other bank p <<
632 lines. The pointer P might be stored in an od <<
633 variable B might be stored in an even-numbered <<
634 even-numbered bank of the reading CPU's cache <<
635 odd-numbered bank is idle, one can see the new <<
636 but the old value of the variable B (2). <<
637 <<
638 <<
639 An address-dependency barrier is not required <<
640 because the CPUs that the Linux kernel support <<
641 are certain (1) that the write will actually h <<
642 the write, and (3) of the value to be written. <<
643 But please carefully read the "CONTROL DEPENDE <<
644 Documentation/RCU/rcu_dereference.rst file: T <<
645 dependencies in a great many highly creative w <<
646 598
647 CPU 1 CPU 2 599 CPU 1 CPU 2
648 =============== =============== 600 =============== ===============
649 { A == 1, B == 2, C = 3, P == &A, Q == 601 { A == 1, B == 2, C = 3, P == &A, Q == &C }
650 B = 4; 602 B = 4;
651 <write barrier> 603 <write barrier>
652 WRITE_ONCE(P, &B); 604 WRITE_ONCE(P, &B);
653 Q = READ_ONCE_OL !! 605 Q = READ_ONCE(P);
654 WRITE_ONCE(*Q, 5 !! 606 <data dependency barrier>
>> 607 *Q = 5;
655 608
656 Therefore, no address-dependency barrier is re !! 609 The data-dependency barrier must order the read into Q with the store
657 Q with the store into *Q. In other words, thi !! 610 into *Q. This prohibits this outcome:
658 even without an implicit address-dependency ba <<
659 611
660 (Q == &B) && (B == 4) 612 (Q == &B) && (B == 4)
661 613
662 Please note that this pattern should be rare. 614 Please note that this pattern should be rare. After all, the whole point
663 of dependency ordering is to -prevent- writes 615 of dependency ordering is to -prevent- writes to the data structure, along
664 with the expensive cache misses associated wit 616 with the expensive cache misses associated with those writes. This pattern
665 can be used to record rare error conditions an !! 617 can be used to record rare error conditions and the like, and the ordering
666 naturally occurring ordering prevents such rec !! 618 prevents such records from being lost.
667 619
668 620
669 Note well that the ordering provided by an add !! 621 [!] Note that this extremely counterintuitive situation arises most easily on
670 the CPU containing it. See the section on "Mu !! 622 machines with split caches, so that, for example, one cache bank processes
671 more information. !! 623 even-numbered cache lines and the other bank processes odd-numbered cache
>> 624 lines. The pointer P might be stored in an odd-numbered cache line, and the
>> 625 variable B might be stored in an even-numbered cache line. Then, if the
>> 626 even-numbered bank of the reading CPU's cache is extremely busy while the
>> 627 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
>> 628 but the old value of the variable B (2).
672 629
673 630
674 The address-dependency barrier is very importa !! 631 The data dependency barrier is very important to the RCU system,
675 for example. See rcu_assign_pointer() and rcu 632 for example. See rcu_assign_pointer() and rcu_dereference() in
676 include/linux/rcupdate.h. This permits the cu 633 include/linux/rcupdate.h. This permits the current target of an RCU'd
677 pointer to be replaced with a new modified tar 634 pointer to be replaced with a new modified target, without the replacement
678 target appearing to be incompletely initialise 635 target appearing to be incompletely initialised.
679 636
680 See also the subsection on "Cache Coherency" f 637 See also the subsection on "Cache Coherency" for a more thorough example.
681 638
682 639
683 CONTROL DEPENDENCIES 640 CONTROL DEPENDENCIES
684 -------------------- 641 --------------------
685 642
686 Control dependencies can be a bit tricky becau 643 Control dependencies can be a bit tricky because current compilers do
687 not understand them. The purpose of this sect 644 not understand them. The purpose of this section is to help you prevent
688 the compiler's ignorance from breaking your co 645 the compiler's ignorance from breaking your code.
689 646
690 A load-load control dependency requires a full 647 A load-load control dependency requires a full read memory barrier, not
691 simply an (implicit) address-dependency barrie !! 648 simply a data dependency barrier to make it work correctly. Consider the
692 Consider the following bit of code: !! 649 following bit of code:
693 650
694 q = READ_ONCE(a); 651 q = READ_ONCE(a);
695 <implicit address-dependency barrier> <<
696 if (q) { 652 if (q) {
697 /* BUG: No address dependency! !! 653 <data dependency barrier> /* BUG: No data dependency!!! */
698 p = READ_ONCE(b); 654 p = READ_ONCE(b);
699 } 655 }
700 656
701 This will not have the desired effect because !! 657 This will not have the desired effect because there is no actual data
702 dependency, but rather a control dependency th 658 dependency, but rather a control dependency that the CPU may short-circuit
703 by attempting to predict the outcome in advanc 659 by attempting to predict the outcome in advance, so that other CPUs see
704 the load from b as having happened before the !! 660 the load from b as having happened before the load from a. In such a
705 what's actually required is: !! 661 case what's actually required is:
706 662
707 q = READ_ONCE(a); 663 q = READ_ONCE(a);
708 if (q) { 664 if (q) {
709 <read barrier> 665 <read barrier>
710 p = READ_ONCE(b); 666 p = READ_ONCE(b);
711 } 667 }
712 668
713 However, stores are not speculated. This mean 669 However, stores are not speculated. This means that ordering -is- provided
714 for load-store control dependencies, as in the 670 for load-store control dependencies, as in the following example:
715 671
716 q = READ_ONCE(a); 672 q = READ_ONCE(a);
717 if (q) { 673 if (q) {
718 WRITE_ONCE(b, 1); 674 WRITE_ONCE(b, 1);
719 } 675 }
720 676
721 Control dependencies pair normally with other 677 Control dependencies pair normally with other types of barriers.
722 That said, please note that neither READ_ONCE( 678 That said, please note that neither READ_ONCE() nor WRITE_ONCE()
723 are optional! Without the READ_ONCE(), the com 679 are optional! Without the READ_ONCE(), the compiler might combine the
724 load from 'a' with other loads from 'a'. With 680 load from 'a' with other loads from 'a'. Without the WRITE_ONCE(),
725 the compiler might combine the store to 'b' wi 681 the compiler might combine the store to 'b' with other stores to 'b'.
726 Either can result in highly counterintuitive e 682 Either can result in highly counterintuitive effects on ordering.
727 683
728 Worse yet, if the compiler is able to prove (s 684 Worse yet, if the compiler is able to prove (say) that the value of
729 variable 'a' is always non-zero, it would be w 685 variable 'a' is always non-zero, it would be well within its rights
730 to optimize the original example by eliminatin 686 to optimize the original example by eliminating the "if" statement
731 as follows: 687 as follows:
732 688
733 q = a; 689 q = a;
734 b = 1; /* BUG: Compiler and CPU can b 690 b = 1; /* BUG: Compiler and CPU can both reorder!!! */
735 691
736 So don't leave out the READ_ONCE(). 692 So don't leave out the READ_ONCE().
737 693
738 It is tempting to try to enforce ordering on i 694 It is tempting to try to enforce ordering on identical stores on both
739 branches of the "if" statement as follows: 695 branches of the "if" statement as follows:
740 696
741 q = READ_ONCE(a); 697 q = READ_ONCE(a);
742 if (q) { 698 if (q) {
743 barrier(); 699 barrier();
744 WRITE_ONCE(b, 1); 700 WRITE_ONCE(b, 1);
745 do_something(); 701 do_something();
746 } else { 702 } else {
747 barrier(); 703 barrier();
748 WRITE_ONCE(b, 1); 704 WRITE_ONCE(b, 1);
749 do_something_else(); 705 do_something_else();
750 } 706 }
751 707
752 Unfortunately, current compilers will transfor 708 Unfortunately, current compilers will transform this as follows at high
753 optimization levels: 709 optimization levels:
754 710
755 q = READ_ONCE(a); 711 q = READ_ONCE(a);
756 barrier(); 712 barrier();
757 WRITE_ONCE(b, 1); /* BUG: No ordering 713 WRITE_ONCE(b, 1); /* BUG: No ordering vs. load from a!!! */
758 if (q) { 714 if (q) {
759 /* WRITE_ONCE(b, 1); -- moved 715 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */
760 do_something(); 716 do_something();
761 } else { 717 } else {
762 /* WRITE_ONCE(b, 1); -- moved 718 /* WRITE_ONCE(b, 1); -- moved up, BUG!!! */
763 do_something_else(); 719 do_something_else();
764 } 720 }
765 721
766 Now there is no conditional between the load f 722 Now there is no conditional between the load from 'a' and the store to
767 'b', which means that the CPU is within its ri 723 'b', which means that the CPU is within its rights to reorder them:
768 The conditional is absolutely required, and mu 724 The conditional is absolutely required, and must be present in the
769 assembly code even after all compiler optimiza 725 assembly code even after all compiler optimizations have been applied.
770 Therefore, if you need ordering in this exampl 726 Therefore, if you need ordering in this example, you need explicit
771 memory barriers, for example, smp_store_releas 727 memory barriers, for example, smp_store_release():
772 728
773 q = READ_ONCE(a); 729 q = READ_ONCE(a);
774 if (q) { 730 if (q) {
775 smp_store_release(&b, 1); 731 smp_store_release(&b, 1);
776 do_something(); 732 do_something();
777 } else { 733 } else {
778 smp_store_release(&b, 1); 734 smp_store_release(&b, 1);
779 do_something_else(); 735 do_something_else();
780 } 736 }
781 737
782 In contrast, without explicit memory barriers, 738 In contrast, without explicit memory barriers, two-legged-if control
783 ordering is guaranteed only when the stores di 739 ordering is guaranteed only when the stores differ, for example:
784 740
785 q = READ_ONCE(a); 741 q = READ_ONCE(a);
786 if (q) { 742 if (q) {
787 WRITE_ONCE(b, 1); 743 WRITE_ONCE(b, 1);
788 do_something(); 744 do_something();
789 } else { 745 } else {
790 WRITE_ONCE(b, 2); 746 WRITE_ONCE(b, 2);
791 do_something_else(); 747 do_something_else();
792 } 748 }
793 749
794 The initial READ_ONCE() is still required to p 750 The initial READ_ONCE() is still required to prevent the compiler from
795 proving the value of 'a'. 751 proving the value of 'a'.
796 752
797 In addition, you need to be careful what you d 753 In addition, you need to be careful what you do with the local variable 'q',
798 otherwise the compiler might be able to guess 754 otherwise the compiler might be able to guess the value and again remove
799 the needed conditional. For example: 755 the needed conditional. For example:
800 756
801 q = READ_ONCE(a); 757 q = READ_ONCE(a);
802 if (q % MAX) { 758 if (q % MAX) {
803 WRITE_ONCE(b, 1); 759 WRITE_ONCE(b, 1);
804 do_something(); 760 do_something();
805 } else { 761 } else {
806 WRITE_ONCE(b, 2); 762 WRITE_ONCE(b, 2);
807 do_something_else(); 763 do_something_else();
808 } 764 }
809 765
810 If MAX is defined to be 1, then the compiler k 766 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
811 equal to zero, in which case the compiler is w 767 equal to zero, in which case the compiler is within its rights to
812 transform the above code into the following: 768 transform the above code into the following:
813 769
814 q = READ_ONCE(a); 770 q = READ_ONCE(a);
815 WRITE_ONCE(b, 2); 771 WRITE_ONCE(b, 2);
816 do_something_else(); 772 do_something_else();
817 773
818 Given this transformation, the CPU is not requ 774 Given this transformation, the CPU is not required to respect the ordering
819 between the load from variable 'a' and the sto 775 between the load from variable 'a' and the store to variable 'b'. It is
820 tempting to add a barrier(), but this does not 776 tempting to add a barrier(), but this does not help. The conditional
821 is gone, and the barrier won't bring it back. 777 is gone, and the barrier won't bring it back. Therefore, if you are
822 relying on this ordering, you should make sure 778 relying on this ordering, you should make sure that MAX is greater than
823 one, perhaps as follows: 779 one, perhaps as follows:
824 780
825 q = READ_ONCE(a); 781 q = READ_ONCE(a);
826 BUILD_BUG_ON(MAX <= 1); /* Order load 782 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
827 if (q % MAX) { 783 if (q % MAX) {
828 WRITE_ONCE(b, 1); 784 WRITE_ONCE(b, 1);
829 do_something(); 785 do_something();
830 } else { 786 } else {
831 WRITE_ONCE(b, 2); 787 WRITE_ONCE(b, 2);
832 do_something_else(); 788 do_something_else();
833 } 789 }
834 790
835 Please note once again that the stores to 'b' 791 Please note once again that the stores to 'b' differ. If they were
836 identical, as noted earlier, the compiler coul 792 identical, as noted earlier, the compiler could pull this store outside
837 of the 'if' statement. 793 of the 'if' statement.
838 794
839 You must also be careful not to rely too much 795 You must also be careful not to rely too much on boolean short-circuit
840 evaluation. Consider this example: 796 evaluation. Consider this example:
841 797
842 q = READ_ONCE(a); 798 q = READ_ONCE(a);
843 if (q || 1 > 0) 799 if (q || 1 > 0)
844 WRITE_ONCE(b, 1); 800 WRITE_ONCE(b, 1);
845 801
846 Because the first condition cannot fault and t 802 Because the first condition cannot fault and the second condition is
847 always true, the compiler can transform this e 803 always true, the compiler can transform this example as following,
848 defeating control dependency: 804 defeating control dependency:
849 805
850 q = READ_ONCE(a); 806 q = READ_ONCE(a);
851 WRITE_ONCE(b, 1); 807 WRITE_ONCE(b, 1);
852 808
853 This example underscores the need to ensure th 809 This example underscores the need to ensure that the compiler cannot
854 out-guess your code. More generally, although 810 out-guess your code. More generally, although READ_ONCE() does force
855 the compiler to actually emit code for a given 811 the compiler to actually emit code for a given load, it does not force
856 the compiler to use the results. 812 the compiler to use the results.
857 813
858 In addition, control dependencies apply only t 814 In addition, control dependencies apply only to the then-clause and
859 else-clause of the if-statement in question. 815 else-clause of the if-statement in question. In particular, it does
860 not necessarily apply to code following the if 816 not necessarily apply to code following the if-statement:
861 817
862 q = READ_ONCE(a); 818 q = READ_ONCE(a);
863 if (q) { 819 if (q) {
864 WRITE_ONCE(b, 1); 820 WRITE_ONCE(b, 1);
865 } else { 821 } else {
866 WRITE_ONCE(b, 2); 822 WRITE_ONCE(b, 2);
867 } 823 }
868 WRITE_ONCE(c, 1); /* BUG: No ordering 824 WRITE_ONCE(c, 1); /* BUG: No ordering against the read from 'a'. */
869 825
870 It is tempting to argue that there in fact is 826 It is tempting to argue that there in fact is ordering because the
871 compiler cannot reorder volatile accesses and 827 compiler cannot reorder volatile accesses and also cannot reorder
872 the writes to 'b' with the condition. Unfortu 828 the writes to 'b' with the condition. Unfortunately for this line
873 of reasoning, the compiler might compile the t 829 of reasoning, the compiler might compile the two writes to 'b' as
874 conditional-move instructions, as in this fanc 830 conditional-move instructions, as in this fanciful pseudo-assembly
875 language: 831 language:
876 832
877 ld r1,a 833 ld r1,a
878 cmp r1,$0 834 cmp r1,$0
879 cmov,ne r4,$1 835 cmov,ne r4,$1
880 cmov,eq r4,$2 836 cmov,eq r4,$2
881 st r4,b 837 st r4,b
882 st $1,c 838 st $1,c
883 839
884 A weakly ordered CPU would have no dependency 840 A weakly ordered CPU would have no dependency of any sort between the load
885 from 'a' and the store to 'c'. The control de 841 from 'a' and the store to 'c'. The control dependencies would extend
886 only to the pair of cmov instructions and the 842 only to the pair of cmov instructions and the store depending on them.
887 In short, control dependencies apply only to t 843 In short, control dependencies apply only to the stores in the then-clause
888 and else-clause of the if-statement in questio 844 and else-clause of the if-statement in question (including functions
889 invoked by those two clauses), not to code fol 845 invoked by those two clauses), not to code following that if-statement.
890 846
891 !! 847 Finally, control dependencies do -not- provide transitivity. This is
892 Note well that the ordering provided by a cont !! 848 demonstrated by two related examples, with the initial values of
893 to the CPU containing it. See the section on !! 849 'x' and 'y' both being zero:
894 for more information. !! 850
895 !! 851 CPU 0 CPU 1
>> 852 ======================= =======================
>> 853 r1 = READ_ONCE(x); r2 = READ_ONCE(y);
>> 854 if (r1 > 0) if (r2 > 0)
>> 855 WRITE_ONCE(y, 1); WRITE_ONCE(x, 1);
>> 856
>> 857 assert(!(r1 == 1 && r2 == 1));
>> 858
>> 859 The above two-CPU example will never trigger the assert(). However,
>> 860 if control dependencies guaranteed transitivity (which they do not),
>> 861 then adding the following CPU would guarantee a related assertion:
>> 862
>> 863 CPU 2
>> 864 =====================
>> 865 WRITE_ONCE(x, 2);
>> 866
>> 867 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
>> 868
>> 869 But because control dependencies do -not- provide transitivity, the above
>> 870 assertion can fail after the combined three-CPU example completes. If you
>> 871 need the three-CPU example to provide ordering, you will need smp_mb()
>> 872 between the loads and stores in the CPU 0 and CPU 1 code fragments,
>> 873 that is, just before or just after the "if" statements. Furthermore,
>> 874 the original two-CPU example is very fragile and should be avoided.
>> 875
>> 876 These two examples are the LB and WWC litmus tests from this paper:
>> 877 http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
>> 878 site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
896 879
897 In summary: 880 In summary:
898 881
899 (*) Control dependencies can order prior loa 882 (*) Control dependencies can order prior loads against later stores.
900 However, they do -not- guarantee any oth 883 However, they do -not- guarantee any other sort of ordering:
901 Not prior loads against later loads, nor 884 Not prior loads against later loads, nor prior stores against
902 later anything. If you need these other 885 later anything. If you need these other forms of ordering,
903 use smp_rmb(), smp_wmb(), or, in the cas 886 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
904 later loads, smp_mb(). 887 later loads, smp_mb().
905 888
906 (*) If both legs of the "if" statement begin 889 (*) If both legs of the "if" statement begin with identical stores to
907 the same variable, then those stores mus 890 the same variable, then those stores must be ordered, either by
908 preceding both of them with smp_mb() or 891 preceding both of them with smp_mb() or by using smp_store_release()
909 to carry out the stores. Please note th 892 to carry out the stores. Please note that it is -not- sufficient
910 to use barrier() at beginning of each le 893 to use barrier() at beginning of each leg of the "if" statement
911 because, as shown by the example above, 894 because, as shown by the example above, optimizing compilers can
912 destroy the control dependency while res 895 destroy the control dependency while respecting the letter of the
913 barrier() law. 896 barrier() law.
914 897
915 (*) Control dependencies require at least on 898 (*) Control dependencies require at least one run-time conditional
916 between the prior load and the subsequen 899 between the prior load and the subsequent store, and this
917 conditional must involve the prior load. 900 conditional must involve the prior load. If the compiler is able
918 to optimize the conditional away, it wil 901 to optimize the conditional away, it will have also optimized
919 away the ordering. Careful use of READ_ 902 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
920 can help to preserve the needed conditio 903 can help to preserve the needed conditional.
921 904
922 (*) Control dependencies require that the co 905 (*) Control dependencies require that the compiler avoid reordering the
923 dependency into nonexistence. Careful u 906 dependency into nonexistence. Careful use of READ_ONCE() or
924 atomic{,64}_read() can help to preserve 907 atomic{,64}_read() can help to preserve your control dependency.
925 Please see the COMPILER BARRIER section 908 Please see the COMPILER BARRIER section for more information.
926 909
927 (*) Control dependencies apply only to the t 910 (*) Control dependencies apply only to the then-clause and else-clause
928 of the if-statement containing the contr 911 of the if-statement containing the control dependency, including
929 any functions that these two clauses cal 912 any functions that these two clauses call. Control dependencies
930 do -not- apply to code following the if- 913 do -not- apply to code following the if-statement containing the
931 control dependency. 914 control dependency.
932 915
933 (*) Control dependencies pair normally with 916 (*) Control dependencies pair normally with other types of barriers.
934 917
935 (*) Control dependencies do -not- provide mu !! 918 (*) Control dependencies do -not- provide transitivity. If you
936 need all the CPUs to see a given store a !! 919 need transitivity, use smp_mb().
937 920
938 (*) Compilers do not understand control depe 921 (*) Compilers do not understand control dependencies. It is therefore
939 your job to ensure that they do not brea 922 your job to ensure that they do not break your code.
940 923
941 924
942 SMP BARRIER PAIRING 925 SMP BARRIER PAIRING
943 ------------------- 926 -------------------
944 927
945 When dealing with CPU-CPU interactions, certai 928 When dealing with CPU-CPU interactions, certain types of memory barrier should
946 always be paired. A lack of appropriate pairi 929 always be paired. A lack of appropriate pairing is almost certainly an error.
947 930
948 General barriers pair with each other, though 931 General barriers pair with each other, though they also pair with most
949 other types of barriers, albeit without multic !! 932 other types of barriers, albeit without transitivity. An acquire barrier
950 barrier pairs with a release barrier, but both !! 933 pairs with a release barrier, but both may also pair with other barriers,
951 barriers, including of course general barriers !! 934 including of course general barriers. A write barrier pairs with a data
952 with an address-dependency barrier, a control !! 935 dependency barrier, a control dependency, an acquire barrier, a release
953 a release barrier, a read barrier, or a genera !! 936 barrier, a read barrier, or a general barrier. Similarly a read barrier,
954 read barrier, control dependency, or an addres !! 937 control dependency, or a data dependency barrier pairs with a write
955 with a write barrier, an acquire barrier, a re !! 938 barrier, an acquire barrier, a release barrier, or a general barrier:
956 general barrier: <<
957 939
958 CPU 1 CPU 2 940 CPU 1 CPU 2
959 =============== =============== 941 =============== ===============
960 WRITE_ONCE(a, 1); 942 WRITE_ONCE(a, 1);
961 <write barrier> 943 <write barrier>
962 WRITE_ONCE(b, 2); x = READ_ONCE(b) 944 WRITE_ONCE(b, 2); x = READ_ONCE(b);
963 <read barrier> 945 <read barrier>
964 y = READ_ONCE(a) 946 y = READ_ONCE(a);
965 947
966 Or: 948 Or:
967 949
968 CPU 1 CPU 2 950 CPU 1 CPU 2
969 =============== ================ 951 =============== ===============================
970 a = 1; 952 a = 1;
971 <write barrier> 953 <write barrier>
972 WRITE_ONCE(b, &a); x = READ_ONCE(b) 954 WRITE_ONCE(b, &a); x = READ_ONCE(b);
973 <implicit addres !! 955 <data dependency barrier>
974 y = *x; 956 y = *x;
975 957
976 Or even: 958 Or even:
977 959
978 CPU 1 CPU 2 960 CPU 1 CPU 2
979 =============== ================ 961 =============== ===============================
980 r1 = READ_ONCE(y); 962 r1 = READ_ONCE(y);
981 <general barrier> 963 <general barrier>
982 WRITE_ONCE(x, 1); if (r2 = READ_ON !! 964 WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
983 <implicit con 965 <implicit control dependency>
984 WRITE_ONCE(y, 966 WRITE_ONCE(y, 1);
985 } 967 }
986 968
987 assert(r1 == 0 || r2 == 0); 969 assert(r1 == 0 || r2 == 0);
988 970
989 Basically, the read barrier always has to be t 971 Basically, the read barrier always has to be there, even though it can be of
990 the "weaker" type. 972 the "weaker" type.
991 973
992 [!] Note that the stores before the write barr 974 [!] Note that the stores before the write barrier would normally be expected to
993 match the loads after the read barrier or the !! 975 match the loads after the read barrier or the data dependency barrier, and vice
994 vice versa: !! 976 versa:
995 977
996 CPU 1 CP 978 CPU 1 CPU 2
997 =================== == 979 =================== ===================
998 WRITE_ONCE(a, 1); }---- --->{ v 980 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
999 WRITE_ONCE(b, 2); } \ / { w 981 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
1000 <write barrier> \ < 982 <write barrier> \ <read barrier>
1001 WRITE_ONCE(c, 3); } / \ { x 983 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
1002 WRITE_ONCE(d, 4); }---- --->{ y 984 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
1003 985
1004 986
1005 EXAMPLES OF MEMORY BARRIER SEQUENCES 987 EXAMPLES OF MEMORY BARRIER SEQUENCES
1006 ------------------------------------ 988 ------------------------------------
1007 989
1008 Firstly, write barriers act as partial orderi 990 Firstly, write barriers act as partial orderings on store operations.
1009 Consider the following sequence of events: 991 Consider the following sequence of events:
1010 992
1011 CPU 1 993 CPU 1
1012 ======================= 994 =======================
1013 STORE A = 1 995 STORE A = 1
1014 STORE B = 2 996 STORE B = 2
1015 STORE C = 3 997 STORE C = 3
1016 <write barrier> 998 <write barrier>
1017 STORE D = 4 999 STORE D = 4
1018 STORE E = 5 1000 STORE E = 5
1019 1001
1020 This sequence of events is committed to the m 1002 This sequence of events is committed to the memory coherence system in an order
1021 that the rest of the system might perceive as 1003 that the rest of the system might perceive as the unordered set of { STORE A,
1022 STORE B, STORE C } all occurring before the u 1004 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
1023 }: 1005 }:
1024 1006
1025 +-------+ : : 1007 +-------+ : :
1026 | | +------+ 1008 | | +------+
1027 | |------>| C=3 | } /\ 1009 | |------>| C=3 | } /\
1028 | | : +------+ }----- 1010 | | : +------+ }----- \ -----> Events perceptible to
1029 | | : | A=1 | } 1011 | | : | A=1 | } \/ the rest of the system
1030 | | : +------+ } 1012 | | : +------+ }
1031 | CPU 1 | : | B=2 | } 1013 | CPU 1 | : | B=2 | }
1032 | | +------+ } 1014 | | +------+ }
1033 | | wwwwwwwwwwwwwwww } <--- 1015 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
1034 | | +------+ } 1016 | | +------+ } requires all stores prior to the
1035 | | : | E=5 | } 1017 | | : | E=5 | } barrier to be committed before
1036 | | : +------+ } 1018 | | : +------+ } further stores may take place
1037 | |------>| D=4 | } 1019 | |------>| D=4 | }
1038 | | +------+ 1020 | | +------+
1039 +-------+ : : 1021 +-------+ : :
1040 | 1022 |
1041 | Sequence in whic 1023 | Sequence in which stores are committed to the
1042 | memory system by 1024 | memory system by CPU 1
1043 V 1025 V
1044 1026
1045 1027
1046 Secondly, address-dependency barriers act as !! 1028 Secondly, data dependency barriers act as partial orderings on data-dependent
1047 dependent loads. Consider the following sequ !! 1029 loads. Consider the following sequence of events:
1048 1030
1049 CPU 1 CPU 2 1031 CPU 1 CPU 2
1050 ======================= ============= 1032 ======================= =======================
1051 { B = 7; X = 9; Y = 8; C = &Y 1033 { B = 7; X = 9; Y = 8; C = &Y }
1052 STORE A = 1 1034 STORE A = 1
1053 STORE B = 2 1035 STORE B = 2
1054 <write barrier> 1036 <write barrier>
1055 STORE C = &B LOAD X 1037 STORE C = &B LOAD X
1056 STORE D = 4 LOAD C (gets 1038 STORE D = 4 LOAD C (gets &B)
1057 LOAD *C (read 1039 LOAD *C (reads B)
1058 1040
1059 Without intervention, CPU 2 may perceive the 1041 Without intervention, CPU 2 may perceive the events on CPU 1 in some
1060 effectively random order, despite the write b 1042 effectively random order, despite the write barrier issued by CPU 1:
1061 1043
1062 +-------+ : : 1044 +-------+ : : : :
1063 | | +------+ 1045 | | +------+ +-------+ | Sequence of update
1064 | |------>| B=2 |----- - 1046 | |------>| B=2 |----- --->| Y->8 | | of perception on
1065 | | : +------+ \ 1047 | | : +------+ \ +-------+ | CPU 2
1066 | CPU 1 | : | A=1 | \ - 1048 | CPU 1 | : | A=1 | \ --->| C->&Y | V
1067 | | +------+ | 1049 | | +------+ | +-------+
1068 | | wwwwwwwwwwwwwwww | 1050 | | wwwwwwwwwwwwwwww | : :
1069 | | +------+ | 1051 | | +------+ | : :
1070 | | : | C=&B |--- | 1052 | | : | C=&B |--- | : : +-------+
1071 | | : +------+ \ | 1053 | | : +------+ \ | +-------+ | |
1072 | |------>| D=4 | --------- 1054 | |------>| D=4 | ----------->| C->&B |------>| |
1073 | | +------+ | 1055 | | +------+ | +-------+ | |
1074 +-------+ : : | 1056 +-------+ : : | : : | |
1075 | 1057 | : : | |
1076 | 1058 | : : | CPU 2 |
1077 | 1059 | +-------+ | |
1078 Apparently incorrect ---> | 1060 Apparently incorrect ---> | | B->7 |------>| |
1079 perception of B (!) | 1061 perception of B (!) | +-------+ | |
1080 | 1062 | : : | |
1081 | 1063 | +-------+ | |
1082 The load of X holds ---> \ 1064 The load of X holds ---> \ | X->9 |------>| |
1083 up the maintenance \ 1065 up the maintenance \ +-------+ | |
1084 of coherence of B --- 1066 of coherence of B ----->| B->2 | +-------+
1085 1067 +-------+
1086 1068 : :
1087 1069
1088 1070
1089 In the above example, CPU 2 perceives that B 1071 In the above example, CPU 2 perceives that B is 7, despite the load of *C
1090 (which would be B) coming after the LOAD of C 1072 (which would be B) coming after the LOAD of C.
1091 1073
1092 If, however, an address-dependency barrier we !! 1074 If, however, a data dependency barrier were to be placed between the load of C
1093 of C and the load of *C (ie: B) on CPU 2: !! 1075 and the load of *C (ie: B) on CPU 2:
1094 1076
1095 CPU 1 CPU 2 1077 CPU 1 CPU 2
1096 ======================= ============= 1078 ======================= =======================
1097 { B = 7; X = 9; Y = 8; C = &Y 1079 { B = 7; X = 9; Y = 8; C = &Y }
1098 STORE A = 1 1080 STORE A = 1
1099 STORE B = 2 1081 STORE B = 2
1100 <write barrier> 1082 <write barrier>
1101 STORE C = &B LOAD X 1083 STORE C = &B LOAD X
1102 STORE D = 4 LOAD C (gets 1084 STORE D = 4 LOAD C (gets &B)
1103 <address-depe !! 1085 <data dependency barrier>
1104 LOAD *C (read 1086 LOAD *C (reads B)
1105 1087
1106 then the following will occur: 1088 then the following will occur:
1107 1089
1108 +-------+ : : 1090 +-------+ : : : :
1109 | | +------+ 1091 | | +------+ +-------+
1110 | |------>| B=2 |----- - 1092 | |------>| B=2 |----- --->| Y->8 |
1111 | | : +------+ \ 1093 | | : +------+ \ +-------+
1112 | CPU 1 | : | A=1 | \ - 1094 | CPU 1 | : | A=1 | \ --->| C->&Y |
1113 | | +------+ | 1095 | | +------+ | +-------+
1114 | | wwwwwwwwwwwwwwww | 1096 | | wwwwwwwwwwwwwwww | : :
1115 | | +------+ | 1097 | | +------+ | : :
1116 | | : | C=&B |--- | 1098 | | : | C=&B |--- | : : +-------+
1117 | | : +------+ \ | 1099 | | : +------+ \ | +-------+ | |
1118 | |------>| D=4 | --------- 1100 | |------>| D=4 | ----------->| C->&B |------>| |
1119 | | +------+ | 1101 | | +------+ | +-------+ | |
1120 +-------+ : : | 1102 +-------+ : : | : : | |
1121 | 1103 | : : | |
1122 | 1104 | : : | CPU 2 |
1123 | 1105 | +-------+ | |
1124 | 1106 | | X->9 |------>| |
1125 | 1107 | +-------+ | |
1126 Makes sure all effects ---> \ a !! 1108 Makes sure all effects ---> \ ddddddddddddddddd | |
1127 prior to the store of C \ 1109 prior to the store of C \ +-------+ | |
1128 are perceptible to --- 1110 are perceptible to ----->| B->2 |------>| |
1129 subsequent loads 1111 subsequent loads +-------+ | |
1130 1112 : : +-------+
1131 1113
1132 1114
1133 And thirdly, a read barrier acts as a partial 1115 And thirdly, a read barrier acts as a partial order on loads. Consider the
1134 following sequence of events: 1116 following sequence of events:
1135 1117
1136 CPU 1 CPU 2 1118 CPU 1 CPU 2
1137 ======================= ============= 1119 ======================= =======================
1138 { A = 0, B = 9 } 1120 { A = 0, B = 9 }
1139 STORE A=1 1121 STORE A=1
1140 <write barrier> 1122 <write barrier>
1141 STORE B=2 1123 STORE B=2
1142 LOAD B 1124 LOAD B
1143 LOAD A 1125 LOAD A
1144 1126
1145 Without intervention, CPU 2 may then choose t 1127 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1146 some effectively random order, despite the wr 1128 some effectively random order, despite the write barrier issued by CPU 1:
1147 1129
1148 +-------+ : : 1130 +-------+ : : : :
1149 | | +------+ 1131 | | +------+ +-------+
1150 | |------>| A=1 |------ - 1132 | |------>| A=1 |------ --->| A->0 |
1151 | | +------+ \ 1133 | | +------+ \ +-------+
1152 | CPU 1 | wwwwwwwwwwwwwwww \ - 1134 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1153 | | +------+ | 1135 | | +------+ | +-------+
1154 | |------>| B=2 |--- | 1136 | |------>| B=2 |--- | : :
1155 | | +------+ \ | 1137 | | +------+ \ | : : +-------+
1156 +-------+ : : \ | 1138 +-------+ : : \ | +-------+ | |
1157 -------- 1139 ---------->| B->2 |------>| |
1158 | 1140 | +-------+ | CPU 2 |
1159 | 1141 | | A->0 |------>| |
1160 | 1142 | +-------+ | |
1161 | 1143 | : : +-------+
1162 \ 1144 \ : :
1163 \ 1145 \ +-------+
1164 -- 1146 ---->| A->1 |
1165 1147 +-------+
1166 1148 : :
1167 1149
1168 1150
1169 If, however, a read barrier were to be placed 1151 If, however, a read barrier were to be placed between the load of B and the
1170 load of A on CPU 2: 1152 load of A on CPU 2:
1171 1153
1172 CPU 1 CPU 2 1154 CPU 1 CPU 2
1173 ======================= ============= 1155 ======================= =======================
1174 { A = 0, B = 9 } 1156 { A = 0, B = 9 }
1175 STORE A=1 1157 STORE A=1
1176 <write barrier> 1158 <write barrier>
1177 STORE B=2 1159 STORE B=2
1178 LOAD B 1160 LOAD B
1179 <read barrier 1161 <read barrier>
1180 LOAD A 1162 LOAD A
1181 1163
1182 then the partial ordering imposed by CPU 1 wi 1164 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1183 2: 1165 2:
1184 1166
1185 +-------+ : : 1167 +-------+ : : : :
1186 | | +------+ 1168 | | +------+ +-------+
1187 | |------>| A=1 |------ - 1169 | |------>| A=1 |------ --->| A->0 |
1188 | | +------+ \ 1170 | | +------+ \ +-------+
1189 | CPU 1 | wwwwwwwwwwwwwwww \ - 1171 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1190 | | +------+ | 1172 | | +------+ | +-------+
1191 | |------>| B=2 |--- | 1173 | |------>| B=2 |--- | : :
1192 | | +------+ \ | 1174 | | +------+ \ | : : +-------+
1193 +-------+ : : \ | 1175 +-------+ : : \ | +-------+ | |
1194 -------- 1176 ---------->| B->2 |------>| |
1195 | 1177 | +-------+ | CPU 2 |
1196 | 1178 | : : | |
1197 | 1179 | : : | |
1198 At this point the read ----> \ r 1180 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1199 barrier causes all effects \ 1181 barrier causes all effects \ +-------+ | |
1200 prior to the storage of B -- 1182 prior to the storage of B ---->| A->1 |------>| |
1201 to be perceptible to CPU 2 1183 to be perceptible to CPU 2 +-------+ | |
1202 1184 : : +-------+
1203 1185
1204 1186
1205 To illustrate this more completely, consider 1187 To illustrate this more completely, consider what could happen if the code
1206 contained a load of A either side of the read 1188 contained a load of A either side of the read barrier:
1207 1189
1208 CPU 1 CPU 2 1190 CPU 1 CPU 2
1209 ======================= ============= 1191 ======================= =======================
1210 { A = 0, B = 9 } 1192 { A = 0, B = 9 }
1211 STORE A=1 1193 STORE A=1
1212 <write barrier> 1194 <write barrier>
1213 STORE B=2 1195 STORE B=2
1214 LOAD B 1196 LOAD B
1215 LOAD A [first 1197 LOAD A [first load of A]
1216 <read barrier 1198 <read barrier>
1217 LOAD A [secon 1199 LOAD A [second load of A]
1218 1200
1219 Even though the two loads of A both occur aft 1201 Even though the two loads of A both occur after the load of B, they may both
1220 come up with different values: 1202 come up with different values:
1221 1203
1222 +-------+ : : 1204 +-------+ : : : :
1223 | | +------+ 1205 | | +------+ +-------+
1224 | |------>| A=1 |------ - 1206 | |------>| A=1 |------ --->| A->0 |
1225 | | +------+ \ 1207 | | +------+ \ +-------+
1226 | CPU 1 | wwwwwwwwwwwwwwww \ - 1208 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1227 | | +------+ | 1209 | | +------+ | +-------+
1228 | |------>| B=2 |--- | 1210 | |------>| B=2 |--- | : :
1229 | | +------+ \ | 1211 | | +------+ \ | : : +-------+
1230 +-------+ : : \ | 1212 +-------+ : : \ | +-------+ | |
1231 -------- 1213 ---------->| B->2 |------>| |
1232 | 1214 | +-------+ | CPU 2 |
1233 | 1215 | : : | |
1234 | 1216 | : : | |
1235 | 1217 | +-------+ | |
1236 | 1218 | | A->0 |------>| 1st |
1237 | 1219 | +-------+ | |
1238 At this point the read ----> \ r 1220 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1239 barrier causes all effects \ 1221 barrier causes all effects \ +-------+ | |
1240 prior to the storage of B -- 1222 prior to the storage of B ---->| A->1 |------>| 2nd |
1241 to be perceptible to CPU 2 1223 to be perceptible to CPU 2 +-------+ | |
1242 1224 : : +-------+
1243 1225
1244 1226
1245 But it may be that the update to A from CPU 1 1227 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1246 before the read barrier completes anyway: 1228 before the read barrier completes anyway:
1247 1229
1248 +-------+ : : 1230 +-------+ : : : :
1249 | | +------+ 1231 | | +------+ +-------+
1250 | |------>| A=1 |------ - 1232 | |------>| A=1 |------ --->| A->0 |
1251 | | +------+ \ 1233 | | +------+ \ +-------+
1252 | CPU 1 | wwwwwwwwwwwwwwww \ - 1234 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1253 | | +------+ | 1235 | | +------+ | +-------+
1254 | |------>| B=2 |--- | 1236 | |------>| B=2 |--- | : :
1255 | | +------+ \ | 1237 | | +------+ \ | : : +-------+
1256 +-------+ : : \ | 1238 +-------+ : : \ | +-------+ | |
1257 -------- 1239 ---------->| B->2 |------>| |
1258 | 1240 | +-------+ | CPU 2 |
1259 | 1241 | : : | |
1260 \ 1242 \ : : | |
1261 \ 1243 \ +-------+ | |
1262 -- 1244 ---->| A->1 |------>| 1st |
1263 1245 +-------+ | |
1264 r 1246 rrrrrrrrrrrrrrrrr | |
1265 1247 +-------+ | |
1266 1248 | A->1 |------>| 2nd |
1267 1249 +-------+ | |
1268 1250 : : +-------+
1269 1251
1270 1252
1271 The guarantee is that the second load will al 1253 The guarantee is that the second load will always come up with A == 1 if the
1272 load of B came up with B == 2. No such guara 1254 load of B came up with B == 2. No such guarantee exists for the first load of
1273 A; that may come up with either A == 0 or A = 1255 A; that may come up with either A == 0 or A == 1.
1274 1256
1275 1257
1276 READ MEMORY BARRIERS VS LOAD SPECULATION 1258 READ MEMORY BARRIERS VS LOAD SPECULATION
1277 ---------------------------------------- 1259 ----------------------------------------
1278 1260
1279 Many CPUs speculate with loads: that is they 1261 Many CPUs speculate with loads: that is they see that they will need to load an
1280 item from memory, and they find a time where 1262 item from memory, and they find a time where they're not using the bus for any
1281 other loads, and so do the load in advance - 1263 other loads, and so do the load in advance - even though they haven't actually
1282 got to that point in the instruction executio 1264 got to that point in the instruction execution flow yet. This permits the
1283 actual load instruction to potentially comple 1265 actual load instruction to potentially complete immediately because the CPU
1284 already has the value to hand. 1266 already has the value to hand.
1285 1267
1286 It may turn out that the CPU didn't actually 1268 It may turn out that the CPU didn't actually need the value - perhaps because a
1287 branch circumvented the load - in which case 1269 branch circumvented the load - in which case it can discard the value or just
1288 cache it for later use. 1270 cache it for later use.
1289 1271
1290 Consider: 1272 Consider:
1291 1273
1292 CPU 1 CPU 2 1274 CPU 1 CPU 2
1293 ======================= ============= 1275 ======================= =======================
1294 LOAD B 1276 LOAD B
1295 DIVIDE 1277 DIVIDE } Divide instructions generally
1296 DIVIDE 1278 DIVIDE } take a long time to perform
1297 LOAD A 1279 LOAD A
1298 1280
1299 Which might appear as this: 1281 Which might appear as this:
1300 1282
1301 1283 : : +-------+
1302 1284 +-------+ | |
1303 - 1285 --->| B->2 |------>| |
1304 1286 +-------+ | CPU 2 |
1305 1287 : :DIVIDE | |
1306 1288 +-------+ | |
1307 The CPU being busy doing a ---> - 1289 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1308 division speculates on the 1290 division speculates on the +-------+ ~ | |
1309 LOAD of A 1291 LOAD of A : : ~ | |
1310 1292 : :DIVIDE | |
1311 1293 : : ~ | |
1312 Once the divisions are complete --> 1294 Once the divisions are complete --> : : ~-->| |
1313 the CPU can then perform the 1295 the CPU can then perform the : : | |
1314 LOAD with immediate effect 1296 LOAD with immediate effect : : +-------+
1315 1297
1316 1298
1317 Placing a read barrier or an address-dependen !! 1299 Placing a read barrier or a data dependency barrier just before the second
1318 load: 1300 load:
1319 1301
1320 CPU 1 CPU 2 1302 CPU 1 CPU 2
1321 ======================= ============= 1303 ======================= =======================
1322 LOAD B 1304 LOAD B
1323 DIVIDE 1305 DIVIDE
1324 DIVIDE 1306 DIVIDE
1325 <read barrier 1307 <read barrier>
1326 LOAD A 1308 LOAD A
1327 1309
1328 will force any value speculatively obtained t 1310 will force any value speculatively obtained to be reconsidered to an extent
1329 dependent on the type of barrier used. If th 1311 dependent on the type of barrier used. If there was no change made to the
1330 speculated memory location, then the speculat 1312 speculated memory location, then the speculated value will just be used:
1331 1313
1332 1314 : : +-------+
1333 1315 +-------+ | |
1334 - 1316 --->| B->2 |------>| |
1335 1317 +-------+ | CPU 2 |
1336 1318 : :DIVIDE | |
1337 1319 +-------+ | |
1338 The CPU being busy doing a ---> - 1320 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1339 division speculates on the 1321 division speculates on the +-------+ ~ | |
1340 LOAD of A 1322 LOAD of A : : ~ | |
1341 1323 : :DIVIDE | |
1342 1324 : : ~ | |
1343 1325 : : ~ | |
1344 r 1326 rrrrrrrrrrrrrrrr~ | |
1345 1327 : : ~ | |
1346 1328 : : ~-->| |
1347 1329 : : | |
1348 1330 : : +-------+
1349 1331
1350 1332
1351 but if there was an update or an invalidation 1333 but if there was an update or an invalidation from another CPU pending, then
1352 the speculation will be cancelled and the val 1334 the speculation will be cancelled and the value reloaded:
1353 1335
1354 1336 : : +-------+
1355 1337 +-------+ | |
1356 - 1338 --->| B->2 |------>| |
1357 1339 +-------+ | CPU 2 |
1358 1340 : :DIVIDE | |
1359 1341 +-------+ | |
1360 The CPU being busy doing a ---> - 1342 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1361 division speculates on the 1343 division speculates on the +-------+ ~ | |
1362 LOAD of A 1344 LOAD of A : : ~ | |
1363 1345 : :DIVIDE | |
1364 1346 : : ~ | |
1365 1347 : : ~ | |
1366 r 1348 rrrrrrrrrrrrrrrrr | |
1367 1349 +-------+ | |
1368 The speculation is discarded ---> - 1350 The speculation is discarded ---> --->| A->1 |------>| |
1369 and an updated value is 1351 and an updated value is +-------+ | |
1370 retrieved 1352 retrieved : : +-------+
1371 1353
1372 1354
1373 MULTICOPY ATOMICITY !! 1355 TRANSITIVITY
1374 -------------------- !! 1356 ------------
1375 <<
1376 Multicopy atomicity is a deeply intuitive not <<
1377 not always provided by real computer systems, <<
1378 becomes visible at the same time to all CPUs, <<
1379 CPUs agree on the order in which all stores b <<
1380 support of full multicopy atomicity would rul <<
1381 optimizations, so a weaker form called ``othe <<
1382 instead guarantees only that a given store be <<
1383 time to all -other- CPUs. The remainder of t <<
1384 weaker form, but for brevity will call it sim <<
1385 1357
1386 The following example demonstrates multicopy !! 1358 Transitivity is a deeply intuitive notion about ordering that is not
>> 1359 always provided by real computer systems. The following example
>> 1360 demonstrates transitivity:
1387 1361
1388 CPU 1 CPU 2 1362 CPU 1 CPU 2 CPU 3
1389 ======================= ============= 1363 ======================= ======================= =======================
1390 { X = 0, Y = 0 } 1364 { X = 0, Y = 0 }
1391 STORE X=1 r1=LOAD X (re !! 1365 STORE X=1 LOAD X STORE Y=1
1392 <general barr !! 1366 <general barrier> <general barrier>
1393 STORE Y=r1 !! 1367 LOAD Y LOAD X
1394 !! 1368
1395 Suppose that CPU 2's load from X returns 1, w !! 1369 Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1396 and CPU 3's load from Y returns 1. This indi !! 1370 This indicates that CPU 2's load from X in some sense follows CPU 1's
1397 to X precedes CPU 2's load from X and that CP !! 1371 store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1398 CPU 3's load from Y. In addition, the memory !! 1372 store to Y. The question is then "Can CPU 3's load from X return 0?"
1399 CPU 2 executes its load before its store, and <<
1400 it loads from X. The question is then "Can C <<
1401 1373
1402 Because CPU 3's load from X in some sense com !! 1374 Because CPU 2's load from X in some sense came after CPU 1's store, it
1403 is natural to expect that CPU 3's load from X 1375 is natural to expect that CPU 3's load from X must therefore return 1.
1404 This expectation follows from multicopy atomi !! 1376 This expectation is an example of transitivity: if a load executing on
1405 on CPU B follows a load from the same variabl !! 1377 CPU A follows a load from the same variable executing on CPU B, then
1406 CPU A did not originally store the value whic !! 1378 CPU A's load must either return the same value that CPU B's load did,
1407 multicopy-atomic systems, CPU B's load must r !! 1379 or must return some later value.
1408 that CPU A's load did or some later value. H !! 1380
1409 does not require systems to be multicopy atom !! 1381 In the Linux kernel, use of general memory barriers guarantees
1410 !! 1382 transitivity. Therefore, in the above example, if CPU 2's load from X
1411 The use of a general memory barrier in the ex !! 1383 returns 1 and its load from Y returns 0, then CPU 3's load from X must
1412 for any lack of multicopy atomicity. In the !! 1384 also return 1.
1413 from X returns 1 and CPU 3's load from Y retu !! 1385
1414 from X must indeed also return 1. !! 1386 However, transitivity is -not- guaranteed for read or write barriers.
1415 !! 1387 For example, suppose that CPU 2's general barrier in the above example
1416 However, dependencies, read barriers, and wri !! 1388 is changed to a read barrier as shown below:
1417 able to compensate for non-multicopy atomicit <<
1418 that CPU 2's general barrier is removed from <<
1419 only the data dependency shown below: <<
1420 1389
1421 CPU 1 CPU 2 1390 CPU 1 CPU 2 CPU 3
1422 ======================= ============= 1391 ======================= ======================= =======================
1423 { X = 0, Y = 0 } 1392 { X = 0, Y = 0 }
1424 STORE X=1 r1=LOAD X (re !! 1393 STORE X=1 LOAD X STORE Y=1
1425 <data depende !! 1394 <read barrier> <general barrier>
1426 STORE Y=r1 !! 1395 LOAD Y LOAD X
1427 !! 1396
1428 This substitution allows non-multicopy atomic !! 1397 This substitution destroys transitivity: in this example, it is perfectly
1429 this example, it is perfectly legal for CPU 2 !! 1398 legal for CPU 2's load from X to return 1, its load from Y to return 0,
1430 CPU 3's load from Y to return 1, and its load !! 1399 and CPU 3's load from X to return 0.
1431 !! 1400
1432 The key point is that although CPU 2's data d !! 1401 The key point is that although CPU 2's read barrier orders its pair
1433 and store, it does not guarantee to order CPU !! 1402 of loads, it does not guarantee to order CPU 1's store. Therefore, if
1434 example runs on a non-multicopy-atomic system !! 1403 this example runs on a system where CPUs 1 and 2 share a store buffer
1435 store buffer or a level of cache, CPU 2 might !! 1404 or a level of cache, CPU 2 might have early access to CPU 1's writes.
1436 writes. General barriers are therefore requi !! 1405 General barriers are therefore required to ensure that all CPUs agree
1437 agree on the combined order of multiple acces !! 1406 on the combined order of CPU 1's and CPU 2's accesses.
1438 !! 1407
1439 General barriers can compensate not only for !! 1408 General barriers provide "global transitivity", so that all CPUs will
1440 but can also generate additional ordering tha !! 1409 agree on the order of operations. In contrast, a chain of release-acquire
1441 CPUs will perceive the same order of -all- op !! 1410 pairs provides only "local transitivity", so that only those CPUs on
1442 chain of release-acquire pairs do not provide !! 1411 the chain are guaranteed to agree on the combined order of the accesses.
1443 which means that only those CPUs on the chain !! 1412 For example, switching to C code in deference to Herman Hollerith:
1444 on the combined order of the accesses. For e <<
1445 in deference to the ghost of Herman Hollerith <<
1446 1413
1447 int u, v, x, y, z; 1414 int u, v, x, y, z;
1448 1415
1449 void cpu0(void) 1416 void cpu0(void)
1450 { 1417 {
1451 r0 = smp_load_acquire(&x); 1418 r0 = smp_load_acquire(&x);
1452 WRITE_ONCE(u, 1); 1419 WRITE_ONCE(u, 1);
1453 smp_store_release(&y, 1); 1420 smp_store_release(&y, 1);
1454 } 1421 }
1455 1422
1456 void cpu1(void) 1423 void cpu1(void)
1457 { 1424 {
1458 r1 = smp_load_acquire(&y); 1425 r1 = smp_load_acquire(&y);
1459 r4 = READ_ONCE(v); 1426 r4 = READ_ONCE(v);
1460 r5 = READ_ONCE(u); 1427 r5 = READ_ONCE(u);
1461 smp_store_release(&z, 1); 1428 smp_store_release(&z, 1);
1462 } 1429 }
1463 1430
1464 void cpu2(void) 1431 void cpu2(void)
1465 { 1432 {
1466 r2 = smp_load_acquire(&z); 1433 r2 = smp_load_acquire(&z);
1467 smp_store_release(&x, 1); 1434 smp_store_release(&x, 1);
1468 } 1435 }
1469 1436
1470 void cpu3(void) 1437 void cpu3(void)
1471 { 1438 {
1472 WRITE_ONCE(v, 1); 1439 WRITE_ONCE(v, 1);
1473 smp_mb(); 1440 smp_mb();
1474 r3 = READ_ONCE(u); 1441 r3 = READ_ONCE(u);
1475 } 1442 }
1476 1443
1477 Because cpu0(), cpu1(), and cpu2() participat !! 1444 Because cpu0(), cpu1(), and cpu2() participate in a local transitive
1478 smp_store_release()/smp_load_acquire() pairs, !! 1445 chain of smp_store_release()/smp_load_acquire() pairs, the following
1479 is prohibited: !! 1446 outcome is prohibited:
1480 1447
1481 r0 == 1 && r1 == 1 && r2 == 1 1448 r0 == 1 && r1 == 1 && r2 == 1
1482 1449
1483 Furthermore, because of the release-acquire r 1450 Furthermore, because of the release-acquire relationship between cpu0()
1484 and cpu1(), cpu1() must see cpu0()'s writes, 1451 and cpu1(), cpu1() must see cpu0()'s writes, so that the following
1485 outcome is prohibited: 1452 outcome is prohibited:
1486 1453
1487 r1 == 1 && r5 == 0 1454 r1 == 1 && r5 == 0
1488 1455
1489 However, the ordering provided by a release-a !! 1456 However, the transitivity of release-acquire is local to the participating
1490 to the CPUs participating in that chain and d !! 1457 CPUs and does not apply to cpu3(). Therefore, the following outcome
1491 at least aside from stores. Therefore, the f !! 1458 is possible:
1492 1459
1493 r0 == 0 && r1 == 1 && r2 == 1 && r3 = 1460 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
1494 1461
1495 As an aside, the following outcome is also po 1462 As an aside, the following outcome is also possible:
1496 1463
1497 r0 == 0 && r1 == 1 && r2 == 1 && r3 = 1464 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
1498 1465
1499 Although cpu0(), cpu1(), and cpu2() will see 1466 Although cpu0(), cpu1(), and cpu2() will see their respective reads and
1500 writes in order, CPUs not involved in the rel 1467 writes in order, CPUs not involved in the release-acquire chain might
1501 well disagree on the order. This disagreemen 1468 well disagree on the order. This disagreement stems from the fact that
1502 the weak memory-barrier instructions used to 1469 the weak memory-barrier instructions used to implement smp_load_acquire()
1503 and smp_store_release() are not required to o 1470 and smp_store_release() are not required to order prior stores against
1504 subsequent loads in all cases. This means th 1471 subsequent loads in all cases. This means that cpu3() can see cpu0()'s
1505 store to u as happening -after- cpu1()'s load 1472 store to u as happening -after- cpu1()'s load from v, even though
1506 both cpu0() and cpu1() agree that these two o 1473 both cpu0() and cpu1() agree that these two operations occurred in the
1507 intended order. 1474 intended order.
1508 1475
1509 However, please keep in mind that smp_load_ac 1476 However, please keep in mind that smp_load_acquire() is not magic.
1510 In particular, it simply reads from its argum 1477 In particular, it simply reads from its argument with ordering. It does
1511 -not- ensure that any particular value will b 1478 -not- ensure that any particular value will be read. Therefore, the
1512 following outcome is possible: 1479 following outcome is possible:
1513 1480
1514 r0 == 0 && r1 == 0 && r2 == 0 && r5 = 1481 r0 == 0 && r1 == 0 && r2 == 0 && r5 == 0
1515 1482
1516 Note that this outcome can happen even on a m 1483 Note that this outcome can happen even on a mythical sequentially
1517 consistent system where nothing is ever reord 1484 consistent system where nothing is ever reordered.
1518 1485
1519 To reiterate, if your code requires full orde !! 1486 To reiterate, if your code requires global transitivity, use general
1520 use general barriers throughout. !! 1487 barriers throughout.
1521 1488
1522 1489
1523 ======================== 1490 ========================
1524 EXPLICIT KERNEL BARRIERS 1491 EXPLICIT KERNEL BARRIERS
1525 ======================== 1492 ========================
1526 1493
1527 The Linux kernel has a variety of different b 1494 The Linux kernel has a variety of different barriers that act at different
1528 levels: 1495 levels:
1529 1496
1530 (*) Compiler barrier. 1497 (*) Compiler barrier.
1531 1498
1532 (*) CPU memory barriers. 1499 (*) CPU memory barriers.
1533 1500
>> 1501 (*) MMIO write barrier.
>> 1502
1534 1503
1535 COMPILER BARRIER 1504 COMPILER BARRIER
1536 ---------------- 1505 ----------------
1537 1506
1538 The Linux kernel has an explicit compiler bar 1507 The Linux kernel has an explicit compiler barrier function that prevents the
1539 compiler from moving the memory accesses eith 1508 compiler from moving the memory accesses either side of it to the other side:
1540 1509
1541 barrier(); 1510 barrier();
1542 1511
1543 This is a general barrier -- there are no rea 1512 This is a general barrier -- there are no read-read or write-write
1544 variants of barrier(). However, READ_ONCE() 1513 variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1545 thought of as weak forms of barrier() that af 1514 thought of as weak forms of barrier() that affect only the specific
1546 accesses flagged by the READ_ONCE() or WRITE_ 1515 accesses flagged by the READ_ONCE() or WRITE_ONCE().
1547 1516
1548 The barrier() function has the following effe 1517 The barrier() function has the following effects:
1549 1518
1550 (*) Prevents the compiler from reordering ac 1519 (*) Prevents the compiler from reordering accesses following the
1551 barrier() to precede any accesses preced 1520 barrier() to precede any accesses preceding the barrier().
1552 One example use for this property is to 1521 One example use for this property is to ease communication between
1553 interrupt-handler code and the code that 1522 interrupt-handler code and the code that was interrupted.
1554 1523
1555 (*) Within a loop, forces the compiler to lo 1524 (*) Within a loop, forces the compiler to load the variables used
1556 in that loop's conditional on each pass 1525 in that loop's conditional on each pass through that loop.
1557 1526
1558 The READ_ONCE() and WRITE_ONCE() functions ca 1527 The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1559 optimizations that, while perfectly safe in s 1528 optimizations that, while perfectly safe in single-threaded code, can
1560 be fatal in concurrent code. Here are some e 1529 be fatal in concurrent code. Here are some examples of these sorts
1561 of optimizations: 1530 of optimizations:
1562 1531
1563 (*) The compiler is within its rights to reo 1532 (*) The compiler is within its rights to reorder loads and stores
1564 to the same variable, and in some cases, 1533 to the same variable, and in some cases, the CPU is within its
1565 rights to reorder loads to the same vari 1534 rights to reorder loads to the same variable. This means that
1566 the following code: 1535 the following code:
1567 1536
1568 a[0] = x; 1537 a[0] = x;
1569 a[1] = x; 1538 a[1] = x;
1570 1539
1571 Might result in an older value of x stor 1540 Might result in an older value of x stored in a[1] than in a[0].
1572 Prevent both the compiler and the CPU fr 1541 Prevent both the compiler and the CPU from doing this as follows:
1573 1542
1574 a[0] = READ_ONCE(x); 1543 a[0] = READ_ONCE(x);
1575 a[1] = READ_ONCE(x); 1544 a[1] = READ_ONCE(x);
1576 1545
1577 In short, READ_ONCE() and WRITE_ONCE() p 1546 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1578 accesses from multiple CPUs to a single 1547 accesses from multiple CPUs to a single variable.
1579 1548
1580 (*) The compiler is within its rights to mer 1549 (*) The compiler is within its rights to merge successive loads from
1581 the same variable. Such merging can cau 1550 the same variable. Such merging can cause the compiler to "optimize"
1582 the following code: 1551 the following code:
1583 1552
1584 while (tmp = a) 1553 while (tmp = a)
1585 do_something_with(tmp); 1554 do_something_with(tmp);
1586 1555
1587 into the following code, which, although 1556 into the following code, which, although in some sense legitimate
1588 for single-threaded code, is almost cert 1557 for single-threaded code, is almost certainly not what the developer
1589 intended: 1558 intended:
1590 1559
1591 if (tmp = a) 1560 if (tmp = a)
1592 for (;;) 1561 for (;;)
1593 do_something_with(tmp 1562 do_something_with(tmp);
1594 1563
1595 Use READ_ONCE() to prevent the compiler 1564 Use READ_ONCE() to prevent the compiler from doing this to you:
1596 1565
1597 while (tmp = READ_ONCE(a)) 1566 while (tmp = READ_ONCE(a))
1598 do_something_with(tmp); 1567 do_something_with(tmp);
1599 1568
1600 (*) The compiler is within its rights to rel 1569 (*) The compiler is within its rights to reload a variable, for example,
1601 in cases where high register pressure pr 1570 in cases where high register pressure prevents the compiler from
1602 keeping all data of interest in register 1571 keeping all data of interest in registers. The compiler might
1603 therefore optimize the variable 'tmp' ou 1572 therefore optimize the variable 'tmp' out of our previous example:
1604 1573
1605 while (tmp = a) 1574 while (tmp = a)
1606 do_something_with(tmp); 1575 do_something_with(tmp);
1607 1576
1608 This could result in the following code, 1577 This could result in the following code, which is perfectly safe in
1609 single-threaded code, but can be fatal i 1578 single-threaded code, but can be fatal in concurrent code:
1610 1579
1611 while (a) 1580 while (a)
1612 do_something_with(a); 1581 do_something_with(a);
1613 1582
1614 For example, the optimized version of th 1583 For example, the optimized version of this code could result in
1615 passing a zero to do_something_with() in 1584 passing a zero to do_something_with() in the case where the variable
1616 a was modified by some other CPU between 1585 a was modified by some other CPU between the "while" statement and
1617 the call to do_something_with(). 1586 the call to do_something_with().
1618 1587
1619 Again, use READ_ONCE() to prevent the co 1588 Again, use READ_ONCE() to prevent the compiler from doing this:
1620 1589
1621 while (tmp = READ_ONCE(a)) 1590 while (tmp = READ_ONCE(a))
1622 do_something_with(tmp); 1591 do_something_with(tmp);
1623 1592
1624 Note that if the compiler runs short of 1593 Note that if the compiler runs short of registers, it might save
1625 tmp onto the stack. The overhead of thi 1594 tmp onto the stack. The overhead of this saving and later restoring
1626 is why compilers reload variables. Doin 1595 is why compilers reload variables. Doing so is perfectly safe for
1627 single-threaded code, so you need to tel 1596 single-threaded code, so you need to tell the compiler about cases
1628 where it is not safe. 1597 where it is not safe.
1629 1598
1630 (*) The compiler is within its rights to omi 1599 (*) The compiler is within its rights to omit a load entirely if it knows
1631 what the value will be. For example, if 1600 what the value will be. For example, if the compiler can prove that
1632 the value of variable 'a' is always zero 1601 the value of variable 'a' is always zero, it can optimize this code:
1633 1602
1634 while (tmp = a) 1603 while (tmp = a)
1635 do_something_with(tmp); 1604 do_something_with(tmp);
1636 1605
1637 Into this: 1606 Into this:
1638 1607
1639 do { } while (0); 1608 do { } while (0);
1640 1609
1641 This transformation is a win for single- 1610 This transformation is a win for single-threaded code because it
1642 gets rid of a load and a branch. The pr 1611 gets rid of a load and a branch. The problem is that the compiler
1643 will carry out its proof assuming that t 1612 will carry out its proof assuming that the current CPU is the only
1644 one updating variable 'a'. If variable 1613 one updating variable 'a'. If variable 'a' is shared, then the
1645 compiler's proof will be erroneous. Use 1614 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1646 compiler that it doesn't know as much as 1615 compiler that it doesn't know as much as it thinks it does:
1647 1616
1648 while (tmp = READ_ONCE(a)) 1617 while (tmp = READ_ONCE(a))
1649 do_something_with(tmp); 1618 do_something_with(tmp);
1650 1619
1651 But please note that the compiler is als 1620 But please note that the compiler is also closely watching what you
1652 do with the value after the READ_ONCE(). 1621 do with the value after the READ_ONCE(). For example, suppose you
1653 do the following and MAX is a preprocess 1622 do the following and MAX is a preprocessor macro with the value 1:
1654 1623
1655 while ((tmp = READ_ONCE(a)) % MAX) 1624 while ((tmp = READ_ONCE(a)) % MAX)
1656 do_something_with(tmp); 1625 do_something_with(tmp);
1657 1626
1658 Then the compiler knows that the result 1627 Then the compiler knows that the result of the "%" operator applied
1659 to MAX will always be zero, again allowi 1628 to MAX will always be zero, again allowing the compiler to optimize
1660 the code into near-nonexistence. (It wi 1629 the code into near-nonexistence. (It will still load from the
1661 variable 'a'.) 1630 variable 'a'.)
1662 1631
1663 (*) Similarly, the compiler is within its ri 1632 (*) Similarly, the compiler is within its rights to omit a store entirely
1664 if it knows that the variable already ha 1633 if it knows that the variable already has the value being stored.
1665 Again, the compiler assumes that the cur 1634 Again, the compiler assumes that the current CPU is the only one
1666 storing into the variable, which can cau 1635 storing into the variable, which can cause the compiler to do the
1667 wrong thing for shared variables. For e 1636 wrong thing for shared variables. For example, suppose you have
1668 the following: 1637 the following:
1669 1638
1670 a = 0; 1639 a = 0;
1671 ... Code that does not store to varia 1640 ... Code that does not store to variable a ...
1672 a = 0; 1641 a = 0;
1673 1642
1674 The compiler sees that the value of vari 1643 The compiler sees that the value of variable 'a' is already zero, so
1675 it might well omit the second store. Th 1644 it might well omit the second store. This would come as a fatal
1676 surprise if some other CPU might have st 1645 surprise if some other CPU might have stored to variable 'a' in the
1677 meantime. 1646 meantime.
1678 1647
1679 Use WRITE_ONCE() to prevent the compiler 1648 Use WRITE_ONCE() to prevent the compiler from making this sort of
1680 wrong guess: 1649 wrong guess:
1681 1650
1682 WRITE_ONCE(a, 0); 1651 WRITE_ONCE(a, 0);
1683 ... Code that does not store to varia 1652 ... Code that does not store to variable a ...
1684 WRITE_ONCE(a, 0); 1653 WRITE_ONCE(a, 0);
1685 1654
1686 (*) The compiler is within its rights to reo 1655 (*) The compiler is within its rights to reorder memory accesses unless
1687 you tell it not to. For example, consid 1656 you tell it not to. For example, consider the following interaction
1688 between process-level code and an interr 1657 between process-level code and an interrupt handler:
1689 1658
1690 void process_level(void) 1659 void process_level(void)
1691 { 1660 {
1692 msg = get_message(); 1661 msg = get_message();
1693 flag = true; 1662 flag = true;
1694 } 1663 }
1695 1664
1696 void interrupt_handler(void) 1665 void interrupt_handler(void)
1697 { 1666 {
1698 if (flag) 1667 if (flag)
1699 process_message(msg); 1668 process_message(msg);
1700 } 1669 }
1701 1670
1702 There is nothing to prevent the compiler 1671 There is nothing to prevent the compiler from transforming
1703 process_level() to the following, in fac 1672 process_level() to the following, in fact, this might well be a
1704 win for single-threaded code: 1673 win for single-threaded code:
1705 1674
1706 void process_level(void) 1675 void process_level(void)
1707 { 1676 {
1708 flag = true; 1677 flag = true;
1709 msg = get_message(); 1678 msg = get_message();
1710 } 1679 }
1711 1680
1712 If the interrupt occurs between these tw 1681 If the interrupt occurs between these two statement, then
1713 interrupt_handler() might be passed a ga 1682 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
1714 to prevent this as follows: 1683 to prevent this as follows:
1715 1684
1716 void process_level(void) 1685 void process_level(void)
1717 { 1686 {
1718 WRITE_ONCE(msg, get_message() 1687 WRITE_ONCE(msg, get_message());
1719 WRITE_ONCE(flag, true); 1688 WRITE_ONCE(flag, true);
1720 } 1689 }
1721 1690
1722 void interrupt_handler(void) 1691 void interrupt_handler(void)
1723 { 1692 {
1724 if (READ_ONCE(flag)) 1693 if (READ_ONCE(flag))
1725 process_message(READ_ 1694 process_message(READ_ONCE(msg));
1726 } 1695 }
1727 1696
1728 Note that the READ_ONCE() and WRITE_ONCE 1697 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1729 interrupt_handler() are needed if this i 1698 interrupt_handler() are needed if this interrupt handler can itself
1730 be interrupted by something that also ac 1699 be interrupted by something that also accesses 'flag' and 'msg',
1731 for example, a nested interrupt or an NM 1700 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1732 and WRITE_ONCE() are not needed in inter 1701 and WRITE_ONCE() are not needed in interrupt_handler() other than
1733 for documentation purposes. (Note also 1702 for documentation purposes. (Note also that nested interrupts
1734 do not typically occur in modern Linux k 1703 do not typically occur in modern Linux kernels, in fact, if an
1735 interrupt handler returns with interrupt 1704 interrupt handler returns with interrupts enabled, you will get a
1736 WARN_ONCE() splat.) 1705 WARN_ONCE() splat.)
1737 1706
1738 You should assume that the compiler can 1707 You should assume that the compiler can move READ_ONCE() and
1739 WRITE_ONCE() past code not containing RE 1708 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1740 barrier(), or similar primitives. 1709 barrier(), or similar primitives.
1741 1710
1742 This effect could also be achieved using 1711 This effect could also be achieved using barrier(), but READ_ONCE()
1743 and WRITE_ONCE() are more selective: Wi 1712 and WRITE_ONCE() are more selective: With READ_ONCE() and
1744 WRITE_ONCE(), the compiler need only for 1713 WRITE_ONCE(), the compiler need only forget the contents of the
1745 indicated memory locations, while with b 1714 indicated memory locations, while with barrier() the compiler must
1746 discard the value of all memory location !! 1715 discard the value of all memory locations that it has currented
1747 cached in any machine registers. Of cou 1716 cached in any machine registers. Of course, the compiler must also
1748 respect the order in which the READ_ONCE 1717 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1749 though the CPU of course need not do so. 1718 though the CPU of course need not do so.
1750 1719
1751 (*) The compiler is within its rights to inv 1720 (*) The compiler is within its rights to invent stores to a variable,
1752 as in the following example: 1721 as in the following example:
1753 1722
1754 if (a) 1723 if (a)
1755 b = a; 1724 b = a;
1756 else 1725 else
1757 b = 42; 1726 b = 42;
1758 1727
1759 The compiler might save a branch by opti 1728 The compiler might save a branch by optimizing this as follows:
1760 1729
1761 b = 42; 1730 b = 42;
1762 if (a) 1731 if (a)
1763 b = a; 1732 b = a;
1764 1733
1765 In single-threaded code, this is not onl 1734 In single-threaded code, this is not only safe, but also saves
1766 a branch. Unfortunately, in concurrent 1735 a branch. Unfortunately, in concurrent code, this optimization
1767 could cause some other CPU to see a spur 1736 could cause some other CPU to see a spurious value of 42 -- even
1768 if variable 'a' was never zero -- when l 1737 if variable 'a' was never zero -- when loading variable 'b'.
1769 Use WRITE_ONCE() to prevent this as foll 1738 Use WRITE_ONCE() to prevent this as follows:
1770 1739
1771 if (a) 1740 if (a)
1772 WRITE_ONCE(b, a); 1741 WRITE_ONCE(b, a);
1773 else 1742 else
1774 WRITE_ONCE(b, 42); 1743 WRITE_ONCE(b, 42);
1775 1744
1776 The compiler can also invent loads. The 1745 The compiler can also invent loads. These are usually less
1777 damaging, but they can result in cache-l 1746 damaging, but they can result in cache-line bouncing and thus in
1778 poor performance and scalability. Use R 1747 poor performance and scalability. Use READ_ONCE() to prevent
1779 invented loads. 1748 invented loads.
1780 1749
1781 (*) For aligned memory locations whose size 1750 (*) For aligned memory locations whose size allows them to be accessed
1782 with a single memory-reference instructi 1751 with a single memory-reference instruction, prevents "load tearing"
1783 and "store tearing," in which a single l 1752 and "store tearing," in which a single large access is replaced by
1784 multiple smaller accesses. For example, 1753 multiple smaller accesses. For example, given an architecture having
1785 16-bit store instructions with 7-bit imm 1754 16-bit store instructions with 7-bit immediate fields, the compiler
1786 might be tempted to use two 16-bit store 1755 might be tempted to use two 16-bit store-immediate instructions to
1787 implement the following 32-bit store: 1756 implement the following 32-bit store:
1788 1757
1789 p = 0x00010002; 1758 p = 0x00010002;
1790 1759
1791 Please note that GCC really does use thi 1760 Please note that GCC really does use this sort of optimization,
1792 which is not surprising given that it wo 1761 which is not surprising given that it would likely take more
1793 than two instructions to build the const 1762 than two instructions to build the constant and then store it.
1794 This optimization can therefore be a win 1763 This optimization can therefore be a win in single-threaded code.
1795 In fact, a recent bug (since fixed) caus 1764 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1796 this optimization in a volatile store. 1765 this optimization in a volatile store. In the absence of such bugs,
1797 use of WRITE_ONCE() prevents store teari 1766 use of WRITE_ONCE() prevents store tearing in the following example:
1798 1767
1799 WRITE_ONCE(p, 0x00010002); 1768 WRITE_ONCE(p, 0x00010002);
1800 1769
1801 Use of packed structures can also result 1770 Use of packed structures can also result in load and store tearing,
1802 as in this example: 1771 as in this example:
1803 1772
1804 struct __attribute__((__packed__)) fo 1773 struct __attribute__((__packed__)) foo {
1805 short a; 1774 short a;
1806 int b; 1775 int b;
1807 short c; 1776 short c;
1808 }; 1777 };
1809 struct foo foo1, foo2; 1778 struct foo foo1, foo2;
1810 ... 1779 ...
1811 1780
1812 foo2.a = foo1.a; 1781 foo2.a = foo1.a;
1813 foo2.b = foo1.b; 1782 foo2.b = foo1.b;
1814 foo2.c = foo1.c; 1783 foo2.c = foo1.c;
1815 1784
1816 Because there are no READ_ONCE() or WRIT 1785 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1817 volatile markings, the compiler would be 1786 volatile markings, the compiler would be well within its rights to
1818 implement these three assignment stateme 1787 implement these three assignment statements as a pair of 32-bit
1819 loads followed by a pair of 32-bit store 1788 loads followed by a pair of 32-bit stores. This would result in
1820 load tearing on 'foo1.b' and store teari 1789 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1821 and WRITE_ONCE() again prevent tearing i 1790 and WRITE_ONCE() again prevent tearing in this example:
1822 1791
1823 foo2.a = foo1.a; 1792 foo2.a = foo1.a;
1824 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b)) 1793 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
1825 foo2.c = foo1.c; 1794 foo2.c = foo1.c;
1826 1795
1827 All that aside, it is never necessary to use 1796 All that aside, it is never necessary to use READ_ONCE() and
1828 WRITE_ONCE() on a variable that has been mark 1797 WRITE_ONCE() on a variable that has been marked volatile. For example,
1829 because 'jiffies' is marked volatile, it is n 1798 because 'jiffies' is marked volatile, it is never necessary to
1830 say READ_ONCE(jiffies). The reason for this 1799 say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1831 WRITE_ONCE() are implemented as volatile cast 1800 WRITE_ONCE() are implemented as volatile casts, which has no effect when
1832 its argument is already marked volatile. 1801 its argument is already marked volatile.
1833 1802
1834 Please note that these compiler barriers have 1803 Please note that these compiler barriers have no direct effect on the CPU,
1835 which may then reorder things however it wish 1804 which may then reorder things however it wishes.
1836 1805
1837 1806
1838 CPU MEMORY BARRIERS 1807 CPU MEMORY BARRIERS
1839 ------------------- 1808 -------------------
1840 1809
1841 The Linux kernel has seven basic CPU memory b !! 1810 The Linux kernel has eight basic CPU memory barriers:
1842 1811
1843 TYPE MANDATORY !! 1812 TYPE MANDATORY SMP CONDITIONAL
1844 ======================= ============= !! 1813 =============== ======================= ===========================
1845 GENERAL mb() !! 1814 GENERAL mb() smp_mb()
1846 WRITE wmb() !! 1815 WRITE wmb() smp_wmb()
1847 READ rmb() !! 1816 READ rmb() smp_rmb()
1848 ADDRESS DEPENDENCY !! 1817 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1849 1818
1850 1819
1851 All memory barriers except the address-depend !! 1820 All memory barriers except the data dependency barriers imply a compiler
1852 barrier. Address dependencies do not impose !! 1821 barrier. Data dependencies do not impose any additional compiler ordering.
1853 1822
1854 Aside: In the case of address dependencies, t !! 1823 Aside: In the case of data dependencies, the compiler would be expected
1855 to issue the loads in the correct order (eg. 1824 to issue the loads in the correct order (eg. `a[b]` would have to load
1856 the value of b before loading a[b]), however 1825 the value of b before loading a[b]), however there is no guarantee in
1857 the C specification that the compiler may not 1826 the C specification that the compiler may not speculate the value of b
1858 (eg. is equal to 1) and load a[b] before b (e !! 1827 (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1859 tmp = a[b]; ). There is also the problem of 1828 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1860 having loaded a[b], thus having a newer copy 1829 having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1861 has not yet been reached about these problems 1830 has not yet been reached about these problems, however the READ_ONCE()
1862 macro is a good place to start looking. 1831 macro is a good place to start looking.
1863 1832
1864 SMP memory barriers are reduced to compiler b 1833 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1865 systems because it is assumed that a CPU will 1834 systems because it is assumed that a CPU will appear to be self-consistent,
1866 and will order overlapping accesses correctly 1835 and will order overlapping accesses correctly with respect to itself.
1867 However, see the subsection on "Virtual Machi 1836 However, see the subsection on "Virtual Machine Guests" below.
1868 1837
1869 [!] Note that SMP memory barriers _must_ be u 1838 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1870 references to shared memory on SMP systems, t 1839 references to shared memory on SMP systems, though the use of locking instead
1871 is sufficient. 1840 is sufficient.
1872 1841
1873 Mandatory barriers should not be used to cont 1842 Mandatory barriers should not be used to control SMP effects, since mandatory
1874 barriers impose unnecessary overhead on both 1843 barriers impose unnecessary overhead on both SMP and UP systems. They may,
1875 however, be used to control MMIO effects on a 1844 however, be used to control MMIO effects on accesses through relaxed memory I/O
1876 windows. These barriers are required even on 1845 windows. These barriers are required even on non-SMP systems as they affect
1877 the order in which memory operations appear t 1846 the order in which memory operations appear to a device by prohibiting both the
1878 compiler and the CPU from reordering them. 1847 compiler and the CPU from reordering them.
1879 1848
1880 1849
1881 There are some more advanced barrier function 1850 There are some more advanced barrier functions:
1882 1851
1883 (*) smp_store_mb(var, value) 1852 (*) smp_store_mb(var, value)
1884 1853
1885 This assigns the value to the variable a 1854 This assigns the value to the variable and then inserts a full memory
1886 barrier after it. It isn't guaranteed t 1855 barrier after it. It isn't guaranteed to insert anything more than a
1887 compiler barrier in a UP compilation. 1856 compiler barrier in a UP compilation.
1888 1857
1889 1858
1890 (*) smp_mb__before_atomic(); 1859 (*) smp_mb__before_atomic();
1891 (*) smp_mb__after_atomic(); 1860 (*) smp_mb__after_atomic();
1892 1861
1893 These are for use with atomic RMW functi !! 1862 These are for use with atomic (such as add, subtract, increment and
1894 barriers, but where the code needs a mem !! 1863 decrement) functions that don't return a value, especially when used for
1895 RMW functions that do not imply a memory !! 1864 reference counting. These functions do not imply memory barriers.
1896 subtract, (failed) conditional operation <<
1897 but not atomic_read or atomic_set. A com <<
1898 barrier may be required is when atomic o <<
1899 counting. <<
1900 1865
1901 These are also used for atomic RMW bitop !! 1866 These are also used for atomic bitop functions that do not return a
1902 memory barrier (such as set_bit and clea !! 1867 value (such as set_bit and clear_bit).
1903 1868
1904 As an example, consider a piece of code 1869 As an example, consider a piece of code that marks an object as being dead
1905 and then decrements the object's referen 1870 and then decrements the object's reference count:
1906 1871
1907 obj->dead = 1; 1872 obj->dead = 1;
1908 smp_mb__before_atomic(); 1873 smp_mb__before_atomic();
1909 atomic_dec(&obj->ref_count); 1874 atomic_dec(&obj->ref_count);
1910 1875
1911 This makes sure that the death mark on t 1876 This makes sure that the death mark on the object is perceived to be set
1912 *before* the reference counter is decrem 1877 *before* the reference counter is decremented.
1913 1878
1914 See Documentation/atomic_{t,bitops}.txt !! 1879 See Documentation/atomic_ops.txt for more information. See the "Atomic
>> 1880 operations" subsection for information on where to use these.
>> 1881
>> 1882
>> 1883 (*) lockless_dereference();
>> 1884
>> 1885 This can be thought of as a pointer-fetch wrapper around the
>> 1886 smp_read_barrier_depends() data-dependency barrier.
>> 1887
>> 1888 This is also similar to rcu_dereference(), but in cases where
>> 1889 object lifetime is handled by some mechanism other than RCU, for
>> 1890 example, when the objects removed only when the system goes down.
>> 1891 In addition, lockless_dereference() is used in some data structures
>> 1892 that can be used both with and without RCU.
1915 1893
1916 1894
1917 (*) dma_wmb(); 1895 (*) dma_wmb();
1918 (*) dma_rmb(); 1896 (*) dma_rmb();
1919 (*) dma_mb(); <<
1920 1897
1921 These are for use with consistent memory 1898 These are for use with consistent memory to guarantee the ordering
1922 of writes or reads of shared memory acce 1899 of writes or reads of shared memory accessible to both the CPU and a
1923 DMA capable device. See Documentation/co !! 1900 DMA capable device.
1924 information about consistent memory. <<
1925 1901
1926 For example, consider a device driver th 1902 For example, consider a device driver that shares memory with a device
1927 and uses a descriptor status value to in 1903 and uses a descriptor status value to indicate if the descriptor belongs
1928 to the device or the CPU, and a doorbell 1904 to the device or the CPU, and a doorbell to notify it when new
1929 descriptors are available: 1905 descriptors are available:
1930 1906
1931 if (desc->status != DEVICE_OWN) { 1907 if (desc->status != DEVICE_OWN) {
1932 /* do not read data until we 1908 /* do not read data until we own descriptor */
1933 dma_rmb(); 1909 dma_rmb();
1934 1910
1935 /* read/modify data */ 1911 /* read/modify data */
1936 read_data = desc->data; 1912 read_data = desc->data;
1937 desc->data = write_data; 1913 desc->data = write_data;
1938 1914
1939 /* flush modifications before 1915 /* flush modifications before status update */
1940 dma_wmb(); 1916 dma_wmb();
1941 1917
1942 /* assign ownership */ 1918 /* assign ownership */
1943 desc->status = DEVICE_OWN; 1919 desc->status = DEVICE_OWN;
1944 1920
1945 /* Make descriptor status vis !! 1921 /* force memory to sync before notifying device via MMIO */
1946 * notify device of new descr !! 1922 wmb();
1947 */ !! 1923
>> 1924 /* notify device of new descriptors */
1948 writel(DESC_NOTIFY, doorbell) 1925 writel(DESC_NOTIFY, doorbell);
1949 } 1926 }
1950 1927
1951 The dma_rmb() allows us to guarantee tha !! 1928 The dma_rmb() allows us guarantee the device has released ownership
1952 before we read the data from the descrip 1929 before we read the data from the descriptor, and the dma_wmb() allows
1953 us to guarantee the data is written to t 1930 us to guarantee the data is written to the descriptor before the device
1954 can see it now has ownership. The dma_m !! 1931 can see it now has ownership. The wmb() is needed to guarantee that the
1955 a dma_wmb(). !! 1932 cache coherent memory writes have completed before attempting a write to
>> 1933 the cache incoherent MMIO region.
>> 1934
>> 1935 See Documentation/DMA-API.txt for more information on consistent memory.
>> 1936
>> 1937
>> 1938 MMIO WRITE BARRIER
>> 1939 ------------------
>> 1940
>> 1941 The Linux kernel also has a special barrier for use with memory-mapped I/O
>> 1942 writes:
>> 1943
>> 1944 mmiowb();
>> 1945
>> 1946 This is a variation on the mandatory write barrier that causes writes to weakly
>> 1947 ordered I/O regions to be partially ordered. Its effects may go beyond the
>> 1948 CPU->Hardware interface and actually affect the hardware at some level.
>> 1949
>> 1950 See the subsection "Acquires vs I/O accesses" for more information.
1956 1951
1957 Note that the dma_*() barriers do not pr <<
1958 accesses to MMIO regions. See the later <<
1959 subsection for more information about I/ <<
1960 <<
1961 (*) pmem_wmb(); <<
1962 <<
1963 This is for use with persistent memory t <<
1964 modifications are written to persistent <<
1965 durability domain. <<
1966 <<
1967 For example, after a non-temporal write <<
1968 to ensure that stores have reached a pla <<
1969 that stores have updated persistent stor <<
1970 data transfer caused by subsequent instr <<
1971 in addition to the ordering done by wmb( <<
1972 <<
1973 For load from persistent memory, existin <<
1974 to ensure read ordering. <<
1975 <<
1976 (*) io_stop_wc(); <<
1977 <<
1978 For memory accesses with write-combining <<
1979 by ioremap_wc()), the CPU may wait for p <<
1980 subsequent ones. io_stop_wc() can be use <<
1981 write-combining memory accesses before t <<
1982 such wait has performance implications. <<
1983 1952
1984 =============================== 1953 ===============================
1985 IMPLICIT KERNEL MEMORY BARRIERS 1954 IMPLICIT KERNEL MEMORY BARRIERS
1986 =============================== 1955 ===============================
1987 1956
1988 Some of the other functions in the linux kern 1957 Some of the other functions in the linux kernel imply memory barriers, amongst
1989 which are locking and scheduling functions. 1958 which are locking and scheduling functions.
1990 1959
1991 This specification is a _minimum_ guarantee; 1960 This specification is a _minimum_ guarantee; any particular architecture may
1992 provide more substantial guarantees, but thes 1961 provide more substantial guarantees, but these may not be relied upon outside
1993 of arch specific code. 1962 of arch specific code.
1994 1963
1995 1964
1996 LOCK ACQUISITION FUNCTIONS 1965 LOCK ACQUISITION FUNCTIONS
1997 -------------------------- 1966 --------------------------
1998 1967
1999 The Linux kernel has a number of locking cons 1968 The Linux kernel has a number of locking constructs:
2000 1969
2001 (*) spin locks 1970 (*) spin locks
2002 (*) R/W spin locks 1971 (*) R/W spin locks
2003 (*) mutexes 1972 (*) mutexes
2004 (*) semaphores 1973 (*) semaphores
2005 (*) R/W semaphores 1974 (*) R/W semaphores
2006 1975
2007 In all cases there are variants on "ACQUIRE" 1976 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
2008 for each construct. These operations all imp 1977 for each construct. These operations all imply certain barriers:
2009 1978
2010 (1) ACQUIRE operation implication: 1979 (1) ACQUIRE operation implication:
2011 1980
2012 Memory operations issued after the ACQUI 1981 Memory operations issued after the ACQUIRE will be completed after the
2013 ACQUIRE operation has completed. 1982 ACQUIRE operation has completed.
2014 1983
2015 Memory operations issued before the ACQU 1984 Memory operations issued before the ACQUIRE may be completed after
2016 the ACQUIRE operation has completed. !! 1985 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
>> 1986 combined with a following ACQUIRE, orders prior stores against
>> 1987 subsequent loads and stores. Note that this is weaker than smp_mb()!
>> 1988 The smp_mb__before_spinlock() primitive is free on many architectures.
2017 1989
2018 (2) RELEASE operation implication: 1990 (2) RELEASE operation implication:
2019 1991
2020 Memory operations issued before the RELE 1992 Memory operations issued before the RELEASE will be completed before the
2021 RELEASE operation has completed. 1993 RELEASE operation has completed.
2022 1994
2023 Memory operations issued after the RELEA 1995 Memory operations issued after the RELEASE may be completed before the
2024 RELEASE operation has completed. 1996 RELEASE operation has completed.
2025 1997
2026 (3) ACQUIRE vs ACQUIRE implication: 1998 (3) ACQUIRE vs ACQUIRE implication:
2027 1999
2028 All ACQUIRE operations issued before ano 2000 All ACQUIRE operations issued before another ACQUIRE operation will be
2029 completed before that ACQUIRE operation. 2001 completed before that ACQUIRE operation.
2030 2002
2031 (4) ACQUIRE vs RELEASE implication: 2003 (4) ACQUIRE vs RELEASE implication:
2032 2004
2033 All ACQUIRE operations issued before a R 2005 All ACQUIRE operations issued before a RELEASE operation will be
2034 completed before the RELEASE operation. 2006 completed before the RELEASE operation.
2035 2007
2036 (5) Failed conditional ACQUIRE implication: 2008 (5) Failed conditional ACQUIRE implication:
2037 2009
2038 Certain locking variants of the ACQUIRE 2010 Certain locking variants of the ACQUIRE operation may fail, either due to
2039 being unable to get the lock immediately 2011 being unable to get the lock immediately, or due to receiving an unblocked
2040 signal while asleep waiting for the lock !! 2012 signal whilst asleep waiting for the lock to become available. Failed
2041 locks do not imply any sort of barrier. 2013 locks do not imply any sort of barrier.
2042 2014
2043 [!] Note: one of the consequences of lock ACQ 2015 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
2044 one-way barriers is that the effects of instr 2016 one-way barriers is that the effects of instructions outside of a critical
2045 section may seep into the inside of the criti 2017 section may seep into the inside of the critical section.
2046 2018
2047 An ACQUIRE followed by a RELEASE may not be a 2019 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
2048 because it is possible for an access precedin 2020 because it is possible for an access preceding the ACQUIRE to happen after the
2049 ACQUIRE, and an access following the RELEASE 2021 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
2050 the two accesses can themselves then cross: 2022 the two accesses can themselves then cross:
2051 2023
2052 *A = a; 2024 *A = a;
2053 ACQUIRE M 2025 ACQUIRE M
2054 RELEASE M 2026 RELEASE M
2055 *B = b; 2027 *B = b;
2056 2028
2057 may occur as: 2029 may occur as:
2058 2030
2059 ACQUIRE M, STORE *B, STORE *A, RELEAS 2031 ACQUIRE M, STORE *B, STORE *A, RELEASE M
2060 2032
2061 When the ACQUIRE and RELEASE are a lock acqui 2033 When the ACQUIRE and RELEASE are a lock acquisition and release,
2062 respectively, this same reordering can occur 2034 respectively, this same reordering can occur if the lock's ACQUIRE and
2063 RELEASE are to the same lock variable, but on 2035 RELEASE are to the same lock variable, but only from the perspective of
2064 another CPU not holding that lock. In short, 2036 another CPU not holding that lock. In short, a ACQUIRE followed by an
2065 RELEASE may -not- be assumed to be a full mem 2037 RELEASE may -not- be assumed to be a full memory barrier.
2066 2038
2067 Similarly, the reverse case of a RELEASE foll 2039 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
2068 not imply a full memory barrier. Therefore, 2040 not imply a full memory barrier. Therefore, the CPU's execution of the
2069 critical sections corresponding to the RELEAS 2041 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
2070 so that: 2042 so that:
2071 2043
2072 *A = a; 2044 *A = a;
2073 RELEASE M 2045 RELEASE M
2074 ACQUIRE N 2046 ACQUIRE N
2075 *B = b; 2047 *B = b;
2076 2048
2077 could occur as: 2049 could occur as:
2078 2050
2079 ACQUIRE N, STORE *B, STORE *A, RELEAS 2051 ACQUIRE N, STORE *B, STORE *A, RELEASE M
2080 2052
2081 It might appear that this reordering could in 2053 It might appear that this reordering could introduce a deadlock.
2082 However, this cannot happen because if such a 2054 However, this cannot happen because if such a deadlock threatened,
2083 the RELEASE would simply complete, thereby av 2055 the RELEASE would simply complete, thereby avoiding the deadlock.
2084 2056
2085 Why does this work? 2057 Why does this work?
2086 2058
2087 One key point is that we are only tal 2059 One key point is that we are only talking about the CPU doing
2088 the reordering, not the compiler. If 2060 the reordering, not the compiler. If the compiler (or, for
2089 that matter, the developer) switched 2061 that matter, the developer) switched the operations, deadlock
2090 -could- occur. 2062 -could- occur.
2091 2063
2092 But suppose the CPU reordered the ope 2064 But suppose the CPU reordered the operations. In this case,
2093 the unlock precedes the lock in the a 2065 the unlock precedes the lock in the assembly code. The CPU
2094 simply elected to try executing the l 2066 simply elected to try executing the later lock operation first.
2095 If there is a deadlock, this lock ope 2067 If there is a deadlock, this lock operation will simply spin (or
2096 try to sleep, but more on that later) 2068 try to sleep, but more on that later). The CPU will eventually
2097 execute the unlock operation (which p 2069 execute the unlock operation (which preceded the lock operation
2098 in the assembly code), which will unr 2070 in the assembly code), which will unravel the potential deadlock,
2099 allowing the lock operation to succee 2071 allowing the lock operation to succeed.
2100 2072
2101 But what if the lock is a sleeplock? 2073 But what if the lock is a sleeplock? In that case, the code will
2102 try to enter the scheduler, where it 2074 try to enter the scheduler, where it will eventually encounter
2103 a memory barrier, which will force th 2075 a memory barrier, which will force the earlier unlock operation
2104 to complete, again unraveling the dea 2076 to complete, again unraveling the deadlock. There might be
2105 a sleep-unlock race, but the locking 2077 a sleep-unlock race, but the locking primitive needs to resolve
2106 such races properly in any case. 2078 such races properly in any case.
2107 2079
2108 Locks and semaphores may not provide any guar 2080 Locks and semaphores may not provide any guarantee of ordering on UP compiled
2109 systems, and so cannot be counted on in such 2081 systems, and so cannot be counted on in such a situation to actually achieve
2110 anything at all - especially with respect to 2082 anything at all - especially with respect to I/O accesses - unless combined
2111 with interrupt disabling operations. 2083 with interrupt disabling operations.
2112 2084
2113 See also the section on "Inter-CPU acquiring 2085 See also the section on "Inter-CPU acquiring barrier effects".
2114 2086
2115 2087
2116 As an example, consider the following: 2088 As an example, consider the following:
2117 2089
2118 *A = a; 2090 *A = a;
2119 *B = b; 2091 *B = b;
2120 ACQUIRE 2092 ACQUIRE
2121 *C = c; 2093 *C = c;
2122 *D = d; 2094 *D = d;
2123 RELEASE 2095 RELEASE
2124 *E = e; 2096 *E = e;
2125 *F = f; 2097 *F = f;
2126 2098
2127 The following sequence of events is acceptabl 2099 The following sequence of events is acceptable:
2128 2100
2129 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RE 2101 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2130 2102
2131 [+] Note that {*F,*A} indicates a com 2103 [+] Note that {*F,*A} indicates a combined access.
2132 2104
2133 But none of the following are: 2105 But none of the following are:
2134 2106
2135 {*F,*A}, *B, ACQUIRE, *C, *D, 2107 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2136 *A, *B, *C, ACQUIRE, *D, 2108 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2137 *A, *B, ACQUIRE, *C, 2109 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2138 *B, ACQUIRE, *C, *D, 2110 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2139 2111
2140 2112
2141 2113
2142 INTERRUPT DISABLING FUNCTIONS 2114 INTERRUPT DISABLING FUNCTIONS
2143 ----------------------------- 2115 -----------------------------
2144 2116
2145 Functions that disable interrupts (ACQUIRE eq 2117 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
2146 (RELEASE equivalent) will act as compiler bar 2118 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
2147 barriers are required in such a situation, th 2119 barriers are required in such a situation, they must be provided from some
2148 other means. 2120 other means.
2149 2121
2150 2122
2151 SLEEP AND WAKE-UP FUNCTIONS 2123 SLEEP AND WAKE-UP FUNCTIONS
2152 --------------------------- 2124 ---------------------------
2153 2125
2154 Sleeping and waking on an event flagged in gl 2126 Sleeping and waking on an event flagged in global data can be viewed as an
2155 interaction between two pieces of data: the t 2127 interaction between two pieces of data: the task state of the task waiting for
2156 the event and the global data used to indicat 2128 the event and the global data used to indicate the event. To make sure that
2157 these appear to happen in the right order, th 2129 these appear to happen in the right order, the primitives to begin the process
2158 of going to sleep, and the primitives to init 2130 of going to sleep, and the primitives to initiate a wake up imply certain
2159 barriers. 2131 barriers.
2160 2132
2161 Firstly, the sleeper normally follows somethi 2133 Firstly, the sleeper normally follows something like this sequence of events:
2162 2134
2163 for (;;) { 2135 for (;;) {
2164 set_current_state(TASK_UNINTE 2136 set_current_state(TASK_UNINTERRUPTIBLE);
2165 if (event_indicated) 2137 if (event_indicated)
2166 break; 2138 break;
2167 schedule(); 2139 schedule();
2168 } 2140 }
2169 2141
2170 A general memory barrier is interpolated auto 2142 A general memory barrier is interpolated automatically by set_current_state()
2171 after it has altered the task state: 2143 after it has altered the task state:
2172 2144
2173 CPU 1 2145 CPU 1
2174 =============================== 2146 ===============================
2175 set_current_state(); 2147 set_current_state();
2176 smp_store_mb(); 2148 smp_store_mb();
2177 STORE current->state 2149 STORE current->state
2178 <general barrier> 2150 <general barrier>
2179 LOAD event_indicated 2151 LOAD event_indicated
2180 2152
2181 set_current_state() may be wrapped by: 2153 set_current_state() may be wrapped by:
2182 2154
2183 prepare_to_wait(); 2155 prepare_to_wait();
2184 prepare_to_wait_exclusive(); 2156 prepare_to_wait_exclusive();
2185 2157
2186 which therefore also imply a general memory b 2158 which therefore also imply a general memory barrier after setting the state.
2187 The whole sequence above is available in vari 2159 The whole sequence above is available in various canned forms, all of which
2188 interpolate the memory barrier in the right p 2160 interpolate the memory barrier in the right place:
2189 2161
2190 wait_event(); 2162 wait_event();
2191 wait_event_interruptible(); 2163 wait_event_interruptible();
2192 wait_event_interruptible_exclusive(); 2164 wait_event_interruptible_exclusive();
2193 wait_event_interruptible_timeout(); 2165 wait_event_interruptible_timeout();
2194 wait_event_killable(); 2166 wait_event_killable();
2195 wait_event_timeout(); 2167 wait_event_timeout();
2196 wait_on_bit(); 2168 wait_on_bit();
2197 wait_on_bit_lock(); 2169 wait_on_bit_lock();
2198 2170
2199 2171
2200 Secondly, code that performs a wake up normal 2172 Secondly, code that performs a wake up normally follows something like this:
2201 2173
2202 event_indicated = 1; 2174 event_indicated = 1;
2203 wake_up(&event_wait_queue); 2175 wake_up(&event_wait_queue);
2204 2176
2205 or: 2177 or:
2206 2178
2207 event_indicated = 1; 2179 event_indicated = 1;
2208 wake_up_process(event_daemon); 2180 wake_up_process(event_daemon);
2209 2181
2210 A general memory barrier is executed by wake_ !! 2182 A write memory barrier is implied by wake_up() and co. if and only if they
2211 If it doesn't wake anything up then a memory !! 2183 wake something up. The barrier occurs before the task state is cleared, and so
2212 executed; you must not rely on it. The barri !! 2184 sits between the STORE to indicate the event and the STORE to set TASK_RUNNING:
2213 is accessed, in particular, it sits between t <<
2214 and the STORE to set TASK_RUNNING: <<
2215 2185
2216 CPU 1 (Sleeper) CPU 2 !! 2186 CPU 1 CPU 2
2217 =============================== ===== 2187 =============================== ===============================
2218 set_current_state(); STORE 2188 set_current_state(); STORE event_indicated
2219 smp_store_mb(); wake_ 2189 smp_store_mb(); wake_up();
2220 STORE current->state ... !! 2190 STORE current->state <write barrier>
2221 <general barrier> <ge !! 2191 <general barrier> STORE current->state
2222 LOAD event_indicated if !! 2192 LOAD event_indicated
2223 S !! 2193
2224 !! 2194 To repeat, this write memory barrier is present if and only if something
2225 where "task" is the thread being woken up and !! 2195 is actually awakened. To see this, consider the following sequence of
2226 !! 2196 events, where X and Y are both initially zero:
2227 To repeat, a general memory barrier is guaran <<
2228 if something is actually awakened, but otherw <<
2229 To see this, consider the following sequence <<
2230 initially zero: <<
2231 2197
2232 CPU 1 CPU 2 2198 CPU 1 CPU 2
2233 =============================== ===== 2199 =============================== ===============================
2234 X = 1; Y = 1 !! 2200 X = 1; STORE event_indicated
2235 smp_mb(); wake_ 2201 smp_mb(); wake_up();
2236 LOAD Y LOAD !! 2202 Y = 1; wait_event(wq, Y == 1);
2237 !! 2203 wake_up(); load from Y sees 1, no memory barrier
2238 If a wakeup does occur, one (at least) of the !! 2204 load from X might see 0
2239 the other hand, a wakeup does not occur, both <<
2240 2205
2241 wake_up_process() always executes a general m !! 2206 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2242 occurs before the task state is accessed. In !! 2207 to see 1.
2243 the previous snippet were replaced by a call <<
2244 the two loads would be guaranteed to see 1. <<
2245 2208
2246 The available waker functions include: 2209 The available waker functions include:
2247 2210
2248 complete(); 2211 complete();
2249 wake_up(); 2212 wake_up();
2250 wake_up_all(); 2213 wake_up_all();
2251 wake_up_bit(); 2214 wake_up_bit();
2252 wake_up_interruptible(); 2215 wake_up_interruptible();
2253 wake_up_interruptible_all(); 2216 wake_up_interruptible_all();
2254 wake_up_interruptible_nr(); 2217 wake_up_interruptible_nr();
2255 wake_up_interruptible_poll(); 2218 wake_up_interruptible_poll();
2256 wake_up_interruptible_sync(); 2219 wake_up_interruptible_sync();
2257 wake_up_interruptible_sync_poll(); 2220 wake_up_interruptible_sync_poll();
2258 wake_up_locked(); 2221 wake_up_locked();
2259 wake_up_locked_poll(); 2222 wake_up_locked_poll();
2260 wake_up_nr(); 2223 wake_up_nr();
2261 wake_up_poll(); 2224 wake_up_poll();
2262 wake_up_process(); 2225 wake_up_process();
2263 2226
2264 In terms of memory ordering, these functions <<
2265 a wake_up() (or stronger). <<
2266 2227
2267 [!] Note that the memory barriers implied by 2228 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
2268 order multiple stores before the wake-up with 2229 order multiple stores before the wake-up with respect to loads of those stored
2269 values after the sleeper has called set_curre 2230 values after the sleeper has called set_current_state(). For instance, if the
2270 sleeper does: 2231 sleeper does:
2271 2232
2272 set_current_state(TASK_INTERRUPTIBLE) 2233 set_current_state(TASK_INTERRUPTIBLE);
2273 if (event_indicated) 2234 if (event_indicated)
2274 break; 2235 break;
2275 __set_current_state(TASK_RUNNING); 2236 __set_current_state(TASK_RUNNING);
2276 do_something(my_data); 2237 do_something(my_data);
2277 2238
2278 and the waker does: 2239 and the waker does:
2279 2240
2280 my_data = value; 2241 my_data = value;
2281 event_indicated = 1; 2242 event_indicated = 1;
2282 wake_up(&event_wait_queue); 2243 wake_up(&event_wait_queue);
2283 2244
2284 there's no guarantee that the change to event 2245 there's no guarantee that the change to event_indicated will be perceived by
2285 the sleeper as coming after the change to my_ 2246 the sleeper as coming after the change to my_data. In such a circumstance, the
2286 code on both sides must interpolate its own m 2247 code on both sides must interpolate its own memory barriers between the
2287 separate data accesses. Thus the above sleep 2248 separate data accesses. Thus the above sleeper ought to do:
2288 2249
2289 set_current_state(TASK_INTERRUPTIBLE) 2250 set_current_state(TASK_INTERRUPTIBLE);
2290 if (event_indicated) { 2251 if (event_indicated) {
2291 smp_rmb(); 2252 smp_rmb();
2292 do_something(my_data); 2253 do_something(my_data);
2293 } 2254 }
2294 2255
2295 and the waker should do: 2256 and the waker should do:
2296 2257
2297 my_data = value; 2258 my_data = value;
2298 smp_wmb(); 2259 smp_wmb();
2299 event_indicated = 1; 2260 event_indicated = 1;
2300 wake_up(&event_wait_queue); 2261 wake_up(&event_wait_queue);
2301 2262
2302 2263
2303 MISCELLANEOUS FUNCTIONS 2264 MISCELLANEOUS FUNCTIONS
2304 ----------------------- 2265 -----------------------
2305 2266
2306 Other functions that imply barriers: 2267 Other functions that imply barriers:
2307 2268
2308 (*) schedule() and similar imply full memory 2269 (*) schedule() and similar imply full memory barriers.
2309 2270
2310 2271
2311 =================================== 2272 ===================================
2312 INTER-CPU ACQUIRING BARRIER EFFECTS 2273 INTER-CPU ACQUIRING BARRIER EFFECTS
2313 =================================== 2274 ===================================
2314 2275
2315 On SMP systems locking primitives give a more 2276 On SMP systems locking primitives give a more substantial form of barrier: one
2316 that does affect memory access ordering on ot 2277 that does affect memory access ordering on other CPUs, within the context of
2317 conflict on any particular lock. 2278 conflict on any particular lock.
2318 2279
2319 2280
2320 ACQUIRES VS MEMORY ACCESSES 2281 ACQUIRES VS MEMORY ACCESSES
2321 --------------------------- 2282 ---------------------------
2322 2283
2323 Consider the following: the system has a pair 2284 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2324 three CPUs; then should the following sequenc 2285 three CPUs; then should the following sequence of events occur:
2325 2286
2326 CPU 1 CPU 2 2287 CPU 1 CPU 2
2327 =============================== ===== 2288 =============================== ===============================
2328 WRITE_ONCE(*A, a); WRITE 2289 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2329 ACQUIRE M ACQUI 2290 ACQUIRE M ACQUIRE Q
2330 WRITE_ONCE(*B, b); WRITE 2291 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2331 WRITE_ONCE(*C, c); WRITE 2292 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
2332 RELEASE M RELEA 2293 RELEASE M RELEASE Q
2333 WRITE_ONCE(*D, d); WRITE 2294 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
2334 2295
2335 Then there is no guarantee as to what order C 2296 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2336 through *H occur in, other than the constrain 2297 through *H occur in, other than the constraints imposed by the separate locks
2337 on the separate CPUs. It might, for example, 2298 on the separate CPUs. It might, for example, see:
2338 2299
2339 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, 2300 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2340 2301
2341 But it won't see any of: 2302 But it won't see any of:
2342 2303
2343 *B, *C or *D preceding ACQUIRE M 2304 *B, *C or *D preceding ACQUIRE M
2344 *A, *B or *C following RELEASE M 2305 *A, *B or *C following RELEASE M
2345 *F, *G or *H preceding ACQUIRE Q 2306 *F, *G or *H preceding ACQUIRE Q
2346 *E, *F or *G following RELEASE Q 2307 *E, *F or *G following RELEASE Q
2347 2308
2348 2309
>> 2310
>> 2311 ACQUIRES VS I/O ACCESSES
>> 2312 ------------------------
>> 2313
>> 2314 Under certain circumstances (especially involving NUMA), I/O accesses within
>> 2315 two spinlocked sections on two different CPUs may be seen as interleaved by the
>> 2316 PCI bridge, because the PCI bridge does not necessarily participate in the
>> 2317 cache-coherence protocol, and is therefore incapable of issuing the required
>> 2318 read memory barriers.
>> 2319
>> 2320 For example:
>> 2321
>> 2322 CPU 1 CPU 2
>> 2323 =============================== ===============================
>> 2324 spin_lock(Q)
>> 2325 writel(0, ADDR)
>> 2326 writel(1, DATA);
>> 2327 spin_unlock(Q);
>> 2328 spin_lock(Q);
>> 2329 writel(4, ADDR);
>> 2330 writel(5, DATA);
>> 2331 spin_unlock(Q);
>> 2332
>> 2333 may be seen by the PCI bridge as follows:
>> 2334
>> 2335 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
>> 2336
>> 2337 which would probably cause the hardware to malfunction.
>> 2338
>> 2339
>> 2340 What is necessary here is to intervene with an mmiowb() before dropping the
>> 2341 spinlock, for example:
>> 2342
>> 2343 CPU 1 CPU 2
>> 2344 =============================== ===============================
>> 2345 spin_lock(Q)
>> 2346 writel(0, ADDR)
>> 2347 writel(1, DATA);
>> 2348 mmiowb();
>> 2349 spin_unlock(Q);
>> 2350 spin_lock(Q);
>> 2351 writel(4, ADDR);
>> 2352 writel(5, DATA);
>> 2353 mmiowb();
>> 2354 spin_unlock(Q);
>> 2355
>> 2356 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
>> 2357 before either of the stores issued on CPU 2.
>> 2358
>> 2359
>> 2360 Furthermore, following a store by a load from the same device obviates the need
>> 2361 for the mmiowb(), because the load forces the store to complete before the load
>> 2362 is performed:
>> 2363
>> 2364 CPU 1 CPU 2
>> 2365 =============================== ===============================
>> 2366 spin_lock(Q)
>> 2367 writel(0, ADDR)
>> 2368 a = readl(DATA);
>> 2369 spin_unlock(Q);
>> 2370 spin_lock(Q);
>> 2371 writel(4, ADDR);
>> 2372 b = readl(DATA);
>> 2373 spin_unlock(Q);
>> 2374
>> 2375
>> 2376 See Documentation/driver-api/device-io.rst for more information.
>> 2377
>> 2378
2349 ================================= 2379 =================================
2350 WHERE ARE MEMORY BARRIERS NEEDED? 2380 WHERE ARE MEMORY BARRIERS NEEDED?
2351 ================================= 2381 =================================
2352 2382
2353 Under normal operation, memory operation reor 2383 Under normal operation, memory operation reordering is generally not going to
2354 be a problem as a single-threaded linear piec 2384 be a problem as a single-threaded linear piece of code will still appear to
2355 work correctly, even if it's in an SMP kernel 2385 work correctly, even if it's in an SMP kernel. There are, however, four
2356 circumstances in which reordering definitely 2386 circumstances in which reordering definitely _could_ be a problem:
2357 2387
2358 (*) Interprocessor interaction. 2388 (*) Interprocessor interaction.
2359 2389
2360 (*) Atomic operations. 2390 (*) Atomic operations.
2361 2391
2362 (*) Accessing devices. 2392 (*) Accessing devices.
2363 2393
2364 (*) Interrupts. 2394 (*) Interrupts.
2365 2395
2366 2396
2367 INTERPROCESSOR INTERACTION 2397 INTERPROCESSOR INTERACTION
2368 -------------------------- 2398 --------------------------
2369 2399
2370 When there's a system with more than one proc 2400 When there's a system with more than one processor, more than one CPU in the
2371 system may be working on the same data set at 2401 system may be working on the same data set at the same time. This can cause
2372 synchronisation problems, and the usual way o 2402 synchronisation problems, and the usual way of dealing with them is to use
2373 locks. Locks, however, are quite expensive, 2403 locks. Locks, however, are quite expensive, and so it may be preferable to
2374 operate without the use of a lock if at all p 2404 operate without the use of a lock if at all possible. In such a case
2375 operations that affect both CPUs may have to 2405 operations that affect both CPUs may have to be carefully ordered to prevent
2376 a malfunction. 2406 a malfunction.
2377 2407
2378 Consider, for example, the R/W semaphore slow 2408 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2379 queued on the semaphore, by virtue of it havi 2409 queued on the semaphore, by virtue of it having a piece of its stack linked to
2380 the semaphore's list of waiting processes: 2410 the semaphore's list of waiting processes:
2381 2411
2382 struct rw_semaphore { 2412 struct rw_semaphore {
2383 ... 2413 ...
2384 spinlock_t lock; 2414 spinlock_t lock;
2385 struct list_head waiters; 2415 struct list_head waiters;
2386 }; 2416 };
2387 2417
2388 struct rwsem_waiter { 2418 struct rwsem_waiter {
2389 struct list_head list; 2419 struct list_head list;
2390 struct task_struct *task; 2420 struct task_struct *task;
2391 }; 2421 };
2392 2422
2393 To wake up a particular waiter, the up_read() 2423 To wake up a particular waiter, the up_read() or up_write() functions have to:
2394 2424
2395 (1) read the next pointer from this waiter's 2425 (1) read the next pointer from this waiter's record to know as to where the
2396 next waiter record is; 2426 next waiter record is;
2397 2427
2398 (2) read the pointer to the waiter's task st 2428 (2) read the pointer to the waiter's task structure;
2399 2429
2400 (3) clear the task pointer to tell the waite 2430 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2401 2431
2402 (4) call wake_up_process() on the task; and 2432 (4) call wake_up_process() on the task; and
2403 2433
2404 (5) release the reference held on the waiter 2434 (5) release the reference held on the waiter's task struct.
2405 2435
2406 In other words, it has to perform this sequen 2436 In other words, it has to perform this sequence of events:
2407 2437
2408 LOAD waiter->list.next; 2438 LOAD waiter->list.next;
2409 LOAD waiter->task; 2439 LOAD waiter->task;
2410 STORE waiter->task; 2440 STORE waiter->task;
2411 CALL wakeup 2441 CALL wakeup
2412 RELEASE task 2442 RELEASE task
2413 2443
2414 and if any of these steps occur out of order, 2444 and if any of these steps occur out of order, then the whole thing may
2415 malfunction. 2445 malfunction.
2416 2446
2417 Once it has queued itself and dropped the sem 2447 Once it has queued itself and dropped the semaphore lock, the waiter does not
2418 get the lock again; it instead just waits for 2448 get the lock again; it instead just waits for its task pointer to be cleared
2419 before proceeding. Since the record is on th 2449 before proceeding. Since the record is on the waiter's stack, this means that
2420 if the task pointer is cleared _before_ the n 2450 if the task pointer is cleared _before_ the next pointer in the list is read,
2421 another CPU might start processing the waiter 2451 another CPU might start processing the waiter and might clobber the waiter's
2422 stack before the up*() function has a chance 2452 stack before the up*() function has a chance to read the next pointer.
2423 2453
2424 Consider then what might happen to the above 2454 Consider then what might happen to the above sequence of events:
2425 2455
2426 CPU 1 CPU 2 2456 CPU 1 CPU 2
2427 =============================== ===== 2457 =============================== ===============================
2428 down_ 2458 down_xxx()
2429 Queue 2459 Queue waiter
2430 Sleep 2460 Sleep
2431 up_yyy() 2461 up_yyy()
2432 LOAD waiter->task; 2462 LOAD waiter->task;
2433 STORE waiter->task; 2463 STORE waiter->task;
2434 Woken 2464 Woken up by other event
2435 <preempt> 2465 <preempt>
2436 Resum 2466 Resume processing
2437 down_ 2467 down_xxx() returns
2438 call 2468 call foo()
2439 foo() 2469 foo() clobbers *waiter
2440 </preempt> 2470 </preempt>
2441 LOAD waiter->list.next; 2471 LOAD waiter->list.next;
2442 --- OOPS --- 2472 --- OOPS ---
2443 2473
2444 This could be dealt with using the semaphore 2474 This could be dealt with using the semaphore lock, but then the down_xxx()
2445 function has to needlessly get the spinlock a 2475 function has to needlessly get the spinlock again after being woken up.
2446 2476
2447 The way to deal with this is to insert a gene 2477 The way to deal with this is to insert a general SMP memory barrier:
2448 2478
2449 LOAD waiter->list.next; 2479 LOAD waiter->list.next;
2450 LOAD waiter->task; 2480 LOAD waiter->task;
2451 smp_mb(); 2481 smp_mb();
2452 STORE waiter->task; 2482 STORE waiter->task;
2453 CALL wakeup 2483 CALL wakeup
2454 RELEASE task 2484 RELEASE task
2455 2485
2456 In this case, the barrier makes a guarantee t 2486 In this case, the barrier makes a guarantee that all memory accesses before the
2457 barrier will appear to happen before all the 2487 barrier will appear to happen before all the memory accesses after the barrier
2458 with respect to the other CPUs on the system. 2488 with respect to the other CPUs on the system. It does _not_ guarantee that all
2459 the memory accesses before the barrier will b 2489 the memory accesses before the barrier will be complete by the time the barrier
2460 instruction itself is complete. 2490 instruction itself is complete.
2461 2491
2462 On a UP system - where this wouldn't be a pro 2492 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2463 compiler barrier, thus making sure the compil 2493 compiler barrier, thus making sure the compiler emits the instructions in the
2464 right order without actually intervening in t 2494 right order without actually intervening in the CPU. Since there's only one
2465 CPU, that CPU's dependency ordering logic wil 2495 CPU, that CPU's dependency ordering logic will take care of everything else.
2466 2496
2467 2497
2468 ATOMIC OPERATIONS 2498 ATOMIC OPERATIONS
2469 ----------------- 2499 -----------------
2470 2500
2471 While they are technically interprocessor int !! 2501 Whilst they are technically interprocessor interaction considerations, atomic
2472 operations are noted specially as some of the 2502 operations are noted specially as some of them imply full memory barriers and
2473 some don't, but they're very heavily relied o 2503 some don't, but they're very heavily relied on as a group throughout the
2474 kernel. 2504 kernel.
2475 2505
2476 See Documentation/atomic_t.txt for more infor !! 2506 Any atomic operation that modifies some state in memory and returns information
>> 2507 about the state (old or new) implies an SMP-conditional general memory barrier
>> 2508 (smp_mb()) on each side of the actual operation (with the exception of
>> 2509 explicit lock operations, described later). These include:
>> 2510
>> 2511 xchg();
>> 2512 atomic_xchg(); atomic_long_xchg();
>> 2513 atomic_inc_return(); atomic_long_inc_return();
>> 2514 atomic_dec_return(); atomic_long_dec_return();
>> 2515 atomic_add_return(); atomic_long_add_return();
>> 2516 atomic_sub_return(); atomic_long_sub_return();
>> 2517 atomic_inc_and_test(); atomic_long_inc_and_test();
>> 2518 atomic_dec_and_test(); atomic_long_dec_and_test();
>> 2519 atomic_sub_and_test(); atomic_long_sub_and_test();
>> 2520 atomic_add_negative(); atomic_long_add_negative();
>> 2521 test_and_set_bit();
>> 2522 test_and_clear_bit();
>> 2523 test_and_change_bit();
>> 2524
>> 2525 /* when succeeds */
>> 2526 cmpxchg();
>> 2527 atomic_cmpxchg(); atomic_long_cmpxchg();
>> 2528 atomic_add_unless(); atomic_long_add_unless();
>> 2529
>> 2530 These are used for such things as implementing ACQUIRE-class and RELEASE-class
>> 2531 operations and adjusting reference counters towards object destruction, and as
>> 2532 such the implicit memory barrier effects are necessary.
>> 2533
>> 2534
>> 2535 The following operations are potential problems as they do _not_ imply memory
>> 2536 barriers, but might be used for implementing such things as RELEASE-class
>> 2537 operations:
>> 2538
>> 2539 atomic_set();
>> 2540 set_bit();
>> 2541 clear_bit();
>> 2542 change_bit();
>> 2543
>> 2544 With these the appropriate explicit memory barrier should be used if necessary
>> 2545 (smp_mb__before_atomic() for instance).
>> 2546
>> 2547
>> 2548 The following also do _not_ imply memory barriers, and so may require explicit
>> 2549 memory barriers under some circumstances (smp_mb__before_atomic() for
>> 2550 instance):
>> 2551
>> 2552 atomic_add();
>> 2553 atomic_sub();
>> 2554 atomic_inc();
>> 2555 atomic_dec();
>> 2556
>> 2557 If they're used for statistics generation, then they probably don't need memory
>> 2558 barriers, unless there's a coupling between statistical data.
>> 2559
>> 2560 If they're used for reference counting on an object to control its lifetime,
>> 2561 they probably don't need memory barriers because either the reference count
>> 2562 will be adjusted inside a locked section, or the caller will already hold
>> 2563 sufficient references to make the lock, and thus a memory barrier unnecessary.
>> 2564
>> 2565 If they're used for constructing a lock of some description, then they probably
>> 2566 do need memory barriers as a lock primitive generally has to do things in a
>> 2567 specific order.
>> 2568
>> 2569 Basically, each usage case has to be carefully considered as to whether memory
>> 2570 barriers are needed or not.
>> 2571
>> 2572 The following operations are special locking primitives:
>> 2573
>> 2574 test_and_set_bit_lock();
>> 2575 clear_bit_unlock();
>> 2576 __clear_bit_unlock();
>> 2577
>> 2578 These implement ACQUIRE-class and RELEASE-class operations. These should be
>> 2579 used in preference to other operations when implementing locking primitives,
>> 2580 because their implementations can be optimised on many architectures.
>> 2581
>> 2582 [!] Note that special memory barrier primitives are available for these
>> 2583 situations because on some CPUs the atomic instructions used imply full memory
>> 2584 barriers, and so barrier instructions are superfluous in conjunction with them,
>> 2585 and in such cases the special barrier primitives will be no-ops.
>> 2586
>> 2587 See Documentation/atomic_ops.txt for more information.
2477 2588
2478 2589
2479 ACCESSING DEVICES 2590 ACCESSING DEVICES
2480 ----------------- 2591 -----------------
2481 2592
2482 Many devices can be memory mapped, and so app 2593 Many devices can be memory mapped, and so appear to the CPU as if they're just
2483 a set of memory locations. To control such a 2594 a set of memory locations. To control such a device, the driver usually has to
2484 make the right memory accesses in exactly the 2595 make the right memory accesses in exactly the right order.
2485 2596
2486 However, having a clever CPU or a clever comp 2597 However, having a clever CPU or a clever compiler creates a potential problem
2487 in that the carefully sequenced accesses in t 2598 in that the carefully sequenced accesses in the driver code won't reach the
2488 device in the requisite order if the CPU or t 2599 device in the requisite order if the CPU or the compiler thinks it is more
2489 efficient to reorder, combine or merge access 2600 efficient to reorder, combine or merge accesses - something that would cause
2490 the device to malfunction. 2601 the device to malfunction.
2491 2602
2492 Inside of the Linux kernel, I/O should be don 2603 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2493 routines - such as inb() or writel() - which 2604 routines - such as inb() or writel() - which know how to make such accesses
2494 appropriately sequential. While this, for th !! 2605 appropriately sequential. Whilst this, for the most part, renders the explicit
2495 use of memory barriers unnecessary, if the ac !! 2606 use of memory barriers unnecessary, there are a couple of situations where they
2496 to an I/O memory window with relaxed memory a !! 2607 might be needed:
2497 memory barriers are required to enforce order !! 2608
>> 2609 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
>> 2610 so for _all_ general drivers locks should be used and mmiowb() must be
>> 2611 issued prior to unlocking the critical section.
>> 2612
>> 2613 (2) If the accessor functions are used to refer to an I/O memory window with
>> 2614 relaxed memory access properties, then _mandatory_ memory barriers are
>> 2615 required to enforce ordering.
2498 2616
2499 See Documentation/driver-api/device-io.rst fo 2617 See Documentation/driver-api/device-io.rst for more information.
2500 2618
2501 2619
2502 INTERRUPTS 2620 INTERRUPTS
2503 ---------- 2621 ----------
2504 2622
2505 A driver may be interrupted by its own interr 2623 A driver may be interrupted by its own interrupt service routine, and thus the
2506 two parts of the driver may interfere with ea 2624 two parts of the driver may interfere with each other's attempts to control or
2507 access the device. 2625 access the device.
2508 2626
2509 This may be alleviated - at least in part - b 2627 This may be alleviated - at least in part - by disabling local interrupts (a
2510 form of locking), such that the critical oper 2628 form of locking), such that the critical operations are all contained within
2511 the interrupt-disabled section in the driver. !! 2629 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2512 routine is executing, the driver's core may n 2630 routine is executing, the driver's core may not run on the same CPU, and its
2513 interrupt is not permitted to happen again un 2631 interrupt is not permitted to happen again until the current interrupt has been
2514 handled, thus the interrupt handler does not 2632 handled, thus the interrupt handler does not need to lock against that.
2515 2633
2516 However, consider a driver that was talking t 2634 However, consider a driver that was talking to an ethernet card that sports an
2517 address register and a data register. If tha 2635 address register and a data register. If that driver's core talks to the card
2518 under interrupt-disablement and then the driv 2636 under interrupt-disablement and then the driver's interrupt handler is invoked:
2519 2637
2520 LOCAL IRQ DISABLE 2638 LOCAL IRQ DISABLE
2521 writew(ADDR, 3); 2639 writew(ADDR, 3);
2522 writew(DATA, y); 2640 writew(DATA, y);
2523 LOCAL IRQ ENABLE 2641 LOCAL IRQ ENABLE
2524 <interrupt> 2642 <interrupt>
2525 writew(ADDR, 4); 2643 writew(ADDR, 4);
2526 q = readw(DATA); 2644 q = readw(DATA);
2527 </interrupt> 2645 </interrupt>
2528 2646
2529 The store to the data register might happen a 2647 The store to the data register might happen after the second store to the
2530 address register if ordering rules are suffic 2648 address register if ordering rules are sufficiently relaxed:
2531 2649
2532 STORE *ADDR = 3, STORE *ADDR = 4, STO 2650 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2533 2651
2534 2652
2535 If ordering rules are relaxed, it must be ass 2653 If ordering rules are relaxed, it must be assumed that accesses done inside an
2536 interrupt disabled section may leak outside o 2654 interrupt disabled section may leak outside of it and may interleave with
2537 accesses performed in an interrupt - and vice 2655 accesses performed in an interrupt - and vice versa - unless implicit or
2538 explicit barriers are used. 2656 explicit barriers are used.
2539 2657
2540 Normally this won't be a problem because the 2658 Normally this won't be a problem because the I/O accesses done inside such
2541 sections will include synchronous load operat 2659 sections will include synchronous load operations on strictly ordered I/O
2542 registers that form implicit I/O barriers. !! 2660 registers that form implicit I/O barriers. If this isn't sufficient then an
>> 2661 mmiowb() may need to be used explicitly.
2543 2662
2544 2663
2545 A similar situation may occur between an inte 2664 A similar situation may occur between an interrupt routine and two routines
2546 running on separate CPUs that communicate wit 2665 running on separate CPUs that communicate with each other. If such a case is
2547 likely, then interrupt-disabling locks should 2666 likely, then interrupt-disabling locks should be used to guarantee ordering.
2548 2667
2549 2668
2550 ========================== 2669 ==========================
2551 KERNEL I/O BARRIER EFFECTS 2670 KERNEL I/O BARRIER EFFECTS
2552 ========================== 2671 ==========================
2553 2672
2554 Interfacing with peripherals via I/O accesses !! 2673 When accessing I/O memory, drivers should use the appropriate accessor
2555 specific. Therefore, drivers which are inhere !! 2674 functions:
2556 specific behaviours of their target systems i !! 2675
2557 in the most lightweight manner possible. For !! 2676 (*) inX(), outX():
2558 between multiple architectures and bus implem !! 2677
2559 series of accessor functions that provide var !! 2678 These are intended to talk to I/O space rather than memory space, but
2560 guarantees: !! 2679 that's primarily a CPU-specific concept. The i386 and x86_64 processors
>> 2680 do indeed have special I/O space access cycles and instructions, but many
>> 2681 CPUs don't have such a concept.
>> 2682
>> 2683 The PCI bus, amongst others, defines an I/O space concept which - on such
>> 2684 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
>> 2685 space. However, it may also be mapped as a virtual I/O space in the CPU's
>> 2686 memory map, particularly on those CPUs that don't support alternate I/O
>> 2687 spaces.
>> 2688
>> 2689 Accesses to this space may be fully synchronous (as on i386), but
>> 2690 intermediary bridges (such as the PCI host bridge) may not fully honour
>> 2691 that.
>> 2692
>> 2693 They are guaranteed to be fully ordered with respect to each other.
>> 2694
>> 2695 They are not guaranteed to be fully ordered with respect to other types of
>> 2696 memory and I/O operation.
2561 2697
2562 (*) readX(), writeX(): 2698 (*) readX(), writeX():
2563 2699
2564 The readX() and writeX() MMIO accesso !! 2700 Whether these are guaranteed to be fully ordered and uncombined with
2565 peripheral being accessed as an __iom !! 2701 respect to each other on the issuing CPU depends on the characteristics
2566 mapped with the default I/O attribute !! 2702 defined for the memory window through which they're accessing. On later
2567 ioremap()), the ordering guarantees a !! 2703 i386 architecture machines, for example, this is controlled by way of the
2568 !! 2704 MTRR registers.
2569 1. All readX() and writeX() accesses !! 2705
2570 with respect to each other. This e !! 2706 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2571 by the same CPU thread to a partic !! 2707 provided they're not accessing a prefetchable device.
2572 order. !! 2708
2573 !! 2709 However, intermediary hardware (such as a PCI bridge) may indulge in
2574 2. A writeX() issued by a CPU thread !! 2710 deferral if it so wishes; to flush a store, a load from the same location
2575 before a writeX() to the same peri !! 2711 is preferred[*], but a load from the same device or from configuration
2576 issued after a later acquisition o !! 2712 space should suffice for PCI.
2577 that MMIO register writes to a par !! 2713
2578 a spinlock will arrive in an order !! 2714 [*] NOTE! attempting to load from the same location as was written to may
2579 the lock. !! 2715 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2580 !! 2716 example.
2581 3. A writeX() by a CPU thread to the !! 2717
2582 completion of all prior writes to !! 2718 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2583 propagated to, the same thread. Th !! 2719 force stores to be ordered.
2584 to an outbound DMA buffer allocate !! 2720
2585 visible to a DMA engine when the C !! 2721 Please refer to the PCI specification for more information on interactions
2586 register to trigger the transfer. !! 2722 between PCI transactions.
2587 !! 2723
2588 4. A readX() by a CPU thread from the !! 2724 (*) readX_relaxed(), writeX_relaxed()
2589 any subsequent reads from memory b !! 2725
2590 ensures that reads by the CPU from !! 2726 These are similar to readX() and writeX(), but provide weaker memory
2591 by dma_alloc_coherent() will not s !! 2727 ordering guarantees. Specifically, they do not guarantee ordering with
2592 the DMA engine's MMIO status regis !! 2728 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2593 transfer has completed. !! 2729 ordering with respect to LOCK or UNLOCK operations. If the latter is
2594 !! 2730 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2595 5. A readX() by a CPU thread from the !! 2731 the same peripheral are guaranteed to be ordered with respect to each
2596 any subsequent delay() loop can be !! 2732 other.
2597 This ensures that two MMIO registe <<
2598 will arrive at least 1us apart if <<
2599 back with readX() and udelay(1) is <<
2600 writeX(): <<
2601 <<
2602 writel(42, DEVICE_REGISTER_0) <<
2603 readl(DEVICE_REGISTER_0); <<
2604 udelay(1); <<
2605 writel(42, DEVICE_REGISTER_1) <<
2606 <<
2607 The ordering properties of __iomem po <<
2608 attributes (e.g. those returned by io <<
2609 underlying architecture and therefore <<
2610 generally be relied upon for accesses <<
2611 <<
2612 (*) readX_relaxed(), writeX_relaxed(): <<
2613 <<
2614 These are similar to readX() and writ <<
2615 ordering guarantees. Specifically, th <<
2616 respect to locking, normal memory acc <<
2617 bullets 2-5 above) but they are still <<
2618 respect to other accesses from the sa <<
2619 peripheral when operating on __iomem <<
2620 I/O attributes. <<
2621 <<
2622 (*) readsX(), writesX(): <<
2623 <<
2624 The readsX() and writesX() MMIO acces <<
2625 register-based, memory-mapped FIFOs r <<
2626 capable of performing DMA. Consequent <<
2627 guarantees of readX_relaxed() and wri <<
2628 2733
2629 (*) inX(), outX(): !! 2734 (*) ioreadX(), iowriteX()
2630 2735
2631 The inX() and outX() accessors are in !! 2736 These will perform appropriately for the type of access they're actually
2632 I/O peripherals, which may require sp !! 2737 doing, be it inX()/outX() or readX()/writeX().
2633 architectures (notably x86). The port <<
2634 accessed is passed as an argument. <<
2635 <<
2636 Since many CPU architectures ultimate <<
2637 internal virtual memory mapping, the <<
2638 provided by inX() and outX() are the <<
2639 and writeX() respectively when access <<
2640 attributes. <<
2641 <<
2642 Device drivers may expect outX() to e <<
2643 that waits for a completion response <<
2644 returning. This is not guaranteed by <<
2645 not part of the portable ordering sem <<
2646 <<
2647 (*) insX(), outsX(): <<
2648 <<
2649 As above, the insX() and outsX() acce <<
2650 guarantees as readsX() and writesX() <<
2651 mapping with the default I/O attribut <<
2652 <<
2653 (*) ioreadX(), iowriteX(): <<
2654 <<
2655 These will perform appropriately for <<
2656 doing, be it inX()/outX() or readX()/ <<
2657 <<
2658 With the exception of the string accessors (i <<
2659 writesX()), all of the above assume that the <<
2660 little-endian and will therefore perform byte <<
2661 architectures. <<
2662 2738
2663 2739
2664 ======================================== 2740 ========================================
2665 ASSUMED MINIMUM EXECUTION ORDERING MODEL 2741 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2666 ======================================== 2742 ========================================
2667 2743
2668 It has to be assumed that the conceptual CPU 2744 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2669 maintain the appearance of program causality 2745 maintain the appearance of program causality with respect to itself. Some CPUs
2670 (such as i386 or x86_64) are more constrained 2746 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2671 frv), and so the most relaxed case (namely DE 2747 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2672 of arch-specific code. 2748 of arch-specific code.
2673 2749
2674 This means that it must be considered that th 2750 This means that it must be considered that the CPU will execute its instruction
2675 stream in any order it feels like - or even i 2751 stream in any order it feels like - or even in parallel - provided that if an
2676 instruction in the stream depends on an earli 2752 instruction in the stream depends on an earlier instruction, then that
2677 earlier instruction must be sufficiently comp 2753 earlier instruction must be sufficiently complete[*] before the later
2678 instruction may proceed; in other words: prov 2754 instruction may proceed; in other words: provided that the appearance of
2679 causality is maintained. 2755 causality is maintained.
2680 2756
2681 [*] Some instructions have more than one eff 2757 [*] Some instructions have more than one effect - such as changing the
2682 condition codes, changing registers or c 2758 condition codes, changing registers or changing memory - and different
2683 instructions may depend on different eff 2759 instructions may depend on different effects.
2684 2760
2685 A CPU may also discard any instruction sequen 2761 A CPU may also discard any instruction sequence that winds up having no
2686 ultimate effect. For example, if two adjacen 2762 ultimate effect. For example, if two adjacent instructions both load an
2687 immediate value into the same register, the f 2763 immediate value into the same register, the first may be discarded.
2688 2764
2689 2765
2690 Similarly, it has to be assumed that compiler 2766 Similarly, it has to be assumed that compiler might reorder the instruction
2691 stream in any way it sees fit, again provided 2767 stream in any way it sees fit, again provided the appearance of causality is
2692 maintained. 2768 maintained.
2693 2769
2694 2770
2695 ============================ 2771 ============================
2696 THE EFFECTS OF THE CPU CACHE 2772 THE EFFECTS OF THE CPU CACHE
2697 ============================ 2773 ============================
2698 2774
2699 The way cached memory operations are perceive 2775 The way cached memory operations are perceived across the system is affected to
2700 a certain extent by the caches that lie betwe 2776 a certain extent by the caches that lie between CPUs and memory, and by the
2701 memory coherence system that maintains the co 2777 memory coherence system that maintains the consistency of state in the system.
2702 2778
2703 As far as the way a CPU interacts with anothe 2779 As far as the way a CPU interacts with another part of the system through the
2704 caches goes, the memory system has to include 2780 caches goes, the memory system has to include the CPU's caches, and memory
2705 barriers for the most part act at the interfa 2781 barriers for the most part act at the interface between the CPU and its cache
2706 (memory barriers logically act on the dotted 2782 (memory barriers logically act on the dotted line in the following diagram):
2707 2783
2708 <--- CPU ---> : <-- 2784 <--- CPU ---> : <----------- Memory ----------->
2709 : 2785 :
2710 +--------+ +--------+ : +------ 2786 +--------+ +--------+ : +--------+ +-----------+
2711 | | | | : | 2787 | | | | : | | | | +--------+
2712 | CPU | | Memory | : | CPU 2788 | CPU | | Memory | : | CPU | | | | |
2713 | Core |--->| Access |----->| Cache 2789 | Core |--->| Access |----->| Cache |<-->| | | |
2714 | | | Queue | : | 2790 | | | Queue | : | | | |--->| Memory |
2715 | | | | : | 2791 | | | | : | | | | | |
2716 +--------+ +--------+ : +------ 2792 +--------+ +--------+ : +--------+ | | | |
2717 : 2793 : | Cache | +--------+
2718 : 2794 : | Coherency |
2719 : 2795 : | Mechanism | +--------+
2720 +--------+ +--------+ : +------ 2796 +--------+ +--------+ : +--------+ | | | |
2721 | | | | : | 2797 | | | | : | | | | | |
2722 | CPU | | Memory | : | CPU 2798 | CPU | | Memory | : | CPU | | |--->| Device |
2723 | Core |--->| Access |----->| Cache 2799 | Core |--->| Access |----->| Cache |<-->| | | |
2724 | | | Queue | : | 2800 | | | Queue | : | | | | | |
2725 | | | | : | 2801 | | | | : | | | | +--------+
2726 +--------+ +--------+ : +------ 2802 +--------+ +--------+ : +--------+ +-----------+
2727 : 2803 :
2728 : 2804 :
2729 2805
2730 Although any particular load or store may not 2806 Although any particular load or store may not actually appear outside of the
2731 CPU that issued it since it may have been sat 2807 CPU that issued it since it may have been satisfied within the CPU's own cache,
2732 it will still appear as if the full memory ac 2808 it will still appear as if the full memory access had taken place as far as the
2733 other CPUs are concerned since the cache cohe 2809 other CPUs are concerned since the cache coherency mechanisms will migrate the
2734 cacheline over to the accessing CPU and propa 2810 cacheline over to the accessing CPU and propagate the effects upon conflict.
2735 2811
2736 The CPU core may execute instructions in any 2812 The CPU core may execute instructions in any order it deems fit, provided the
2737 expected program causality appears to be main 2813 expected program causality appears to be maintained. Some of the instructions
2738 generate load and store operations which then 2814 generate load and store operations which then go into the queue of memory
2739 accesses to be performed. The core may place 2815 accesses to be performed. The core may place these in the queue in any order
2740 it wishes, and continue execution until it is 2816 it wishes, and continue execution until it is forced to wait for an instruction
2741 to complete. 2817 to complete.
2742 2818
2743 What memory barriers are concerned with is co 2819 What memory barriers are concerned with is controlling the order in which
2744 accesses cross from the CPU side of things to 2820 accesses cross from the CPU side of things to the memory side of things, and
2745 the order in which the effects are perceived 2821 the order in which the effects are perceived to happen by the other observers
2746 in the system. 2822 in the system.
2747 2823
2748 [!] Memory barriers are _not_ needed within a 2824 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2749 their own loads and stores as if they had hap 2825 their own loads and stores as if they had happened in program order.
2750 2826
2751 [!] MMIO or other device accesses may bypass 2827 [!] MMIO or other device accesses may bypass the cache system. This depends on
2752 the properties of the memory window through w 2828 the properties of the memory window through which devices are accessed and/or
2753 the use of any special device communication i 2829 the use of any special device communication instructions the CPU may have.
2754 2830
2755 2831
>> 2832 CACHE COHERENCY
>> 2833 ---------------
>> 2834
>> 2835 Life isn't quite as simple as it may appear above, however: for while the
>> 2836 caches are expected to be coherent, there's no guarantee that that coherency
>> 2837 will be ordered. This means that whilst changes made on one CPU will
>> 2838 eventually become visible on all CPUs, there's no guarantee that they will
>> 2839 become apparent in the same order on those other CPUs.
>> 2840
>> 2841
>> 2842 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
>> 2843 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
>> 2844
>> 2845 :
>> 2846 : +--------+
>> 2847 : +---------+ | |
>> 2848 +--------+ : +--->| Cache A |<------->| |
>> 2849 | | : | +---------+ | |
>> 2850 | CPU 1 |<---+ | |
>> 2851 | | : | +---------+ | |
>> 2852 +--------+ : +--->| Cache B |<------->| |
>> 2853 : +---------+ | |
>> 2854 : | Memory |
>> 2855 : +---------+ | System |
>> 2856 +--------+ : +--->| Cache C |<------->| |
>> 2857 | | : | +---------+ | |
>> 2858 | CPU 2 |<---+ | |
>> 2859 | | : | +---------+ | |
>> 2860 +--------+ : +--->| Cache D |<------->| |
>> 2861 : +---------+ | |
>> 2862 : +--------+
>> 2863 :
>> 2864
>> 2865 Imagine the system has the following properties:
>> 2866
>> 2867 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
>> 2868 resident in memory;
>> 2869
>> 2870 (*) an even-numbered cache line may be in cache B, cache D or it may still be
>> 2871 resident in memory;
>> 2872
>> 2873 (*) whilst the CPU core is interrogating one cache, the other cache may be
>> 2874 making use of the bus to access the rest of the system - perhaps to
>> 2875 displace a dirty cacheline or to do a speculative load;
>> 2876
>> 2877 (*) each cache has a queue of operations that need to be applied to that cache
>> 2878 to maintain coherency with the rest of the system;
>> 2879
>> 2880 (*) the coherency queue is not flushed by normal loads to lines already
>> 2881 present in the cache, even though the contents of the queue may
>> 2882 potentially affect those loads.
>> 2883
>> 2884 Imagine, then, that two writes are made on the first CPU, with a write barrier
>> 2885 between them to guarantee that they will appear to reach that CPU's caches in
>> 2886 the requisite order:
>> 2887
>> 2888 CPU 1 CPU 2 COMMENT
>> 2889 =============== =============== =======================================
>> 2890 u == 0, v == 1 and p == &u, q == &u
>> 2891 v = 2;
>> 2892 smp_wmb(); Make sure change to v is visible before
>> 2893 change to p
>> 2894 <A:modify v=2> v is now in cache A exclusively
>> 2895 p = &v;
>> 2896 <B:modify p=&v> p is now in cache B exclusively
>> 2897
>> 2898 The write memory barrier forces the other CPUs in the system to perceive that
>> 2899 the local CPU's caches have apparently been updated in the correct order. But
>> 2900 now imagine that the second CPU wants to read those values:
>> 2901
>> 2902 CPU 1 CPU 2 COMMENT
>> 2903 =============== =============== =======================================
>> 2904 ...
>> 2905 q = p;
>> 2906 x = *q;
>> 2907
>> 2908 The above pair of reads may then fail to happen in the expected order, as the
>> 2909 cacheline holding p may get updated in one of the second CPU's caches whilst
>> 2910 the update to the cacheline holding v is delayed in the other of the second
>> 2911 CPU's caches by some other cache event:
>> 2912
>> 2913 CPU 1 CPU 2 COMMENT
>> 2914 =============== =============== =======================================
>> 2915 u == 0, v == 1 and p == &u, q == &u
>> 2916 v = 2;
>> 2917 smp_wmb();
>> 2918 <A:modify v=2> <C:busy>
>> 2919 <C:queue v=2>
>> 2920 p = &v; q = p;
>> 2921 <D:request p>
>> 2922 <B:modify p=&v> <D:commit p=&v>
>> 2923 <D:read p>
>> 2924 x = *q;
>> 2925 <C:read *q> Reads from v before v updated in cache
>> 2926 <C:unbusy>
>> 2927 <C:commit v=2>
>> 2928
>> 2929 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
>> 2930 no guarantee that, without intervention, the order of update will be the same
>> 2931 as that committed on CPU 1.
>> 2932
>> 2933
>> 2934 To intervene, we need to interpolate a data dependency barrier or a read
>> 2935 barrier between the loads. This will force the cache to commit its coherency
>> 2936 queue before processing any further requests:
>> 2937
>> 2938 CPU 1 CPU 2 COMMENT
>> 2939 =============== =============== =======================================
>> 2940 u == 0, v == 1 and p == &u, q == &u
>> 2941 v = 2;
>> 2942 smp_wmb();
>> 2943 <A:modify v=2> <C:busy>
>> 2944 <C:queue v=2>
>> 2945 p = &v; q = p;
>> 2946 <D:request p>
>> 2947 <B:modify p=&v> <D:commit p=&v>
>> 2948 <D:read p>
>> 2949 smp_read_barrier_depends()
>> 2950 <C:unbusy>
>> 2951 <C:commit v=2>
>> 2952 x = *q;
>> 2953 <C:read *q> Reads from v after v updated in cache
>> 2954
>> 2955
>> 2956 This sort of problem can be encountered on DEC Alpha processors as they have a
>> 2957 split cache that improves performance by making better use of the data bus.
>> 2958 Whilst most CPUs do imply a data dependency barrier on the read when a memory
>> 2959 access depends on a read, not all do, so it may not be relied on.
>> 2960
>> 2961 Other CPUs may also have split caches, but must coordinate between the various
>> 2962 cachelets for normal memory accesses. The semantics of the Alpha removes the
>> 2963 need for coordination in the absence of memory barriers.
>> 2964
>> 2965
2756 CACHE COHERENCY VS DMA 2966 CACHE COHERENCY VS DMA
2757 ---------------------- 2967 ----------------------
2758 2968
2759 Not all systems maintain cache coherency with 2969 Not all systems maintain cache coherency with respect to devices doing DMA. In
2760 such cases, a device attempting DMA may obtai 2970 such cases, a device attempting DMA may obtain stale data from RAM because
2761 dirty cache lines may be resident in the cach 2971 dirty cache lines may be resident in the caches of various CPUs, and may not
2762 have been written back to RAM yet. To deal w 2972 have been written back to RAM yet. To deal with this, the appropriate part of
2763 the kernel must flush the overlapping bits of 2973 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2764 invalidate them as well). 2974 invalidate them as well).
2765 2975
2766 In addition, the data DMA'd to RAM by a devic 2976 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2767 cache lines being written back to RAM from a 2977 cache lines being written back to RAM from a CPU's cache after the device has
2768 installed its own data, or cache lines presen 2978 installed its own data, or cache lines present in the CPU's cache may simply
2769 obscure the fact that RAM has been updated, u 2979 obscure the fact that RAM has been updated, until at such time as the cacheline
2770 is discarded from the CPU's cache and reloade 2980 is discarded from the CPU's cache and reloaded. To deal with this, the
2771 appropriate part of the kernel must invalidat 2981 appropriate part of the kernel must invalidate the overlapping bits of the
2772 cache on each CPU. 2982 cache on each CPU.
2773 2983
2774 See Documentation/core-api/cachetlb.rst for m !! 2984 See Documentation/cachetlb.txt for more information on cache management.
2775 management. <<
2776 2985
2777 2986
2778 CACHE COHERENCY VS MMIO 2987 CACHE COHERENCY VS MMIO
2779 ----------------------- 2988 -----------------------
2780 2989
2781 Memory mapped I/O usually takes place through 2990 Memory mapped I/O usually takes place through memory locations that are part of
2782 a window in the CPU's memory space that has d 2991 a window in the CPU's memory space that has different properties assigned than
2783 the usual RAM directed window. 2992 the usual RAM directed window.
2784 2993
2785 Amongst these properties is usually the fact 2994 Amongst these properties is usually the fact that such accesses bypass the
2786 caching entirely and go directly to the devic 2995 caching entirely and go directly to the device buses. This means MMIO accesses
2787 may, in effect, overtake accesses to cached m 2996 may, in effect, overtake accesses to cached memory that were emitted earlier.
2788 A memory barrier isn't sufficient in such a c 2997 A memory barrier isn't sufficient in such a case, but rather the cache must be
2789 flushed between the cached memory write and t 2998 flushed between the cached memory write and the MMIO access if the two are in
2790 any way dependent. 2999 any way dependent.
2791 3000
2792 3001
2793 ========================= 3002 =========================
2794 THE THINGS CPUS GET UP TO 3003 THE THINGS CPUS GET UP TO
2795 ========================= 3004 =========================
2796 3005
2797 A programmer might take it for granted that t 3006 A programmer might take it for granted that the CPU will perform memory
2798 operations in exactly the order specified, so 3007 operations in exactly the order specified, so that if the CPU is, for example,
2799 given the following piece of code to execute: 3008 given the following piece of code to execute:
2800 3009
2801 a = READ_ONCE(*A); 3010 a = READ_ONCE(*A);
2802 WRITE_ONCE(*B, b); 3011 WRITE_ONCE(*B, b);
2803 c = READ_ONCE(*C); 3012 c = READ_ONCE(*C);
2804 d = READ_ONCE(*D); 3013 d = READ_ONCE(*D);
2805 WRITE_ONCE(*E, e); 3014 WRITE_ONCE(*E, e);
2806 3015
2807 they would then expect that the CPU will comp 3016 they would then expect that the CPU will complete the memory operation for each
2808 instruction before moving on to the next one, 3017 instruction before moving on to the next one, leading to a definite sequence of
2809 operations as seen by external observers in t 3018 operations as seen by external observers in the system:
2810 3019
2811 LOAD *A, STORE *B, LOAD *C, LOAD *D, 3020 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2812 3021
2813 3022
2814 Reality is, of course, much messier. With ma 3023 Reality is, of course, much messier. With many CPUs and compilers, the above
2815 assumption doesn't hold because: 3024 assumption doesn't hold because:
2816 3025
2817 (*) loads are more likely to need to be comp 3026 (*) loads are more likely to need to be completed immediately to permit
2818 execution progress, whereas stores can o 3027 execution progress, whereas stores can often be deferred without a
2819 problem; 3028 problem;
2820 3029
2821 (*) loads may be done speculatively, and the 3030 (*) loads may be done speculatively, and the result discarded should it prove
2822 to have been unnecessary; 3031 to have been unnecessary;
2823 3032
2824 (*) loads may be done speculatively, leading 3033 (*) loads may be done speculatively, leading to the result having been fetched
2825 at the wrong time in the expected sequen 3034 at the wrong time in the expected sequence of events;
2826 3035
2827 (*) the order of the memory accesses may be 3036 (*) the order of the memory accesses may be rearranged to promote better use
2828 of the CPU buses and caches; 3037 of the CPU buses and caches;
2829 3038
2830 (*) loads and stores may be combined to impr 3039 (*) loads and stores may be combined to improve performance when talking to
2831 memory or I/O hardware that can do batch 3040 memory or I/O hardware that can do batched accesses of adjacent locations,
2832 thus cutting down on transaction setup c 3041 thus cutting down on transaction setup costs (memory and PCI devices may
2833 both be able to do this); and 3042 both be able to do this); and
2834 3043
2835 (*) the CPU's data cache may affect the orde !! 3044 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2836 mechanisms may alleviate this - once the 3045 mechanisms may alleviate this - once the store has actually hit the cache
2837 - there's no guarantee that the coherenc 3046 - there's no guarantee that the coherency management will be propagated in
2838 order to other CPUs. 3047 order to other CPUs.
2839 3048
2840 So what another CPU, say, might actually obse 3049 So what another CPU, say, might actually observe from the above piece of code
2841 is: 3050 is:
2842 3051
2843 LOAD *A, ..., LOAD {*C,*D}, STORE *E, 3052 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2844 3053
2845 (Where "LOAD {*C,*D}" is a combined l 3054 (Where "LOAD {*C,*D}" is a combined load)
2846 3055
2847 3056
2848 However, it is guaranteed that a CPU will be 3057 However, it is guaranteed that a CPU will be self-consistent: it will see its
2849 _own_ accesses appear to be correctly ordered 3058 _own_ accesses appear to be correctly ordered, without the need for a memory
2850 barrier. For instance with the following cod 3059 barrier. For instance with the following code:
2851 3060
2852 U = READ_ONCE(*A); 3061 U = READ_ONCE(*A);
2853 WRITE_ONCE(*A, V); 3062 WRITE_ONCE(*A, V);
2854 WRITE_ONCE(*A, W); 3063 WRITE_ONCE(*A, W);
2855 X = READ_ONCE(*A); 3064 X = READ_ONCE(*A);
2856 WRITE_ONCE(*A, Y); 3065 WRITE_ONCE(*A, Y);
2857 Z = READ_ONCE(*A); 3066 Z = READ_ONCE(*A);
2858 3067
2859 and assuming no intervention by an external i 3068 and assuming no intervention by an external influence, it can be assumed that
2860 the final result will appear to be: 3069 the final result will appear to be:
2861 3070
2862 U == the original value of *A 3071 U == the original value of *A
2863 X == W 3072 X == W
2864 Z == Y 3073 Z == Y
2865 *A == Y 3074 *A == Y
2866 3075
2867 The code above may cause the CPU to generate 3076 The code above may cause the CPU to generate the full sequence of memory
2868 accesses: 3077 accesses:
2869 3078
2870 U=LOAD *A, STORE *A=V, STORE *A=W, X= 3079 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2871 3080
2872 in that order, but, without intervention, the 3081 in that order, but, without intervention, the sequence may have almost any
2873 combination of elements combined or discarded 3082 combination of elements combined or discarded, provided the program's view
2874 of the world remains consistent. Note that R 3083 of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2875 are -not- optional in the above example, as t 3084 are -not- optional in the above example, as there are architectures
2876 where a given CPU might reorder successive lo 3085 where a given CPU might reorder successive loads to the same location.
2877 On such architectures, READ_ONCE() and WRITE_ 3086 On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
2878 necessary to prevent this, for example, on It 3087 necessary to prevent this, for example, on Itanium the volatile casts
2879 used by READ_ONCE() and WRITE_ONCE() cause GC 3088 used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
2880 and st.rel instructions (respectively) that p 3089 and st.rel instructions (respectively) that prevent such reordering.
2881 3090
2882 The compiler may also combine, discard or def 3091 The compiler may also combine, discard or defer elements of the sequence before
2883 the CPU even sees them. 3092 the CPU even sees them.
2884 3093
2885 For instance: 3094 For instance:
2886 3095
2887 *A = V; 3096 *A = V;
2888 *A = W; 3097 *A = W;
2889 3098
2890 may be reduced to: 3099 may be reduced to:
2891 3100
2892 *A = W; 3101 *A = W;
2893 3102
2894 since, without either a write barrier or an W 3103 since, without either a write barrier or an WRITE_ONCE(), it can be
2895 assumed that the effect of the storage of V t 3104 assumed that the effect of the storage of V to *A is lost. Similarly:
2896 3105
2897 *A = Y; 3106 *A = Y;
2898 Z = *A; 3107 Z = *A;
2899 3108
2900 may, without a memory barrier or an READ_ONCE 3109 may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
2901 reduced to: 3110 reduced to:
2902 3111
2903 *A = Y; 3112 *A = Y;
2904 Z = Y; 3113 Z = Y;
2905 3114
2906 and the LOAD operation never appear outside o 3115 and the LOAD operation never appear outside of the CPU.
2907 3116
2908 3117
2909 AND THEN THERE'S THE ALPHA 3118 AND THEN THERE'S THE ALPHA
2910 -------------------------- 3119 --------------------------
2911 3120
2912 The DEC Alpha CPU is one of the most relaxed 3121 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2913 some versions of the Alpha CPU have a split d 3122 some versions of the Alpha CPU have a split data cache, permitting them to have
2914 two semantically-related cache lines updated 3123 two semantically-related cache lines updated at separate times. This is where
2915 the address-dependency barrier really becomes !! 3124 the data dependency barrier really becomes necessary as this synchronises both
2916 both caches with the memory coherence system, !! 3125 caches with the memory coherence system, thus making it seem like pointer
2917 changes vs new data occur in the right order. 3126 changes vs new data occur in the right order.
2918 3127
2919 The Alpha defines the Linux kernel's memory m !! 3128 The Alpha defines the Linux kernel's memory barrier model.
2920 the Linux kernel's addition of smp_mb() to RE !! 3129
2921 reduced its impact on the memory model. !! 3130 See the subsection on "Cache Coherency" above.
2922 3131
2923 3132
2924 VIRTUAL MACHINE GUESTS 3133 VIRTUAL MACHINE GUESTS
2925 ---------------------- 3134 ----------------------
2926 3135
2927 Guests running within virtual machines might 3136 Guests running within virtual machines might be affected by SMP effects even if
2928 the guest itself is compiled without SMP supp 3137 the guest itself is compiled without SMP support. This is an artifact of
2929 interfacing with an SMP host while running an 3138 interfacing with an SMP host while running an UP kernel. Using mandatory
2930 barriers for this use-case would be possible 3139 barriers for this use-case would be possible but is often suboptimal.
2931 3140
2932 To handle this case optimally, low-level virt 3141 To handle this case optimally, low-level virt_mb() etc macros are available.
2933 These have the same effect as smp_mb() etc wh 3142 These have the same effect as smp_mb() etc when SMP is enabled, but generate
2934 identical code for SMP and non-SMP systems. 3143 identical code for SMP and non-SMP systems. For example, virtual machine guests
2935 should use virt_mb() rather than smp_mb() whe 3144 should use virt_mb() rather than smp_mb() when synchronizing against a
2936 (possibly SMP) host. 3145 (possibly SMP) host.
2937 3146
2938 These are equivalent to smp_mb() etc counterp 3147 These are equivalent to smp_mb() etc counterparts in all other respects,
2939 in particular, they do not control MMIO effec 3148 in particular, they do not control MMIO effects: to control
2940 MMIO effects, use mandatory barriers. 3149 MMIO effects, use mandatory barriers.
2941 3150
2942 3151
2943 ============ 3152 ============
2944 EXAMPLE USES 3153 EXAMPLE USES
2945 ============ 3154 ============
2946 3155
2947 CIRCULAR BUFFERS 3156 CIRCULAR BUFFERS
2948 ---------------- 3157 ----------------
2949 3158
2950 Memory barriers can be used to implement circ 3159 Memory barriers can be used to implement circular buffering without the need
2951 of a lock to serialise the producer with the 3160 of a lock to serialise the producer with the consumer. See:
2952 3161
2953 Documentation/core-api/circular-buffe !! 3162 Documentation/circular-buffers.txt
2954 3163
2955 for details. 3164 for details.
2956 3165
2957 3166
2958 ========== 3167 ==========
2959 REFERENCES 3168 REFERENCES
2960 ========== 3169 ==========
2961 3170
2962 Alpha AXP Architecture Reference Manual, Seco 3171 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2963 Digital Press) 3172 Digital Press)
2964 Chapter 5.2: Physical Address Space C 3173 Chapter 5.2: Physical Address Space Characteristics
2965 Chapter 5.4: Caches and Write Buffers 3174 Chapter 5.4: Caches and Write Buffers
2966 Chapter 5.5: Data Sharing 3175 Chapter 5.5: Data Sharing
2967 Chapter 5.6: Read/Write Ordering 3176 Chapter 5.6: Read/Write Ordering
2968 3177
2969 AMD64 Architecture Programmer's Manual Volume 3178 AMD64 Architecture Programmer's Manual Volume 2: System Programming
2970 Chapter 7.1: Memory-Access Ordering 3179 Chapter 7.1: Memory-Access Ordering
2971 Chapter 7.4: Buffering and Combining 3180 Chapter 7.4: Buffering and Combining Memory Writes
2972 3181
2973 ARM Architecture Reference Manual (ARMv8, for <<
2974 Chapter B2: The AArch64 Application L <<
2975 <<
2976 IA-32 Intel Architecture Software Developer's 3182 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2977 System Programming Guide 3183 System Programming Guide
2978 Chapter 7.1: Locked Atomic Operations 3184 Chapter 7.1: Locked Atomic Operations
2979 Chapter 7.2: Memory Ordering 3185 Chapter 7.2: Memory Ordering
2980 Chapter 7.4: Serializing Instructions 3186 Chapter 7.4: Serializing Instructions
2981 3187
2982 The SPARC Architecture Manual, Version 9 3188 The SPARC Architecture Manual, Version 9
2983 Chapter 8: Memory Models 3189 Chapter 8: Memory Models
2984 Appendix D: Formal Specification of t 3190 Appendix D: Formal Specification of the Memory Models
2985 Appendix J: Programming with the Memo 3191 Appendix J: Programming with the Memory Models
2986 <<
2987 Storage in the PowerPC (Stone and Fitzgerald) <<
2988 3192
2989 UltraSPARC Programmer Reference Manual 3193 UltraSPARC Programmer Reference Manual
2990 Chapter 5: Memory Accesses and Cachea 3194 Chapter 5: Memory Accesses and Cacheability
2991 Chapter 15: Sparc-V9 Memory Models 3195 Chapter 15: Sparc-V9 Memory Models
2992 3196
2993 UltraSPARC III Cu User's Manual 3197 UltraSPARC III Cu User's Manual
2994 Chapter 9: Memory Models 3198 Chapter 9: Memory Models
2995 3199
2996 UltraSPARC IIIi Processor User's Manual 3200 UltraSPARC IIIi Processor User's Manual
2997 Chapter 8: Memory Models 3201 Chapter 8: Memory Models
2998 3202
2999 UltraSPARC Architecture 2005 3203 UltraSPARC Architecture 2005
3000 Chapter 9: Memory 3204 Chapter 9: Memory
3001 Appendix D: Formal Specifications of 3205 Appendix D: Formal Specifications of the Memory Models
3002 3206
3003 UltraSPARC T1 Supplement to the UltraSPARC Ar 3207 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3004 Chapter 8: Memory Models 3208 Chapter 8: Memory Models
3005 Appendix F: Caches and Cache Coherenc 3209 Appendix F: Caches and Cache Coherency
3006 3210
3007 Solaris Internals, Core Kernel Architecture, 3211 Solaris Internals, Core Kernel Architecture, p63-68:
3008 Chapter 3.3: Hardware Considerations 3212 Chapter 3.3: Hardware Considerations for Locks and
3009 Synchronization 3213 Synchronization
3010 3214
3011 Unix Systems for Modern Architectures, Symmet 3215 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3012 for Kernel Programmers: 3216 for Kernel Programmers:
3013 Chapter 13: Other Memory Models 3217 Chapter 13: Other Memory Models
3014 3218
3015 Intel Itanium Architecture Software Developer 3219 Intel Itanium Architecture Software Developer's Manual: Volume 1:
3016 Section 2.6: Speculation 3220 Section 2.6: Speculation
3017 Section 4.4: Memory Access 3221 Section 4.4: Memory Access
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