1 ===================== 1 ============================
2 LINUX KERNEL MEMORY B 2 LINUX KERNEL MEMORY BARRIERS
3 ===================== 3 ============================
4 4
5 By: David Howells <dhowells@redhat.com> 5 By: David Howells <dhowells@redhat.com>
6 Paul E. McKenney <paulmck@linux.ibm.com> !! 6 Paul E. McKenney <paulmck@linux.vnet.ibm.com>
7 Will Deacon <will.deacon@arm.com> <<
8 Peter Zijlstra <peterz@infradead.org> <<
9 7
10 ========== !! 8 Contents:
11 DISCLAIMER <<
12 ========== <<
13 <<
14 This document is not a specification; it is in <<
15 brevity) and unintentionally (due to being hum <<
16 meant as a guide to using the various memory b <<
17 in case of any doubt (and there are many) plea <<
18 resolved by referring to the formal memory con <<
19 documentation at tools/memory-model/. Neverth <<
20 model should be viewed as the collective opini <<
21 than as an infallible oracle. <<
22 <<
23 To repeat, this document is not a specificatio <<
24 hardware. <<
25 <<
26 The purpose of this document is twofold: <<
27 <<
28 (1) to specify the minimum functionality that <<
29 particular barrier, and <<
30 <<
31 (2) to provide a guide as to how to use the b <<
32 <<
33 Note that an architecture can provide more tha <<
34 for any particular barrier, but if the archite <<
35 that, that architecture is incorrect. <<
36 <<
37 Note also that it is possible that a barrier m <<
38 architecture because the way that arch works r <<
39 unnecessary in that case. <<
40 <<
41 <<
42 ======== <<
43 CONTENTS <<
44 ======== <<
45 9
46 (*) Abstract memory access model. 10 (*) Abstract memory access model.
47 11
48 - Device operations. 12 - Device operations.
49 - Guarantees. 13 - Guarantees.
50 14
51 (*) What are memory barriers? 15 (*) What are memory barriers?
52 16
53 - Varieties of memory barrier. 17 - Varieties of memory barrier.
54 - What may not be assumed about memory ba 18 - What may not be assumed about memory barriers?
55 - Address-dependency barriers (historical !! 19 - Data dependency barriers.
56 - Control dependencies. 20 - Control dependencies.
57 - SMP barrier pairing. 21 - SMP barrier pairing.
58 - Examples of memory barrier sequences. 22 - Examples of memory barrier sequences.
59 - Read memory barriers vs load speculatio 23 - Read memory barriers vs load speculation.
60 - Multicopy atomicity. !! 24 - Transitivity
61 25
62 (*) Explicit kernel barriers. 26 (*) Explicit kernel barriers.
63 27
64 - Compiler barrier. 28 - Compiler barrier.
65 - CPU memory barriers. 29 - CPU memory barriers.
>> 30 - MMIO write barrier.
66 31
67 (*) Implicit kernel memory barriers. 32 (*) Implicit kernel memory barriers.
68 33
69 - Lock acquisition functions. !! 34 - Locking functions.
70 - Interrupt disabling functions. 35 - Interrupt disabling functions.
71 - Sleep and wake-up functions. 36 - Sleep and wake-up functions.
72 - Miscellaneous functions. 37 - Miscellaneous functions.
73 38
74 (*) Inter-CPU acquiring barrier effects. !! 39 (*) Inter-CPU locking barrier effects.
75 40
76 - Acquires vs memory accesses. !! 41 - Locks vs memory accesses.
>> 42 - Locks vs I/O accesses.
77 43
78 (*) Where are memory barriers needed? 44 (*) Where are memory barriers needed?
79 45
80 - Interprocessor interaction. 46 - Interprocessor interaction.
81 - Atomic operations. 47 - Atomic operations.
82 - Accessing devices. 48 - Accessing devices.
83 - Interrupts. 49 - Interrupts.
84 50
85 (*) Kernel I/O barrier effects. 51 (*) Kernel I/O barrier effects.
86 52
87 (*) Assumed minimum execution ordering model. 53 (*) Assumed minimum execution ordering model.
88 54
89 (*) The effects of the cpu cache. 55 (*) The effects of the cpu cache.
90 56
91 - Cache coherency. 57 - Cache coherency.
92 - Cache coherency vs DMA. 58 - Cache coherency vs DMA.
93 - Cache coherency vs MMIO. 59 - Cache coherency vs MMIO.
94 60
95 (*) The things CPUs get up to. 61 (*) The things CPUs get up to.
96 62
97 - And then there's the Alpha. 63 - And then there's the Alpha.
98 - Virtual Machine Guests. <<
99 64
100 (*) Example uses. 65 (*) Example uses.
101 66
102 - Circular buffers. 67 - Circular buffers.
103 68
104 (*) References. 69 (*) References.
105 70
106 71
107 ============================ 72 ============================
108 ABSTRACT MEMORY ACCESS MODEL 73 ABSTRACT MEMORY ACCESS MODEL
109 ============================ 74 ============================
110 75
111 Consider the following abstract model of the s 76 Consider the following abstract model of the system:
112 77
113 : : 78 : :
114 : : 79 : :
115 : : 80 : :
116 +-------+ : +--------+ : 81 +-------+ : +--------+ : +-------+
117 | | : | | : 82 | | : | | : | |
118 | | : | | : 83 | | : | | : | |
119 | CPU 1 |<----->| Memory |<--- 84 | CPU 1 |<----->| Memory |<----->| CPU 2 |
120 | | : | | : 85 | | : | | : | |
121 | | : | | : 86 | | : | | : | |
122 +-------+ : +--------+ : 87 +-------+ : +--------+ : +-------+
123 ^ : ^ : 88 ^ : ^ : ^
124 | : | : 89 | : | : |
125 | : | : 90 | : | : |
126 | : v : 91 | : v : |
127 | : +--------+ : 92 | : +--------+ : |
128 | : | | : 93 | : | | : |
129 | : | | : 94 | : | | : |
130 +---------->| Device |<--- 95 +---------->| Device |<----------+
131 : | | : 96 : | | :
132 : | | : 97 : | | :
133 : +--------+ : 98 : +--------+ :
134 : : 99 : :
135 100
136 Each CPU executes a program that generates mem 101 Each CPU executes a program that generates memory access operations. In the
137 abstract CPU, memory operation ordering is ver 102 abstract CPU, memory operation ordering is very relaxed, and a CPU may actually
138 perform the memory operations in any order it 103 perform the memory operations in any order it likes, provided program causality
139 appears to be maintained. Similarly, the comp 104 appears to be maintained. Similarly, the compiler may also arrange the
140 instructions it emits in any order it likes, p 105 instructions it emits in any order it likes, provided it doesn't affect the
141 apparent operation of the program. 106 apparent operation of the program.
142 107
143 So in the above diagram, the effects of the me 108 So in the above diagram, the effects of the memory operations performed by a
144 CPU are perceived by the rest of the system as 109 CPU are perceived by the rest of the system as the operations cross the
145 interface between the CPU and rest of the syst 110 interface between the CPU and rest of the system (the dotted lines).
146 111
147 112
148 For example, consider the following sequence o 113 For example, consider the following sequence of events:
149 114
150 CPU 1 CPU 2 115 CPU 1 CPU 2
151 =============== =============== 116 =============== ===============
152 { A == 1; B == 2 } 117 { A == 1; B == 2 }
153 A = 3; x = B; 118 A = 3; x = B;
154 B = 4; y = A; 119 B = 4; y = A;
155 120
156 The set of accesses as seen by the memory syst 121 The set of accesses as seen by the memory system in the middle can be arranged
157 in 24 different combinations: 122 in 24 different combinations:
158 123
159 STORE A=3, STORE B=4, y=LOAD 124 STORE A=3, STORE B=4, y=LOAD A->3, x=LOAD B->4
160 STORE A=3, STORE B=4, x=LOAD 125 STORE A=3, STORE B=4, x=LOAD B->4, y=LOAD A->3
161 STORE A=3, y=LOAD A->3, STORE 126 STORE A=3, y=LOAD A->3, STORE B=4, x=LOAD B->4
162 STORE A=3, y=LOAD A->3, x=LOAD 127 STORE A=3, y=LOAD A->3, x=LOAD B->2, STORE B=4
163 STORE A=3, x=LOAD B->2, STORE 128 STORE A=3, x=LOAD B->2, STORE B=4, y=LOAD A->3
164 STORE A=3, x=LOAD B->2, y=LOAD 129 STORE A=3, x=LOAD B->2, y=LOAD A->3, STORE B=4
165 STORE B=4, STORE A=3, y=LOAD 130 STORE B=4, STORE A=3, y=LOAD A->3, x=LOAD B->4
166 STORE B=4, ... 131 STORE B=4, ...
167 ... 132 ...
168 133
169 and can thus result in four different combinat 134 and can thus result in four different combinations of values:
170 135
171 x == 2, y == 1 136 x == 2, y == 1
172 x == 2, y == 3 137 x == 2, y == 3
173 x == 4, y == 1 138 x == 4, y == 1
174 x == 4, y == 3 139 x == 4, y == 3
175 140
176 141
177 Furthermore, the stores committed by a CPU to 142 Furthermore, the stores committed by a CPU to the memory system may not be
178 perceived by the loads made by another CPU in 143 perceived by the loads made by another CPU in the same order as the stores were
179 committed. 144 committed.
180 145
181 146
182 As a further example, consider this sequence o 147 As a further example, consider this sequence of events:
183 148
184 CPU 1 CPU 2 149 CPU 1 CPU 2
185 =============== =============== 150 =============== ===============
186 { A == 1, B == 2, C == 3, P == &A, Q = !! 151 { A == 1, B == 2, C = 3, P == &A, Q == &C }
187 B = 4; Q = P; 152 B = 4; Q = P;
188 P = &B; D = *Q; !! 153 P = &B D = *Q;
189 154
190 There is an obvious address dependency here, a !! 155 There is an obvious data dependency here, as the value loaded into D depends on
191 on the address retrieved from P by CPU 2. At !! 156 the address retrieved from P by CPU 2. At the end of the sequence, any of the
192 the following results are possible: !! 157 following results are possible:
193 158
194 (Q == &A) and (D == 1) 159 (Q == &A) and (D == 1)
195 (Q == &B) and (D == 2) 160 (Q == &B) and (D == 2)
196 (Q == &B) and (D == 4) 161 (Q == &B) and (D == 4)
197 162
198 Note that CPU 2 will never try and load C into 163 Note that CPU 2 will never try and load C into D because the CPU will load P
199 into Q before issuing the load of *Q. 164 into Q before issuing the load of *Q.
200 165
201 166
202 DEVICE OPERATIONS 167 DEVICE OPERATIONS
203 ----------------- 168 -----------------
204 169
205 Some devices present their control interfaces 170 Some devices present their control interfaces as collections of memory
206 locations, but the order in which the control 171 locations, but the order in which the control registers are accessed is very
207 important. For instance, imagine an ethernet 172 important. For instance, imagine an ethernet card with a set of internal
208 registers that are accessed through an address 173 registers that are accessed through an address port register (A) and a data
209 port register (D). To read internal register 174 port register (D). To read internal register 5, the following code might then
210 be used: 175 be used:
211 176
212 *A = 5; 177 *A = 5;
213 x = *D; 178 x = *D;
214 179
215 but this might show up as either of the follow 180 but this might show up as either of the following two sequences:
216 181
217 STORE *A = 5, x = LOAD *D 182 STORE *A = 5, x = LOAD *D
218 x = LOAD *D, STORE *A = 5 183 x = LOAD *D, STORE *A = 5
219 184
220 the second of which will almost certainly resu 185 the second of which will almost certainly result in a malfunction, since it set
221 the address _after_ attempting to read the reg 186 the address _after_ attempting to read the register.
222 187
223 188
224 GUARANTEES 189 GUARANTEES
225 ---------- 190 ----------
226 191
227 There are some minimal guarantees that may be 192 There are some minimal guarantees that may be expected of a CPU:
228 193
229 (*) On any given CPU, dependent memory access 194 (*) On any given CPU, dependent memory accesses will be issued in order, with
230 respect to itself. This means that for: 195 respect to itself. This means that for:
231 196
232 Q = READ_ONCE(P); D = READ_ONCE(*Q); !! 197 WRITE_ONCE(Q, P); smp_read_barrier_depends(); D = READ_ONCE(*Q);
233 198
234 the CPU will issue the following memory o 199 the CPU will issue the following memory operations:
235 200
236 Q = LOAD P, D = LOAD *Q 201 Q = LOAD P, D = LOAD *Q
237 202
238 and always in that order. However, on DE !! 203 and always in that order. On most systems, smp_read_barrier_depends()
239 emits a memory-barrier instruction, so th !! 204 does nothing, but it is required for DEC Alpha. The READ_ONCE()
240 instead issue the following memory operat !! 205 and WRITE_ONCE() are required to prevent compiler mischief. Please
241 !! 206 note that you should normally use something like rcu_dereference()
242 Q = LOAD P, MEMORY_BARRIER, D = LOAD * !! 207 instead of open-coding smp_read_barrier_depends().
243 <<
244 Whether on DEC Alpha or not, the READ_ONC <<
245 mischief. <<
246 208
247 (*) Overlapping loads and stores within a par 209 (*) Overlapping loads and stores within a particular CPU will appear to be
248 ordered within that CPU. This means that 210 ordered within that CPU. This means that for:
249 211
250 a = READ_ONCE(*X); WRITE_ONCE(*X, b); 212 a = READ_ONCE(*X); WRITE_ONCE(*X, b);
251 213
252 the CPU will only issue the following seq 214 the CPU will only issue the following sequence of memory operations:
253 215
254 a = LOAD *X, STORE *X = b 216 a = LOAD *X, STORE *X = b
255 217
256 And for: 218 And for:
257 219
258 WRITE_ONCE(*X, c); d = READ_ONCE(*X); 220 WRITE_ONCE(*X, c); d = READ_ONCE(*X);
259 221
260 the CPU will only issue: 222 the CPU will only issue:
261 223
262 STORE *X = c, d = LOAD *X 224 STORE *X = c, d = LOAD *X
263 225
264 (Loads and stores overlap if they are tar 226 (Loads and stores overlap if they are targeted at overlapping pieces of
265 memory). 227 memory).
266 228
267 And there are a number of things that _must_ o 229 And there are a number of things that _must_ or _must_not_ be assumed:
268 230
269 (*) It _must_not_ be assumed that the compile 231 (*) It _must_not_ be assumed that the compiler will do what you want
270 with memory references that are not prote 232 with memory references that are not protected by READ_ONCE() and
271 WRITE_ONCE(). Without them, the compiler 233 WRITE_ONCE(). Without them, the compiler is within its rights to
272 do all sorts of "creative" transformation 234 do all sorts of "creative" transformations, which are covered in
273 the COMPILER BARRIER section. !! 235 the Compiler Barrier section.
274 236
275 (*) It _must_not_ be assumed that independent 237 (*) It _must_not_ be assumed that independent loads and stores will be issued
276 in the order given. This means that for: 238 in the order given. This means that for:
277 239
278 X = *A; Y = *B; *D = Z; 240 X = *A; Y = *B; *D = Z;
279 241
280 we may get any of the following sequences 242 we may get any of the following sequences:
281 243
282 X = LOAD *A, Y = LOAD *B, STORE *D = 244 X = LOAD *A, Y = LOAD *B, STORE *D = Z
283 X = LOAD *A, STORE *D = Z, Y = LOAD * 245 X = LOAD *A, STORE *D = Z, Y = LOAD *B
284 Y = LOAD *B, X = LOAD *A, STORE *D = 246 Y = LOAD *B, X = LOAD *A, STORE *D = Z
285 Y = LOAD *B, STORE *D = Z, X = LOAD * 247 Y = LOAD *B, STORE *D = Z, X = LOAD *A
286 STORE *D = Z, X = LOAD *A, Y = LOAD * 248 STORE *D = Z, X = LOAD *A, Y = LOAD *B
287 STORE *D = Z, Y = LOAD *B, X = LOAD * 249 STORE *D = Z, Y = LOAD *B, X = LOAD *A
288 250
289 (*) It _must_ be assumed that overlapping mem 251 (*) It _must_ be assumed that overlapping memory accesses may be merged or
290 discarded. This means that for: 252 discarded. This means that for:
291 253
292 X = *A; Y = *(A + 4); 254 X = *A; Y = *(A + 4);
293 255
294 we may get any one of the following seque 256 we may get any one of the following sequences:
295 257
296 X = LOAD *A; Y = LOAD *(A + 4); 258 X = LOAD *A; Y = LOAD *(A + 4);
297 Y = LOAD *(A + 4); X = LOAD *A; 259 Y = LOAD *(A + 4); X = LOAD *A;
298 {X, Y} = LOAD {*A, *(A + 4) }; 260 {X, Y} = LOAD {*A, *(A + 4) };
299 261
300 And for: 262 And for:
301 263
302 *A = X; *(A + 4) = Y; 264 *A = X; *(A + 4) = Y;
303 265
304 we may get any of: 266 we may get any of:
305 267
306 STORE *A = X; STORE *(A + 4) = Y; 268 STORE *A = X; STORE *(A + 4) = Y;
307 STORE *(A + 4) = Y; STORE *A = X; 269 STORE *(A + 4) = Y; STORE *A = X;
308 STORE {*A, *(A + 4) } = {X, Y}; 270 STORE {*A, *(A + 4) } = {X, Y};
309 271
310 And there are anti-guarantees: 272 And there are anti-guarantees:
311 273
312 (*) These guarantees do not apply to bitfield 274 (*) These guarantees do not apply to bitfields, because compilers often
313 generate code to modify these using non-a 275 generate code to modify these using non-atomic read-modify-write
314 sequences. Do not attempt to use bitfiel 276 sequences. Do not attempt to use bitfields to synchronize parallel
315 algorithms. 277 algorithms.
316 278
317 (*) Even in cases where bitfields are protect 279 (*) Even in cases where bitfields are protected by locks, all fields
318 in a given bitfield must be protected by 280 in a given bitfield must be protected by one lock. If two fields
319 in a given bitfield are protected by diff 281 in a given bitfield are protected by different locks, the compiler's
320 non-atomic read-modify-write sequences ca 282 non-atomic read-modify-write sequences can cause an update to one
321 field to corrupt the value of an adjacent 283 field to corrupt the value of an adjacent field.
322 284
323 (*) These guarantees apply only to properly a 285 (*) These guarantees apply only to properly aligned and sized scalar
324 variables. "Properly sized" currently me 286 variables. "Properly sized" currently means variables that are
325 the same size as "char", "short", "int" a 287 the same size as "char", "short", "int" and "long". "Properly
326 aligned" means the natural alignment, thu 288 aligned" means the natural alignment, thus no constraints for
327 "char", two-byte alignment for "short", f 289 "char", two-byte alignment for "short", four-byte alignment for
328 "int", and either four-byte or eight-byte 290 "int", and either four-byte or eight-byte alignment for "long",
329 on 32-bit and 64-bit systems, respectivel 291 on 32-bit and 64-bit systems, respectively. Note that these
330 guarantees were introduced into the C11 s 292 guarantees were introduced into the C11 standard, so beware when
331 using older pre-C11 compilers (for exampl 293 using older pre-C11 compilers (for example, gcc 4.6). The portion
332 of the standard containing this guarantee 294 of the standard containing this guarantee is Section 3.14, which
333 defines "memory location" as follows: 295 defines "memory location" as follows:
334 296
335 memory location 297 memory location
336 either an object of scalar typ 298 either an object of scalar type, or a maximal sequence
337 of adjacent bit-fields all hav 299 of adjacent bit-fields all having nonzero width
338 300
339 NOTE 1: Two threads of executi 301 NOTE 1: Two threads of execution can update and access
340 separate memory locations with 302 separate memory locations without interfering with
341 each other. 303 each other.
342 304
343 NOTE 2: A bit-field and an adj 305 NOTE 2: A bit-field and an adjacent non-bit-field member
344 are in separate memory locatio 306 are in separate memory locations. The same applies
345 to two bit-fields, if one is d 307 to two bit-fields, if one is declared inside a nested
346 structure declaration and the 308 structure declaration and the other is not, or if the two
347 are separated by a zero-length 309 are separated by a zero-length bit-field declaration,
348 or if they are separated by a 310 or if they are separated by a non-bit-field member
349 declaration. It is not safe to 311 declaration. It is not safe to concurrently update two
350 bit-fields in the same structu 312 bit-fields in the same structure if all members declared
351 between them are also bit-fiel 313 between them are also bit-fields, no matter what the
352 sizes of those intervening bit 314 sizes of those intervening bit-fields happen to be.
353 315
354 316
355 ========================= 317 =========================
356 WHAT ARE MEMORY BARRIERS? 318 WHAT ARE MEMORY BARRIERS?
357 ========================= 319 =========================
358 320
359 As can be seen above, independent memory opera 321 As can be seen above, independent memory operations are effectively performed
360 in random order, but this can be a problem for 322 in random order, but this can be a problem for CPU-CPU interaction and for I/O.
361 What is required is some way of intervening to 323 What is required is some way of intervening to instruct the compiler and the
362 CPU to restrict the order. 324 CPU to restrict the order.
363 325
364 Memory barriers are such interventions. They 326 Memory barriers are such interventions. They impose a perceived partial
365 ordering over the memory operations on either 327 ordering over the memory operations on either side of the barrier.
366 328
367 Such enforcement is important because the CPUs 329 Such enforcement is important because the CPUs and other devices in a system
368 can use a variety of tricks to improve perform 330 can use a variety of tricks to improve performance, including reordering,
369 deferral and combination of memory operations; 331 deferral and combination of memory operations; speculative loads; speculative
370 branch prediction and various types of caching 332 branch prediction and various types of caching. Memory barriers are used to
371 override or suppress these tricks, allowing th 333 override or suppress these tricks, allowing the code to sanely control the
372 interaction of multiple CPUs and/or devices. 334 interaction of multiple CPUs and/or devices.
373 335
374 336
375 VARIETIES OF MEMORY BARRIER 337 VARIETIES OF MEMORY BARRIER
376 --------------------------- 338 ---------------------------
377 339
378 Memory barriers come in four basic varieties: 340 Memory barriers come in four basic varieties:
379 341
380 (1) Write (or store) memory barriers. 342 (1) Write (or store) memory barriers.
381 343
382 A write memory barrier gives a guarantee 344 A write memory barrier gives a guarantee that all the STORE operations
383 specified before the barrier will appear 345 specified before the barrier will appear to happen before all the STORE
384 operations specified after the barrier wi 346 operations specified after the barrier with respect to the other
385 components of the system. 347 components of the system.
386 348
387 A write barrier is a partial ordering on 349 A write barrier is a partial ordering on stores only; it is not required
388 to have any effect on loads. 350 to have any effect on loads.
389 351
390 A CPU can be viewed as committing a seque 352 A CPU can be viewed as committing a sequence of store operations to the
391 memory system as time progresses. All st !! 353 memory system as time progresses. All stores before a write barrier will
392 will occur _before_ all the stores after !! 354 occur in the sequence _before_ all the stores after the write barrier.
>> 355
>> 356 [!] Note that write barriers should normally be paired with read or data
>> 357 dependency barriers; see the "SMP barrier pairing" subsection.
393 358
394 [!] Note that write barriers should norma <<
395 address-dependency barriers; see the "SMP <<
396 359
>> 360 (2) Data dependency barriers.
397 361
398 (2) Address-dependency barriers (historical). !! 362 A data dependency barrier is a weaker form of read barrier. In the case
399 [!] This section is marked as HISTORICAL: !! 363 where two loads are performed such that the second depends on the result
400 smp_read_barrier_depends() macro, the sem !! 364 of the first (eg: the first load retrieves the address to which the second
401 implicit in all marked accesses. For mor !! 365 load will be directed), a data dependency barrier would be required to
402 including how compiler transformations ca !! 366 make sure that the target of the second load is updated before the address
403 dependencies, see Documentation/RCU/rcu_d !! 367 obtained by the first load is accessed.
404 !! 368
405 An address-dependency barrier is a weaker !! 369 A data dependency barrier is a partial ordering on interdependent loads
406 case where two loads are performed such t !! 370 only; it is not required to have any effect on stores, independent loads
407 result of the first (eg: the first load r !! 371 or overlapping loads.
408 the second load will be directed), an add <<
409 be required to make sure that the target <<
410 after the address obtained by the first l <<
411 <<
412 An address-dependency barrier is a partia <<
413 loads only; it is not required to have an <<
414 loads or overlapping loads. <<
415 372
416 As mentioned in (1), the other CPUs in th 373 As mentioned in (1), the other CPUs in the system can be viewed as
417 committing sequences of stores to the mem 374 committing sequences of stores to the memory system that the CPU being
418 considered can then perceive. An address !! 375 considered can then perceive. A data dependency barrier issued by the CPU
419 the CPU under consideration guarantees th !! 376 under consideration guarantees that for any load preceding it, if that
420 if that load touches one of a sequence of !! 377 load touches one of a sequence of stores from another CPU, then by the
421 by the time the barrier completes, the ef !! 378 time the barrier completes, the effects of all the stores prior to that
422 that touched by the load will be percepti !! 379 touched by the load will be perceptible to any loads issued after the data
423 the address-dependency barrier. !! 380 dependency barrier.
424 381
425 See the "Examples of memory barrier seque 382 See the "Examples of memory barrier sequences" subsection for diagrams
426 showing the ordering constraints. 383 showing the ordering constraints.
427 384
428 [!] Note that the first load really has t !! 385 [!] Note that the first load really has to have a _data_ dependency and
429 not a control dependency. If the address 386 not a control dependency. If the address for the second load is dependent
430 on the first load, but the dependency is 387 on the first load, but the dependency is through a conditional rather than
431 actually loading the address itself, then 388 actually loading the address itself, then it's a _control_ dependency and
432 a full read barrier or better is required 389 a full read barrier or better is required. See the "Control dependencies"
433 subsection for more information. 390 subsection for more information.
434 391
435 [!] Note that address-dependency barriers !! 392 [!] Note that data dependency barriers should normally be paired with
436 write barriers; see the "SMP barrier pair 393 write barriers; see the "SMP barrier pairing" subsection.
437 394
438 [!] Kernel release v5.9 removed kernel AP <<
439 dependency barriers. Nowadays, APIs for <<
440 variables such as READ_ONCE() and rcu_der <<
441 address-dependency barriers. <<
442 395
443 (3) Read (or load) memory barriers. 396 (3) Read (or load) memory barriers.
444 397
445 A read barrier is an address-dependency b !! 398 A read barrier is a data dependency barrier plus a guarantee that all the
446 the LOAD operations specified before the !! 399 LOAD operations specified before the barrier will appear to happen before
447 before all the LOAD operations specified !! 400 all the LOAD operations specified after the barrier with respect to the
448 the other components of the system. !! 401 other components of the system.
449 402
450 A read barrier is a partial ordering on l 403 A read barrier is a partial ordering on loads only; it is not required to
451 have any effect on stores. 404 have any effect on stores.
452 405
453 Read memory barriers imply address-depend !! 406 Read memory barriers imply data dependency barriers, and so can substitute
454 substitute for them. !! 407 for them.
455 408
456 [!] Note that read barriers should normal 409 [!] Note that read barriers should normally be paired with write barriers;
457 see the "SMP barrier pairing" subsection. 410 see the "SMP barrier pairing" subsection.
458 411
459 412
460 (4) General memory barriers. 413 (4) General memory barriers.
461 414
462 A general memory barrier gives a guarante 415 A general memory barrier gives a guarantee that all the LOAD and STORE
463 operations specified before the barrier w 416 operations specified before the barrier will appear to happen before all
464 the LOAD and STORE operations specified a 417 the LOAD and STORE operations specified after the barrier with respect to
465 the other components of the system. 418 the other components of the system.
466 419
467 A general memory barrier is a partial ord 420 A general memory barrier is a partial ordering over both loads and stores.
468 421
469 General memory barriers imply both read a 422 General memory barriers imply both read and write memory barriers, and so
470 can substitute for either. 423 can substitute for either.
471 424
472 425
473 And a couple of implicit varieties: 426 And a couple of implicit varieties:
474 427
475 (5) ACQUIRE operations. 428 (5) ACQUIRE operations.
476 429
477 This acts as a one-way permeable barrier. 430 This acts as a one-way permeable barrier. It guarantees that all memory
478 operations after the ACQUIRE operation wi 431 operations after the ACQUIRE operation will appear to happen after the
479 ACQUIRE operation with respect to the oth 432 ACQUIRE operation with respect to the other components of the system.
480 ACQUIRE operations include LOCK operation !! 433 ACQUIRE operations include LOCK operations and smp_load_acquire()
481 and smp_cond_load_acquire() operations. !! 434 operations.
482 435
483 Memory operations that occur before an AC 436 Memory operations that occur before an ACQUIRE operation may appear to
484 happen after it completes. 437 happen after it completes.
485 438
486 An ACQUIRE operation should almost always 439 An ACQUIRE operation should almost always be paired with a RELEASE
487 operation. 440 operation.
488 441
489 442
490 (6) RELEASE operations. 443 (6) RELEASE operations.
491 444
492 This also acts as a one-way permeable bar 445 This also acts as a one-way permeable barrier. It guarantees that all
493 memory operations before the RELEASE oper 446 memory operations before the RELEASE operation will appear to happen
494 before the RELEASE operation with respect 447 before the RELEASE operation with respect to the other components of the
495 system. RELEASE operations include UNLOCK 448 system. RELEASE operations include UNLOCK operations and
496 smp_store_release() operations. 449 smp_store_release() operations.
497 450
498 Memory operations that occur after a RELE 451 Memory operations that occur after a RELEASE operation may appear to
499 happen before it completes. 452 happen before it completes.
500 453
501 The use of ACQUIRE and RELEASE operations 454 The use of ACQUIRE and RELEASE operations generally precludes the need
502 for other sorts of memory barrier. In ad !! 455 for other sorts of memory barrier (but note the exceptions mentioned in
503 -not- guaranteed to act as a full memory !! 456 the subsection "MMIO write barrier"). In addition, a RELEASE+ACQUIRE
504 ACQUIRE on a given variable, all memory a !! 457 pair is -not- guaranteed to act as a full memory barrier. However, after
>> 458 an ACQUIRE on a given variable, all memory accesses preceding any prior
505 RELEASE on that same variable are guarant 459 RELEASE on that same variable are guaranteed to be visible. In other
506 words, within a given variable's critical 460 words, within a given variable's critical section, all accesses of all
507 previous critical sections for that varia 461 previous critical sections for that variable are guaranteed to have
508 completed. 462 completed.
509 463
510 This means that ACQUIRE acts as a minimal 464 This means that ACQUIRE acts as a minimal "acquire" operation and
511 RELEASE acts as a minimal "release" opera 465 RELEASE acts as a minimal "release" operation.
512 466
513 A subset of the atomic operations described in <<
514 RELEASE variants in addition to fully-ordered <<
515 semantics) definitions. For compound atomics <<
516 store, ACQUIRE semantics apply only to the loa <<
517 only to the store portion of the operation. <<
518 467
519 Memory barriers are only required where there' 468 Memory barriers are only required where there's a possibility of interaction
520 between two CPUs or between a CPU and a device 469 between two CPUs or between a CPU and a device. If it can be guaranteed that
521 there won't be any such interaction in any par 470 there won't be any such interaction in any particular piece of code, then
522 memory barriers are unnecessary in that piece 471 memory barriers are unnecessary in that piece of code.
523 472
524 473
525 Note that these are the _minimum_ guarantees. 474 Note that these are the _minimum_ guarantees. Different architectures may give
526 more substantial guarantees, but they may _not 475 more substantial guarantees, but they may _not_ be relied upon outside of arch
527 specific code. 476 specific code.
528 477
529 478
530 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS? 479 WHAT MAY NOT BE ASSUMED ABOUT MEMORY BARRIERS?
531 ---------------------------------------------- 480 ----------------------------------------------
532 481
533 There are certain things that the Linux kernel 482 There are certain things that the Linux kernel memory barriers do not guarantee:
534 483
535 (*) There is no guarantee that any of the mem 484 (*) There is no guarantee that any of the memory accesses specified before a
536 memory barrier will be _complete_ by the 485 memory barrier will be _complete_ by the completion of a memory barrier
537 instruction; the barrier can be considere 486 instruction; the barrier can be considered to draw a line in that CPU's
538 access queue that accesses of the appropr 487 access queue that accesses of the appropriate type may not cross.
539 488
540 (*) There is no guarantee that issuing a memo 489 (*) There is no guarantee that issuing a memory barrier on one CPU will have
541 any direct effect on another CPU or any o 490 any direct effect on another CPU or any other hardware in the system. The
542 indirect effect will be the order in whic 491 indirect effect will be the order in which the second CPU sees the effects
543 of the first CPU's accesses occur, but se 492 of the first CPU's accesses occur, but see the next point:
544 493
545 (*) There is no guarantee that a CPU will see 494 (*) There is no guarantee that a CPU will see the correct order of effects
546 from a second CPU's accesses, even _if_ t 495 from a second CPU's accesses, even _if_ the second CPU uses a memory
547 barrier, unless the first CPU _also_ uses 496 barrier, unless the first CPU _also_ uses a matching memory barrier (see
548 the subsection on "SMP Barrier Pairing"). 497 the subsection on "SMP Barrier Pairing").
549 498
550 (*) There is no guarantee that some interveni 499 (*) There is no guarantee that some intervening piece of off-the-CPU
551 hardware[*] will not reorder the memory a 500 hardware[*] will not reorder the memory accesses. CPU cache coherency
552 mechanisms should propagate the indirect 501 mechanisms should propagate the indirect effects of a memory barrier
553 between CPUs, but might not do so in orde 502 between CPUs, but might not do so in order.
554 503
555 [*] For information on bus mastering D 504 [*] For information on bus mastering DMA and coherency please read:
556 505
557 Documentation/driver-api/pci/pci.r !! 506 Documentation/PCI/pci.txt
558 Documentation/core-api/dma-api-how !! 507 Documentation/DMA-API-HOWTO.txt
559 Documentation/core-api/dma-api.rst !! 508 Documentation/DMA-API.txt
560 509
561 510
562 ADDRESS-DEPENDENCY BARRIERS (HISTORICAL) !! 511 DATA DEPENDENCY BARRIERS
563 ---------------------------------------- !! 512 ------------------------
564 [!] This section is marked as HISTORICAL: it c <<
565 smp_read_barrier_depends() macro, the semantic <<
566 in all marked accesses. For more up-to-date i <<
567 how compiler transformations can sometimes bre <<
568 see Documentation/RCU/rcu_dereference.rst. <<
569 <<
570 As of v4.15 of the Linux kernel, an smp_mb() w <<
571 DEC Alpha, which means that about the only peo <<
572 to this section are those working on DEC Alpha <<
573 and those working on READ_ONCE() itself. For <<
574 those who are interested in the history, here <<
575 address-dependency barriers. <<
576 <<
577 [!] While address dependencies are observed in <<
578 load-to-store relations, address-dependency ba <<
579 for load-to-store situations. <<
580 513
581 The requirement of address-dependency barriers !! 514 The usage requirements of data dependency barriers are a little subtle, and
582 it's not always obvious that they're needed. 515 it's not always obvious that they're needed. To illustrate, consider the
583 following sequence of events: 516 following sequence of events:
584 517
585 CPU 1 CPU 2 518 CPU 1 CPU 2
586 =============== =============== 519 =============== ===============
587 { A == 1, B == 2, C == 3, P == &A, Q = !! 520 { A == 1, B == 2, C = 3, P == &A, Q == &C }
588 B = 4; 521 B = 4;
589 <write barrier> 522 <write barrier>
590 WRITE_ONCE(P, &B); !! 523 WRITE_ONCE(P, &B)
591 Q = READ_ONCE_OL !! 524 Q = READ_ONCE(P);
592 D = *Q; 525 D = *Q;
593 526
594 [!] READ_ONCE_OLD() corresponds to READ_ONCE() !! 527 There's a clear data dependency here, and it would seem that by the end of the
595 doesn't imply an address-dependency barrier. !! 528 sequence, Q must be either &A or &B, and that:
596 <<
597 There's a clear address dependency here, and i <<
598 the sequence, Q must be either &A or &B, and t <<
599 529
600 (Q == &A) implies (D == 1) 530 (Q == &A) implies (D == 1)
601 (Q == &B) implies (D == 4) 531 (Q == &B) implies (D == 4)
602 532
603 But! CPU 2's perception of P may be updated _ 533 But! CPU 2's perception of P may be updated _before_ its perception of B, thus
604 leading to the following situation: 534 leading to the following situation:
605 535
606 (Q == &B) and (D == 2) ???? 536 (Q == &B) and (D == 2) ????
607 537
608 While this may seem like a failure of coherenc !! 538 Whilst this may seem like a failure of coherency or causality maintenance, it
609 isn't, and this behaviour can be observed on c 539 isn't, and this behaviour can be observed on certain real CPUs (such as the DEC
610 Alpha). 540 Alpha).
611 541
612 To deal with this, READ_ONCE() provides an imp !! 542 To deal with this, a data dependency barrier or better must be inserted
613 since kernel release v4.15: !! 543 between the address load and the data load:
614 544
615 CPU 1 CPU 2 545 CPU 1 CPU 2
616 =============== =============== 546 =============== ===============
617 { A == 1, B == 2, C == 3, P == &A, Q = !! 547 { A == 1, B == 2, C = 3, P == &A, Q == &C }
618 B = 4; 548 B = 4;
619 <write barrier> 549 <write barrier>
620 WRITE_ONCE(P, &B); 550 WRITE_ONCE(P, &B);
621 Q = READ_ONCE(P) 551 Q = READ_ONCE(P);
622 <implicit addres !! 552 <data dependency barrier>
623 D = *Q; 553 D = *Q;
624 554
625 This enforces the occurrence of one of the two 555 This enforces the occurrence of one of the two implications, and prevents the
626 third possibility from arising. 556 third possibility from arising.
627 557
628 <<
629 [!] Note that this extremely counterintuitive 558 [!] Note that this extremely counterintuitive situation arises most easily on
630 machines with split caches, so that, for examp 559 machines with split caches, so that, for example, one cache bank processes
631 even-numbered cache lines and the other bank p 560 even-numbered cache lines and the other bank processes odd-numbered cache
632 lines. The pointer P might be stored in an od 561 lines. The pointer P might be stored in an odd-numbered cache line, and the
633 variable B might be stored in an even-numbered 562 variable B might be stored in an even-numbered cache line. Then, if the
634 even-numbered bank of the reading CPU's cache 563 even-numbered bank of the reading CPU's cache is extremely busy while the
635 odd-numbered bank is idle, one can see the new 564 odd-numbered bank is idle, one can see the new value of the pointer P (&B),
636 but the old value of the variable B (2). 565 but the old value of the variable B (2).
637 566
638 567
639 An address-dependency barrier is not required !! 568 Another example of where data dependency barriers might be required is where a
640 because the CPUs that the Linux kernel support !! 569 number is read from memory and then used to calculate the index for an array
641 are certain (1) that the write will actually h !! 570 access:
642 the write, and (3) of the value to be written. <<
643 But please carefully read the "CONTROL DEPENDE <<
644 Documentation/RCU/rcu_dereference.rst file: T <<
645 dependencies in a great many highly creative w <<
646 571
647 CPU 1 CPU 2 572 CPU 1 CPU 2
648 =============== =============== 573 =============== ===============
649 { A == 1, B == 2, C = 3, P == &A, Q == !! 574 { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 }
650 B = 4; !! 575 M[1] = 4;
651 <write barrier> 576 <write barrier>
652 WRITE_ONCE(P, &B); !! 577 WRITE_ONCE(P, 1);
653 Q = READ_ONCE_OL !! 578 Q = READ_ONCE(P);
654 WRITE_ONCE(*Q, 5 !! 579 <data dependency barrier>
655 !! 580 D = M[Q];
656 Therefore, no address-dependency barrier is re <<
657 Q with the store into *Q. In other words, thi <<
658 even without an implicit address-dependency ba <<
659 <<
660 (Q == &B) && (B == 4) <<
661 <<
662 Please note that this pattern should be rare. <<
663 of dependency ordering is to -prevent- writes <<
664 with the expensive cache misses associated wit <<
665 can be used to record rare error conditions an <<
666 naturally occurring ordering prevents such rec <<
667 <<
668 <<
669 Note well that the ordering provided by an add <<
670 the CPU containing it. See the section on "Mu <<
671 more information. <<
672 581
673 582
674 The address-dependency barrier is very importa !! 583 The data dependency barrier is very important to the RCU system,
675 for example. See rcu_assign_pointer() and rcu 584 for example. See rcu_assign_pointer() and rcu_dereference() in
676 include/linux/rcupdate.h. This permits the cu 585 include/linux/rcupdate.h. This permits the current target of an RCU'd
677 pointer to be replaced with a new modified tar 586 pointer to be replaced with a new modified target, without the replacement
678 target appearing to be incompletely initialise 587 target appearing to be incompletely initialised.
679 588
680 See also the subsection on "Cache Coherency" f 589 See also the subsection on "Cache Coherency" for a more thorough example.
681 590
682 591
683 CONTROL DEPENDENCIES 592 CONTROL DEPENDENCIES
684 -------------------- 593 --------------------
685 594
686 Control dependencies can be a bit tricky becau <<
687 not understand them. The purpose of this sect <<
688 the compiler's ignorance from breaking your co <<
689 <<
690 A load-load control dependency requires a full 595 A load-load control dependency requires a full read memory barrier, not
691 simply an (implicit) address-dependency barrie !! 596 simply a data dependency barrier to make it work correctly. Consider the
692 Consider the following bit of code: !! 597 following bit of code:
693 598
694 q = READ_ONCE(a); 599 q = READ_ONCE(a);
695 <implicit address-dependency barrier> <<
696 if (q) { 600 if (q) {
697 /* BUG: No address dependency! !! 601 <data dependency barrier> /* BUG: No data dependency!!! */
698 p = READ_ONCE(b); 602 p = READ_ONCE(b);
699 } 603 }
700 604
701 This will not have the desired effect because !! 605 This will not have the desired effect because there is no actual data
702 dependency, but rather a control dependency th 606 dependency, but rather a control dependency that the CPU may short-circuit
703 by attempting to predict the outcome in advanc 607 by attempting to predict the outcome in advance, so that other CPUs see
704 the load from b as having happened before the !! 608 the load from b as having happened before the load from a. In such a
705 what's actually required is: !! 609 case what's actually required is:
706 610
707 q = READ_ONCE(a); 611 q = READ_ONCE(a);
708 if (q) { 612 if (q) {
709 <read barrier> 613 <read barrier>
710 p = READ_ONCE(b); 614 p = READ_ONCE(b);
711 } 615 }
712 616
713 However, stores are not speculated. This mean 617 However, stores are not speculated. This means that ordering -is- provided
714 for load-store control dependencies, as in the 618 for load-store control dependencies, as in the following example:
715 619
716 q = READ_ONCE(a); 620 q = READ_ONCE(a);
717 if (q) { 621 if (q) {
718 WRITE_ONCE(b, 1); !! 622 WRITE_ONCE(b, p);
719 } 623 }
720 624
721 Control dependencies pair normally with other !! 625 Control dependencies pair normally with other types of barriers. That
722 That said, please note that neither READ_ONCE( !! 626 said, please note that READ_ONCE() is not optional! Without the
723 are optional! Without the READ_ONCE(), the com !! 627 READ_ONCE(), the compiler might combine the load from 'a' with other
724 load from 'a' with other loads from 'a'. With !! 628 loads from 'a', and the store to 'b' with other stores to 'b', with
725 the compiler might combine the store to 'b' wi !! 629 possible highly counterintuitive effects on ordering.
726 Either can result in highly counterintuitive e <<
727 630
728 Worse yet, if the compiler is able to prove (s 631 Worse yet, if the compiler is able to prove (say) that the value of
729 variable 'a' is always non-zero, it would be w 632 variable 'a' is always non-zero, it would be well within its rights
730 to optimize the original example by eliminatin 633 to optimize the original example by eliminating the "if" statement
731 as follows: 634 as follows:
732 635
733 q = a; 636 q = a;
734 b = 1; /* BUG: Compiler and CPU can b !! 637 b = p; /* BUG: Compiler and CPU can both reorder!!! */
735 638
736 So don't leave out the READ_ONCE(). 639 So don't leave out the READ_ONCE().
737 640
738 It is tempting to try to enforce ordering on i 641 It is tempting to try to enforce ordering on identical stores on both
739 branches of the "if" statement as follows: 642 branches of the "if" statement as follows:
740 643
741 q = READ_ONCE(a); 644 q = READ_ONCE(a);
742 if (q) { 645 if (q) {
743 barrier(); 646 barrier();
744 WRITE_ONCE(b, 1); !! 647 WRITE_ONCE(b, p);
745 do_something(); 648 do_something();
746 } else { 649 } else {
747 barrier(); 650 barrier();
748 WRITE_ONCE(b, 1); !! 651 WRITE_ONCE(b, p);
749 do_something_else(); 652 do_something_else();
750 } 653 }
751 654
752 Unfortunately, current compilers will transfor 655 Unfortunately, current compilers will transform this as follows at high
753 optimization levels: 656 optimization levels:
754 657
755 q = READ_ONCE(a); 658 q = READ_ONCE(a);
756 barrier(); 659 barrier();
757 WRITE_ONCE(b, 1); /* BUG: No ordering !! 660 WRITE_ONCE(b, p); /* BUG: No ordering vs. load from a!!! */
758 if (q) { 661 if (q) {
759 /* WRITE_ONCE(b, 1); -- moved !! 662 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
760 do_something(); 663 do_something();
761 } else { 664 } else {
762 /* WRITE_ONCE(b, 1); -- moved !! 665 /* WRITE_ONCE(b, p); -- moved up, BUG!!! */
763 do_something_else(); 666 do_something_else();
764 } 667 }
765 668
766 Now there is no conditional between the load f 669 Now there is no conditional between the load from 'a' and the store to
767 'b', which means that the CPU is within its ri 670 'b', which means that the CPU is within its rights to reorder them:
768 The conditional is absolutely required, and mu 671 The conditional is absolutely required, and must be present in the
769 assembly code even after all compiler optimiza 672 assembly code even after all compiler optimizations have been applied.
770 Therefore, if you need ordering in this exampl 673 Therefore, if you need ordering in this example, you need explicit
771 memory barriers, for example, smp_store_releas 674 memory barriers, for example, smp_store_release():
772 675
773 q = READ_ONCE(a); 676 q = READ_ONCE(a);
774 if (q) { 677 if (q) {
775 smp_store_release(&b, 1); !! 678 smp_store_release(&b, p);
776 do_something(); 679 do_something();
777 } else { 680 } else {
778 smp_store_release(&b, 1); !! 681 smp_store_release(&b, p);
779 do_something_else(); 682 do_something_else();
780 } 683 }
781 684
782 In contrast, without explicit memory barriers, 685 In contrast, without explicit memory barriers, two-legged-if control
783 ordering is guaranteed only when the stores di 686 ordering is guaranteed only when the stores differ, for example:
784 687
785 q = READ_ONCE(a); 688 q = READ_ONCE(a);
786 if (q) { 689 if (q) {
787 WRITE_ONCE(b, 1); !! 690 WRITE_ONCE(b, p);
788 do_something(); 691 do_something();
789 } else { 692 } else {
790 WRITE_ONCE(b, 2); !! 693 WRITE_ONCE(b, r);
791 do_something_else(); 694 do_something_else();
792 } 695 }
793 696
794 The initial READ_ONCE() is still required to p 697 The initial READ_ONCE() is still required to prevent the compiler from
795 proving the value of 'a'. 698 proving the value of 'a'.
796 699
797 In addition, you need to be careful what you d 700 In addition, you need to be careful what you do with the local variable 'q',
798 otherwise the compiler might be able to guess 701 otherwise the compiler might be able to guess the value and again remove
799 the needed conditional. For example: 702 the needed conditional. For example:
800 703
801 q = READ_ONCE(a); 704 q = READ_ONCE(a);
802 if (q % MAX) { 705 if (q % MAX) {
803 WRITE_ONCE(b, 1); !! 706 WRITE_ONCE(b, p);
804 do_something(); 707 do_something();
805 } else { 708 } else {
806 WRITE_ONCE(b, 2); !! 709 WRITE_ONCE(b, r);
807 do_something_else(); 710 do_something_else();
808 } 711 }
809 712
810 If MAX is defined to be 1, then the compiler k 713 If MAX is defined to be 1, then the compiler knows that (q % MAX) is
811 equal to zero, in which case the compiler is w 714 equal to zero, in which case the compiler is within its rights to
812 transform the above code into the following: 715 transform the above code into the following:
813 716
814 q = READ_ONCE(a); 717 q = READ_ONCE(a);
815 WRITE_ONCE(b, 2); !! 718 WRITE_ONCE(b, p);
816 do_something_else(); 719 do_something_else();
817 720
818 Given this transformation, the CPU is not requ 721 Given this transformation, the CPU is not required to respect the ordering
819 between the load from variable 'a' and the sto 722 between the load from variable 'a' and the store to variable 'b'. It is
820 tempting to add a barrier(), but this does not 723 tempting to add a barrier(), but this does not help. The conditional
821 is gone, and the barrier won't bring it back. 724 is gone, and the barrier won't bring it back. Therefore, if you are
822 relying on this ordering, you should make sure 725 relying on this ordering, you should make sure that MAX is greater than
823 one, perhaps as follows: 726 one, perhaps as follows:
824 727
825 q = READ_ONCE(a); 728 q = READ_ONCE(a);
826 BUILD_BUG_ON(MAX <= 1); /* Order load 729 BUILD_BUG_ON(MAX <= 1); /* Order load from a with store to b. */
827 if (q % MAX) { 730 if (q % MAX) {
828 WRITE_ONCE(b, 1); !! 731 WRITE_ONCE(b, p);
829 do_something(); 732 do_something();
830 } else { 733 } else {
831 WRITE_ONCE(b, 2); !! 734 WRITE_ONCE(b, r);
832 do_something_else(); 735 do_something_else();
833 } 736 }
834 737
835 Please note once again that the stores to 'b' 738 Please note once again that the stores to 'b' differ. If they were
836 identical, as noted earlier, the compiler coul 739 identical, as noted earlier, the compiler could pull this store outside
837 of the 'if' statement. 740 of the 'if' statement.
838 741
839 You must also be careful not to rely too much 742 You must also be careful not to rely too much on boolean short-circuit
840 evaluation. Consider this example: 743 evaluation. Consider this example:
841 744
842 q = READ_ONCE(a); 745 q = READ_ONCE(a);
843 if (q || 1 > 0) 746 if (q || 1 > 0)
844 WRITE_ONCE(b, 1); 747 WRITE_ONCE(b, 1);
845 748
846 Because the first condition cannot fault and t 749 Because the first condition cannot fault and the second condition is
847 always true, the compiler can transform this e 750 always true, the compiler can transform this example as following,
848 defeating control dependency: 751 defeating control dependency:
849 752
850 q = READ_ONCE(a); 753 q = READ_ONCE(a);
851 WRITE_ONCE(b, 1); 754 WRITE_ONCE(b, 1);
852 755
853 This example underscores the need to ensure th 756 This example underscores the need to ensure that the compiler cannot
854 out-guess your code. More generally, although 757 out-guess your code. More generally, although READ_ONCE() does force
855 the compiler to actually emit code for a given 758 the compiler to actually emit code for a given load, it does not force
856 the compiler to use the results. 759 the compiler to use the results.
857 760
858 In addition, control dependencies apply only t !! 761 Finally, control dependencies do -not- provide transitivity. This is
859 else-clause of the if-statement in question. !! 762 demonstrated by two related examples, with the initial values of
860 not necessarily apply to code following the if !! 763 x and y both being zero:
861 !! 764
862 q = READ_ONCE(a); !! 765 CPU 0 CPU 1
863 if (q) { !! 766 ======================= =======================
864 WRITE_ONCE(b, 1); !! 767 r1 = READ_ONCE(x); r2 = READ_ONCE(y);
865 } else { !! 768 if (r1 > 0) if (r2 > 0)
866 WRITE_ONCE(b, 2); !! 769 WRITE_ONCE(y, 1); WRITE_ONCE(x, 1);
867 } !! 770
868 WRITE_ONCE(c, 1); /* BUG: No ordering !! 771 assert(!(r1 == 1 && r2 == 1));
869 !! 772
870 It is tempting to argue that there in fact is !! 773 The above two-CPU example will never trigger the assert(). However,
871 compiler cannot reorder volatile accesses and !! 774 if control dependencies guaranteed transitivity (which they do not),
872 the writes to 'b' with the condition. Unfortu !! 775 then adding the following CPU would guarantee a related assertion:
873 of reasoning, the compiler might compile the t !! 776
874 conditional-move instructions, as in this fanc !! 777 CPU 2
875 language: !! 778 =====================
876 !! 779 WRITE_ONCE(x, 2);
877 ld r1,a !! 780
878 cmp r1,$0 !! 781 assert(!(r1 == 2 && r2 == 1 && x == 2)); /* FAILS!!! */
879 cmov,ne r4,$1 !! 782
880 cmov,eq r4,$2 !! 783 But because control dependencies do -not- provide transitivity, the above
881 st r4,b !! 784 assertion can fail after the combined three-CPU example completes. If you
882 st $1,c !! 785 need the three-CPU example to provide ordering, you will need smp_mb()
883 !! 786 between the loads and stores in the CPU 0 and CPU 1 code fragments,
884 A weakly ordered CPU would have no dependency !! 787 that is, just before or just after the "if" statements. Furthermore,
885 from 'a' and the store to 'c'. The control de !! 788 the original two-CPU example is very fragile and should be avoided.
886 only to the pair of cmov instructions and the !! 789
887 In short, control dependencies apply only to t !! 790 These two examples are the LB and WWC litmus tests from this paper:
888 and else-clause of the if-statement in questio !! 791 http://www.cl.cam.ac.uk/users/pes20/ppc-supplemental/test6.pdf and this
889 invoked by those two clauses), not to code fol !! 792 site: https://www.cl.cam.ac.uk/~pes20/ppcmem/index.html.
890 <<
891 <<
892 Note well that the ordering provided by a cont <<
893 to the CPU containing it. See the section on <<
894 for more information. <<
895 <<
896 793
897 In summary: 794 In summary:
898 795
899 (*) Control dependencies can order prior loa 796 (*) Control dependencies can order prior loads against later stores.
900 However, they do -not- guarantee any oth 797 However, they do -not- guarantee any other sort of ordering:
901 Not prior loads against later loads, nor 798 Not prior loads against later loads, nor prior stores against
902 later anything. If you need these other 799 later anything. If you need these other forms of ordering,
903 use smp_rmb(), smp_wmb(), or, in the cas 800 use smp_rmb(), smp_wmb(), or, in the case of prior stores and
904 later loads, smp_mb(). 801 later loads, smp_mb().
905 802
906 (*) If both legs of the "if" statement begin !! 803 (*) If both legs of the "if" statement begin with identical stores
907 the same variable, then those stores mus !! 804 to the same variable, a barrier() statement is required at the
908 preceding both of them with smp_mb() or !! 805 beginning of each leg of the "if" statement.
909 to carry out the stores. Please note th <<
910 to use barrier() at beginning of each le <<
911 because, as shown by the example above, <<
912 destroy the control dependency while res <<
913 barrier() law. <<
914 806
915 (*) Control dependencies require at least on 807 (*) Control dependencies require at least one run-time conditional
916 between the prior load and the subsequen 808 between the prior load and the subsequent store, and this
917 conditional must involve the prior load. 809 conditional must involve the prior load. If the compiler is able
918 to optimize the conditional away, it wil 810 to optimize the conditional away, it will have also optimized
919 away the ordering. Careful use of READ_ 811 away the ordering. Careful use of READ_ONCE() and WRITE_ONCE()
920 can help to preserve the needed conditio 812 can help to preserve the needed conditional.
921 813
922 (*) Control dependencies require that the co 814 (*) Control dependencies require that the compiler avoid reordering the
923 dependency into nonexistence. Careful u 815 dependency into nonexistence. Careful use of READ_ONCE() or
924 atomic{,64}_read() can help to preserve 816 atomic{,64}_read() can help to preserve your control dependency.
925 Please see the COMPILER BARRIER section !! 817 Please see the Compiler Barrier section for more information.
926 <<
927 (*) Control dependencies apply only to the t <<
928 of the if-statement containing the contr <<
929 any functions that these two clauses cal <<
930 do -not- apply to code following the if- <<
931 control dependency. <<
932 818
933 (*) Control dependencies pair normally with 819 (*) Control dependencies pair normally with other types of barriers.
934 820
935 (*) Control dependencies do -not- provide mu !! 821 (*) Control dependencies do -not- provide transitivity. If you
936 need all the CPUs to see a given store a !! 822 need transitivity, use smp_mb().
937 <<
938 (*) Compilers do not understand control depe <<
939 your job to ensure that they do not brea <<
940 823
941 824
942 SMP BARRIER PAIRING 825 SMP BARRIER PAIRING
943 ------------------- 826 -------------------
944 827
945 When dealing with CPU-CPU interactions, certai 828 When dealing with CPU-CPU interactions, certain types of memory barrier should
946 always be paired. A lack of appropriate pairi 829 always be paired. A lack of appropriate pairing is almost certainly an error.
947 830
948 General barriers pair with each other, though 831 General barriers pair with each other, though they also pair with most
949 other types of barriers, albeit without multic !! 832 other types of barriers, albeit without transitivity. An acquire barrier
950 barrier pairs with a release barrier, but both !! 833 pairs with a release barrier, but both may also pair with other barriers,
951 barriers, including of course general barriers !! 834 including of course general barriers. A write barrier pairs with a data
952 with an address-dependency barrier, a control !! 835 dependency barrier, a control dependency, an acquire barrier, a release
953 a release barrier, a read barrier, or a genera !! 836 barrier, a read barrier, or a general barrier. Similarly a read barrier,
954 read barrier, control dependency, or an addres !! 837 control dependency, or a data dependency barrier pairs with a write
955 with a write barrier, an acquire barrier, a re !! 838 barrier, an acquire barrier, a release barrier, or a general barrier:
956 general barrier: <<
957 839
958 CPU 1 CPU 2 840 CPU 1 CPU 2
959 =============== =============== 841 =============== ===============
960 WRITE_ONCE(a, 1); 842 WRITE_ONCE(a, 1);
961 <write barrier> 843 <write barrier>
962 WRITE_ONCE(b, 2); x = READ_ONCE(b) 844 WRITE_ONCE(b, 2); x = READ_ONCE(b);
963 <read barrier> 845 <read barrier>
964 y = READ_ONCE(a) 846 y = READ_ONCE(a);
965 847
966 Or: 848 Or:
967 849
968 CPU 1 CPU 2 850 CPU 1 CPU 2
969 =============== ================ 851 =============== ===============================
970 a = 1; 852 a = 1;
971 <write barrier> 853 <write barrier>
972 WRITE_ONCE(b, &a); x = READ_ONCE(b) 854 WRITE_ONCE(b, &a); x = READ_ONCE(b);
973 <implicit addres !! 855 <data dependency barrier>
974 y = *x; 856 y = *x;
975 857
976 Or even: 858 Or even:
977 859
978 CPU 1 CPU 2 860 CPU 1 CPU 2
979 =============== ================ 861 =============== ===============================
980 r1 = READ_ONCE(y); 862 r1 = READ_ONCE(y);
981 <general barrier> 863 <general barrier>
982 WRITE_ONCE(x, 1); if (r2 = READ_ON !! 864 WRITE_ONCE(y, 1); if (r2 = READ_ONCE(x)) {
983 <implicit con 865 <implicit control dependency>
984 WRITE_ONCE(y, 866 WRITE_ONCE(y, 1);
985 } 867 }
986 868
987 assert(r1 == 0 || r2 == 0); 869 assert(r1 == 0 || r2 == 0);
988 870
989 Basically, the read barrier always has to be t 871 Basically, the read barrier always has to be there, even though it can be of
990 the "weaker" type. 872 the "weaker" type.
991 873
992 [!] Note that the stores before the write barr 874 [!] Note that the stores before the write barrier would normally be expected to
993 match the loads after the read barrier or the !! 875 match the loads after the read barrier or the data dependency barrier, and vice
994 vice versa: !! 876 versa:
995 877
996 CPU 1 CP 878 CPU 1 CPU 2
997 =================== == 879 =================== ===================
998 WRITE_ONCE(a, 1); }---- --->{ v 880 WRITE_ONCE(a, 1); }---- --->{ v = READ_ONCE(c);
999 WRITE_ONCE(b, 2); } \ / { w 881 WRITE_ONCE(b, 2); } \ / { w = READ_ONCE(d);
1000 <write barrier> \ < 882 <write barrier> \ <read barrier>
1001 WRITE_ONCE(c, 3); } / \ { x 883 WRITE_ONCE(c, 3); } / \ { x = READ_ONCE(a);
1002 WRITE_ONCE(d, 4); }---- --->{ y 884 WRITE_ONCE(d, 4); }---- --->{ y = READ_ONCE(b);
1003 885
1004 886
1005 EXAMPLES OF MEMORY BARRIER SEQUENCES 887 EXAMPLES OF MEMORY BARRIER SEQUENCES
1006 ------------------------------------ 888 ------------------------------------
1007 889
1008 Firstly, write barriers act as partial orderi 890 Firstly, write barriers act as partial orderings on store operations.
1009 Consider the following sequence of events: 891 Consider the following sequence of events:
1010 892
1011 CPU 1 893 CPU 1
1012 ======================= 894 =======================
1013 STORE A = 1 895 STORE A = 1
1014 STORE B = 2 896 STORE B = 2
1015 STORE C = 3 897 STORE C = 3
1016 <write barrier> 898 <write barrier>
1017 STORE D = 4 899 STORE D = 4
1018 STORE E = 5 900 STORE E = 5
1019 901
1020 This sequence of events is committed to the m 902 This sequence of events is committed to the memory coherence system in an order
1021 that the rest of the system might perceive as 903 that the rest of the system might perceive as the unordered set of { STORE A,
1022 STORE B, STORE C } all occurring before the u 904 STORE B, STORE C } all occurring before the unordered set of { STORE D, STORE E
1023 }: 905 }:
1024 906
1025 +-------+ : : 907 +-------+ : :
1026 | | +------+ 908 | | +------+
1027 | |------>| C=3 | } /\ 909 | |------>| C=3 | } /\
1028 | | : +------+ }----- 910 | | : +------+ }----- \ -----> Events perceptible to
1029 | | : | A=1 | } 911 | | : | A=1 | } \/ the rest of the system
1030 | | : +------+ } 912 | | : +------+ }
1031 | CPU 1 | : | B=2 | } 913 | CPU 1 | : | B=2 | }
1032 | | +------+ } 914 | | +------+ }
1033 | | wwwwwwwwwwwwwwww } <--- 915 | | wwwwwwwwwwwwwwww } <--- At this point the write barrier
1034 | | +------+ } 916 | | +------+ } requires all stores prior to the
1035 | | : | E=5 | } 917 | | : | E=5 | } barrier to be committed before
1036 | | : +------+ } 918 | | : +------+ } further stores may take place
1037 | |------>| D=4 | } 919 | |------>| D=4 | }
1038 | | +------+ 920 | | +------+
1039 +-------+ : : 921 +-------+ : :
1040 | 922 |
1041 | Sequence in whic 923 | Sequence in which stores are committed to the
1042 | memory system by 924 | memory system by CPU 1
1043 V 925 V
1044 926
1045 927
1046 Secondly, address-dependency barriers act as !! 928 Secondly, data dependency barriers act as partial orderings on data-dependent
1047 dependent loads. Consider the following sequ !! 929 loads. Consider the following sequence of events:
1048 930
1049 CPU 1 CPU 2 931 CPU 1 CPU 2
1050 ======================= ============= 932 ======================= =======================
1051 { B = 7; X = 9; Y = 8; C = &Y 933 { B = 7; X = 9; Y = 8; C = &Y }
1052 STORE A = 1 934 STORE A = 1
1053 STORE B = 2 935 STORE B = 2
1054 <write barrier> 936 <write barrier>
1055 STORE C = &B LOAD X 937 STORE C = &B LOAD X
1056 STORE D = 4 LOAD C (gets 938 STORE D = 4 LOAD C (gets &B)
1057 LOAD *C (read 939 LOAD *C (reads B)
1058 940
1059 Without intervention, CPU 2 may perceive the 941 Without intervention, CPU 2 may perceive the events on CPU 1 in some
1060 effectively random order, despite the write b 942 effectively random order, despite the write barrier issued by CPU 1:
1061 943
1062 +-------+ : : 944 +-------+ : : : :
1063 | | +------+ 945 | | +------+ +-------+ | Sequence of update
1064 | |------>| B=2 |----- - 946 | |------>| B=2 |----- --->| Y->8 | | of perception on
1065 | | : +------+ \ 947 | | : +------+ \ +-------+ | CPU 2
1066 | CPU 1 | : | A=1 | \ - 948 | CPU 1 | : | A=1 | \ --->| C->&Y | V
1067 | | +------+ | 949 | | +------+ | +-------+
1068 | | wwwwwwwwwwwwwwww | 950 | | wwwwwwwwwwwwwwww | : :
1069 | | +------+ | 951 | | +------+ | : :
1070 | | : | C=&B |--- | 952 | | : | C=&B |--- | : : +-------+
1071 | | : +------+ \ | 953 | | : +------+ \ | +-------+ | |
1072 | |------>| D=4 | --------- 954 | |------>| D=4 | ----------->| C->&B |------>| |
1073 | | +------+ | 955 | | +------+ | +-------+ | |
1074 +-------+ : : | 956 +-------+ : : | : : | |
1075 | 957 | : : | |
1076 | 958 | : : | CPU 2 |
1077 | 959 | +-------+ | |
1078 Apparently incorrect ---> | 960 Apparently incorrect ---> | | B->7 |------>| |
1079 perception of B (!) | 961 perception of B (!) | +-------+ | |
1080 | 962 | : : | |
1081 | 963 | +-------+ | |
1082 The load of X holds ---> \ 964 The load of X holds ---> \ | X->9 |------>| |
1083 up the maintenance \ 965 up the maintenance \ +-------+ | |
1084 of coherence of B --- 966 of coherence of B ----->| B->2 | +-------+
1085 967 +-------+
1086 968 : :
1087 969
1088 970
1089 In the above example, CPU 2 perceives that B 971 In the above example, CPU 2 perceives that B is 7, despite the load of *C
1090 (which would be B) coming after the LOAD of C 972 (which would be B) coming after the LOAD of C.
1091 973
1092 If, however, an address-dependency barrier we !! 974 If, however, a data dependency barrier were to be placed between the load of C
1093 of C and the load of *C (ie: B) on CPU 2: !! 975 and the load of *C (ie: B) on CPU 2:
1094 976
1095 CPU 1 CPU 2 977 CPU 1 CPU 2
1096 ======================= ============= 978 ======================= =======================
1097 { B = 7; X = 9; Y = 8; C = &Y 979 { B = 7; X = 9; Y = 8; C = &Y }
1098 STORE A = 1 980 STORE A = 1
1099 STORE B = 2 981 STORE B = 2
1100 <write barrier> 982 <write barrier>
1101 STORE C = &B LOAD X 983 STORE C = &B LOAD X
1102 STORE D = 4 LOAD C (gets 984 STORE D = 4 LOAD C (gets &B)
1103 <address-depe !! 985 <data dependency barrier>
1104 LOAD *C (read 986 LOAD *C (reads B)
1105 987
1106 then the following will occur: 988 then the following will occur:
1107 989
1108 +-------+ : : 990 +-------+ : : : :
1109 | | +------+ 991 | | +------+ +-------+
1110 | |------>| B=2 |----- - 992 | |------>| B=2 |----- --->| Y->8 |
1111 | | : +------+ \ 993 | | : +------+ \ +-------+
1112 | CPU 1 | : | A=1 | \ - 994 | CPU 1 | : | A=1 | \ --->| C->&Y |
1113 | | +------+ | 995 | | +------+ | +-------+
1114 | | wwwwwwwwwwwwwwww | 996 | | wwwwwwwwwwwwwwww | : :
1115 | | +------+ | 997 | | +------+ | : :
1116 | | : | C=&B |--- | 998 | | : | C=&B |--- | : : +-------+
1117 | | : +------+ \ | 999 | | : +------+ \ | +-------+ | |
1118 | |------>| D=4 | --------- 1000 | |------>| D=4 | ----------->| C->&B |------>| |
1119 | | +------+ | 1001 | | +------+ | +-------+ | |
1120 +-------+ : : | 1002 +-------+ : : | : : | |
1121 | 1003 | : : | |
1122 | 1004 | : : | CPU 2 |
1123 | 1005 | +-------+ | |
1124 | 1006 | | X->9 |------>| |
1125 | 1007 | +-------+ | |
1126 Makes sure all effects ---> \ a !! 1008 Makes sure all effects ---> \ ddddddddddddddddd | |
1127 prior to the store of C \ 1009 prior to the store of C \ +-------+ | |
1128 are perceptible to --- 1010 are perceptible to ----->| B->2 |------>| |
1129 subsequent loads 1011 subsequent loads +-------+ | |
1130 1012 : : +-------+
1131 1013
1132 1014
1133 And thirdly, a read barrier acts as a partial 1015 And thirdly, a read barrier acts as a partial order on loads. Consider the
1134 following sequence of events: 1016 following sequence of events:
1135 1017
1136 CPU 1 CPU 2 1018 CPU 1 CPU 2
1137 ======================= ============= 1019 ======================= =======================
1138 { A = 0, B = 9 } 1020 { A = 0, B = 9 }
1139 STORE A=1 1021 STORE A=1
1140 <write barrier> 1022 <write barrier>
1141 STORE B=2 1023 STORE B=2
1142 LOAD B 1024 LOAD B
1143 LOAD A 1025 LOAD A
1144 1026
1145 Without intervention, CPU 2 may then choose t 1027 Without intervention, CPU 2 may then choose to perceive the events on CPU 1 in
1146 some effectively random order, despite the wr 1028 some effectively random order, despite the write barrier issued by CPU 1:
1147 1029
1148 +-------+ : : 1030 +-------+ : : : :
1149 | | +------+ 1031 | | +------+ +-------+
1150 | |------>| A=1 |------ - 1032 | |------>| A=1 |------ --->| A->0 |
1151 | | +------+ \ 1033 | | +------+ \ +-------+
1152 | CPU 1 | wwwwwwwwwwwwwwww \ - 1034 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1153 | | +------+ | 1035 | | +------+ | +-------+
1154 | |------>| B=2 |--- | 1036 | |------>| B=2 |--- | : :
1155 | | +------+ \ | 1037 | | +------+ \ | : : +-------+
1156 +-------+ : : \ | 1038 +-------+ : : \ | +-------+ | |
1157 -------- 1039 ---------->| B->2 |------>| |
1158 | 1040 | +-------+ | CPU 2 |
1159 | 1041 | | A->0 |------>| |
1160 | 1042 | +-------+ | |
1161 | 1043 | : : +-------+
1162 \ 1044 \ : :
1163 \ 1045 \ +-------+
1164 -- 1046 ---->| A->1 |
1165 1047 +-------+
1166 1048 : :
1167 1049
1168 1050
1169 If, however, a read barrier were to be placed 1051 If, however, a read barrier were to be placed between the load of B and the
1170 load of A on CPU 2: 1052 load of A on CPU 2:
1171 1053
1172 CPU 1 CPU 2 1054 CPU 1 CPU 2
1173 ======================= ============= 1055 ======================= =======================
1174 { A = 0, B = 9 } 1056 { A = 0, B = 9 }
1175 STORE A=1 1057 STORE A=1
1176 <write barrier> 1058 <write barrier>
1177 STORE B=2 1059 STORE B=2
1178 LOAD B 1060 LOAD B
1179 <read barrier 1061 <read barrier>
1180 LOAD A 1062 LOAD A
1181 1063
1182 then the partial ordering imposed by CPU 1 wi 1064 then the partial ordering imposed by CPU 1 will be perceived correctly by CPU
1183 2: 1065 2:
1184 1066
1185 +-------+ : : 1067 +-------+ : : : :
1186 | | +------+ 1068 | | +------+ +-------+
1187 | |------>| A=1 |------ - 1069 | |------>| A=1 |------ --->| A->0 |
1188 | | +------+ \ 1070 | | +------+ \ +-------+
1189 | CPU 1 | wwwwwwwwwwwwwwww \ - 1071 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1190 | | +------+ | 1072 | | +------+ | +-------+
1191 | |------>| B=2 |--- | 1073 | |------>| B=2 |--- | : :
1192 | | +------+ \ | 1074 | | +------+ \ | : : +-------+
1193 +-------+ : : \ | 1075 +-------+ : : \ | +-------+ | |
1194 -------- 1076 ---------->| B->2 |------>| |
1195 | 1077 | +-------+ | CPU 2 |
1196 | 1078 | : : | |
1197 | 1079 | : : | |
1198 At this point the read ----> \ r 1080 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1199 barrier causes all effects \ 1081 barrier causes all effects \ +-------+ | |
1200 prior to the storage of B -- 1082 prior to the storage of B ---->| A->1 |------>| |
1201 to be perceptible to CPU 2 1083 to be perceptible to CPU 2 +-------+ | |
1202 1084 : : +-------+
1203 1085
1204 1086
1205 To illustrate this more completely, consider 1087 To illustrate this more completely, consider what could happen if the code
1206 contained a load of A either side of the read 1088 contained a load of A either side of the read barrier:
1207 1089
1208 CPU 1 CPU 2 1090 CPU 1 CPU 2
1209 ======================= ============= 1091 ======================= =======================
1210 { A = 0, B = 9 } 1092 { A = 0, B = 9 }
1211 STORE A=1 1093 STORE A=1
1212 <write barrier> 1094 <write barrier>
1213 STORE B=2 1095 STORE B=2
1214 LOAD B 1096 LOAD B
1215 LOAD A [first 1097 LOAD A [first load of A]
1216 <read barrier 1098 <read barrier>
1217 LOAD A [secon 1099 LOAD A [second load of A]
1218 1100
1219 Even though the two loads of A both occur aft 1101 Even though the two loads of A both occur after the load of B, they may both
1220 come up with different values: 1102 come up with different values:
1221 1103
1222 +-------+ : : 1104 +-------+ : : : :
1223 | | +------+ 1105 | | +------+ +-------+
1224 | |------>| A=1 |------ - 1106 | |------>| A=1 |------ --->| A->0 |
1225 | | +------+ \ 1107 | | +------+ \ +-------+
1226 | CPU 1 | wwwwwwwwwwwwwwww \ - 1108 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1227 | | +------+ | 1109 | | +------+ | +-------+
1228 | |------>| B=2 |--- | 1110 | |------>| B=2 |--- | : :
1229 | | +------+ \ | 1111 | | +------+ \ | : : +-------+
1230 +-------+ : : \ | 1112 +-------+ : : \ | +-------+ | |
1231 -------- 1113 ---------->| B->2 |------>| |
1232 | 1114 | +-------+ | CPU 2 |
1233 | 1115 | : : | |
1234 | 1116 | : : | |
1235 | 1117 | +-------+ | |
1236 | 1118 | | A->0 |------>| 1st |
1237 | 1119 | +-------+ | |
1238 At this point the read ----> \ r 1120 At this point the read ----> \ rrrrrrrrrrrrrrrrr | |
1239 barrier causes all effects \ 1121 barrier causes all effects \ +-------+ | |
1240 prior to the storage of B -- 1122 prior to the storage of B ---->| A->1 |------>| 2nd |
1241 to be perceptible to CPU 2 1123 to be perceptible to CPU 2 +-------+ | |
1242 1124 : : +-------+
1243 1125
1244 1126
1245 But it may be that the update to A from CPU 1 1127 But it may be that the update to A from CPU 1 becomes perceptible to CPU 2
1246 before the read barrier completes anyway: 1128 before the read barrier completes anyway:
1247 1129
1248 +-------+ : : 1130 +-------+ : : : :
1249 | | +------+ 1131 | | +------+ +-------+
1250 | |------>| A=1 |------ - 1132 | |------>| A=1 |------ --->| A->0 |
1251 | | +------+ \ 1133 | | +------+ \ +-------+
1252 | CPU 1 | wwwwwwwwwwwwwwww \ - 1134 | CPU 1 | wwwwwwwwwwwwwwww \ --->| B->9 |
1253 | | +------+ | 1135 | | +------+ | +-------+
1254 | |------>| B=2 |--- | 1136 | |------>| B=2 |--- | : :
1255 | | +------+ \ | 1137 | | +------+ \ | : : +-------+
1256 +-------+ : : \ | 1138 +-------+ : : \ | +-------+ | |
1257 -------- 1139 ---------->| B->2 |------>| |
1258 | 1140 | +-------+ | CPU 2 |
1259 | 1141 | : : | |
1260 \ 1142 \ : : | |
1261 \ 1143 \ +-------+ | |
1262 -- 1144 ---->| A->1 |------>| 1st |
1263 1145 +-------+ | |
1264 r 1146 rrrrrrrrrrrrrrrrr | |
1265 1147 +-------+ | |
1266 1148 | A->1 |------>| 2nd |
1267 1149 +-------+ | |
1268 1150 : : +-------+
1269 1151
1270 1152
1271 The guarantee is that the second load will al 1153 The guarantee is that the second load will always come up with A == 1 if the
1272 load of B came up with B == 2. No such guara 1154 load of B came up with B == 2. No such guarantee exists for the first load of
1273 A; that may come up with either A == 0 or A = 1155 A; that may come up with either A == 0 or A == 1.
1274 1156
1275 1157
1276 READ MEMORY BARRIERS VS LOAD SPECULATION 1158 READ MEMORY BARRIERS VS LOAD SPECULATION
1277 ---------------------------------------- 1159 ----------------------------------------
1278 1160
1279 Many CPUs speculate with loads: that is they 1161 Many CPUs speculate with loads: that is they see that they will need to load an
1280 item from memory, and they find a time where 1162 item from memory, and they find a time where they're not using the bus for any
1281 other loads, and so do the load in advance - 1163 other loads, and so do the load in advance - even though they haven't actually
1282 got to that point in the instruction executio 1164 got to that point in the instruction execution flow yet. This permits the
1283 actual load instruction to potentially comple 1165 actual load instruction to potentially complete immediately because the CPU
1284 already has the value to hand. 1166 already has the value to hand.
1285 1167
1286 It may turn out that the CPU didn't actually 1168 It may turn out that the CPU didn't actually need the value - perhaps because a
1287 branch circumvented the load - in which case 1169 branch circumvented the load - in which case it can discard the value or just
1288 cache it for later use. 1170 cache it for later use.
1289 1171
1290 Consider: 1172 Consider:
1291 1173
1292 CPU 1 CPU 2 1174 CPU 1 CPU 2
1293 ======================= ============= 1175 ======================= =======================
1294 LOAD B 1176 LOAD B
1295 DIVIDE 1177 DIVIDE } Divide instructions generally
1296 DIVIDE 1178 DIVIDE } take a long time to perform
1297 LOAD A 1179 LOAD A
1298 1180
1299 Which might appear as this: 1181 Which might appear as this:
1300 1182
1301 1183 : : +-------+
1302 1184 +-------+ | |
1303 - 1185 --->| B->2 |------>| |
1304 1186 +-------+ | CPU 2 |
1305 1187 : :DIVIDE | |
1306 1188 +-------+ | |
1307 The CPU being busy doing a ---> - 1189 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1308 division speculates on the 1190 division speculates on the +-------+ ~ | |
1309 LOAD of A 1191 LOAD of A : : ~ | |
1310 1192 : :DIVIDE | |
1311 1193 : : ~ | |
1312 Once the divisions are complete --> 1194 Once the divisions are complete --> : : ~-->| |
1313 the CPU can then perform the 1195 the CPU can then perform the : : | |
1314 LOAD with immediate effect 1196 LOAD with immediate effect : : +-------+
1315 1197
1316 1198
1317 Placing a read barrier or an address-dependen !! 1199 Placing a read barrier or a data dependency barrier just before the second
1318 load: 1200 load:
1319 1201
1320 CPU 1 CPU 2 1202 CPU 1 CPU 2
1321 ======================= ============= 1203 ======================= =======================
1322 LOAD B 1204 LOAD B
1323 DIVIDE 1205 DIVIDE
1324 DIVIDE 1206 DIVIDE
1325 <read barrier 1207 <read barrier>
1326 LOAD A 1208 LOAD A
1327 1209
1328 will force any value speculatively obtained t 1210 will force any value speculatively obtained to be reconsidered to an extent
1329 dependent on the type of barrier used. If th 1211 dependent on the type of barrier used. If there was no change made to the
1330 speculated memory location, then the speculat 1212 speculated memory location, then the speculated value will just be used:
1331 1213
1332 1214 : : +-------+
1333 1215 +-------+ | |
1334 - 1216 --->| B->2 |------>| |
1335 1217 +-------+ | CPU 2 |
1336 1218 : :DIVIDE | |
1337 1219 +-------+ | |
1338 The CPU being busy doing a ---> - 1220 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1339 division speculates on the 1221 division speculates on the +-------+ ~ | |
1340 LOAD of A 1222 LOAD of A : : ~ | |
1341 1223 : :DIVIDE | |
1342 1224 : : ~ | |
1343 1225 : : ~ | |
1344 r 1226 rrrrrrrrrrrrrrrr~ | |
1345 1227 : : ~ | |
1346 1228 : : ~-->| |
1347 1229 : : | |
1348 1230 : : +-------+
1349 1231
1350 1232
1351 but if there was an update or an invalidation 1233 but if there was an update or an invalidation from another CPU pending, then
1352 the speculation will be cancelled and the val 1234 the speculation will be cancelled and the value reloaded:
1353 1235
1354 1236 : : +-------+
1355 1237 +-------+ | |
1356 - 1238 --->| B->2 |------>| |
1357 1239 +-------+ | CPU 2 |
1358 1240 : :DIVIDE | |
1359 1241 +-------+ | |
1360 The CPU being busy doing a ---> - 1242 The CPU being busy doing a ---> --->| A->0 |~~~~ | |
1361 division speculates on the 1243 division speculates on the +-------+ ~ | |
1362 LOAD of A 1244 LOAD of A : : ~ | |
1363 1245 : :DIVIDE | |
1364 1246 : : ~ | |
1365 1247 : : ~ | |
1366 r 1248 rrrrrrrrrrrrrrrrr | |
1367 1249 +-------+ | |
1368 The speculation is discarded ---> - 1250 The speculation is discarded ---> --->| A->1 |------>| |
1369 and an updated value is 1251 and an updated value is +-------+ | |
1370 retrieved 1252 retrieved : : +-------+
1371 1253
1372 1254
1373 MULTICOPY ATOMICITY !! 1255 TRANSITIVITY
1374 -------------------- !! 1256 ------------
1375 1257
1376 Multicopy atomicity is a deeply intuitive not !! 1258 Transitivity is a deeply intuitive notion about ordering that is not
1377 not always provided by real computer systems, !! 1259 always provided by real computer systems. The following example
1378 becomes visible at the same time to all CPUs, !! 1260 demonstrates transitivity (also called "cumulativity"):
1379 CPUs agree on the order in which all stores b <<
1380 support of full multicopy atomicity would rul <<
1381 optimizations, so a weaker form called ``othe <<
1382 instead guarantees only that a given store be <<
1383 time to all -other- CPUs. The remainder of t <<
1384 weaker form, but for brevity will call it sim <<
1385 <<
1386 The following example demonstrates multicopy <<
1387 1261
1388 CPU 1 CPU 2 1262 CPU 1 CPU 2 CPU 3
1389 ======================= ============= 1263 ======================= ======================= =======================
1390 { X = 0, Y = 0 } 1264 { X = 0, Y = 0 }
1391 STORE X=1 r1=LOAD X (re !! 1265 STORE X=1 LOAD X STORE Y=1
1392 <general barr !! 1266 <general barrier> <general barrier>
1393 STORE Y=r1 !! 1267 LOAD Y LOAD X
1394 !! 1268
1395 Suppose that CPU 2's load from X returns 1, w !! 1269 Suppose that CPU 2's load from X returns 1 and its load from Y returns 0.
1396 and CPU 3's load from Y returns 1. This indi !! 1270 This indicates that CPU 2's load from X in some sense follows CPU 1's
1397 to X precedes CPU 2's load from X and that CP !! 1271 store to X and that CPU 2's load from Y in some sense preceded CPU 3's
1398 CPU 3's load from Y. In addition, the memory !! 1272 store to Y. The question is then "Can CPU 3's load from X return 0?"
1399 CPU 2 executes its load before its store, and <<
1400 it loads from X. The question is then "Can C <<
1401 1273
1402 Because CPU 3's load from X in some sense com !! 1274 Because CPU 2's load from X in some sense came after CPU 1's store, it
1403 is natural to expect that CPU 3's load from X 1275 is natural to expect that CPU 3's load from X must therefore return 1.
1404 This expectation follows from multicopy atomi !! 1276 This expectation is an example of transitivity: if a load executing on
1405 on CPU B follows a load from the same variabl !! 1277 CPU A follows a load from the same variable executing on CPU B, then
1406 CPU A did not originally store the value whic !! 1278 CPU A's load must either return the same value that CPU B's load did,
1407 multicopy-atomic systems, CPU B's load must r !! 1279 or must return some later value.
1408 that CPU A's load did or some later value. H !! 1280
1409 does not require systems to be multicopy atom !! 1281 In the Linux kernel, use of general memory barriers guarantees
1410 !! 1282 transitivity. Therefore, in the above example, if CPU 2's load from X
1411 The use of a general memory barrier in the ex !! 1283 returns 1 and its load from Y returns 0, then CPU 3's load from X must
1412 for any lack of multicopy atomicity. In the !! 1284 also return 1.
1413 from X returns 1 and CPU 3's load from Y retu !! 1285
1414 from X must indeed also return 1. !! 1286 However, transitivity is -not- guaranteed for read or write barriers.
1415 !! 1287 For example, suppose that CPU 2's general barrier in the above example
1416 However, dependencies, read barriers, and wri !! 1288 is changed to a read barrier as shown below:
1417 able to compensate for non-multicopy atomicit <<
1418 that CPU 2's general barrier is removed from <<
1419 only the data dependency shown below: <<
1420 1289
1421 CPU 1 CPU 2 1290 CPU 1 CPU 2 CPU 3
1422 ======================= ============= 1291 ======================= ======================= =======================
1423 { X = 0, Y = 0 } 1292 { X = 0, Y = 0 }
1424 STORE X=1 r1=LOAD X (re !! 1293 STORE X=1 LOAD X STORE Y=1
1425 <data depende !! 1294 <read barrier> <general barrier>
1426 STORE Y=r1 !! 1295 LOAD Y LOAD X
1427 !! 1296
1428 This substitution allows non-multicopy atomic !! 1297 This substitution destroys transitivity: in this example, it is perfectly
1429 this example, it is perfectly legal for CPU 2 !! 1298 legal for CPU 2's load from X to return 1, its load from Y to return 0,
1430 CPU 3's load from Y to return 1, and its load !! 1299 and CPU 3's load from X to return 0.
1431 !! 1300
1432 The key point is that although CPU 2's data d !! 1301 The key point is that although CPU 2's read barrier orders its pair
1433 and store, it does not guarantee to order CPU !! 1302 of loads, it does not guarantee to order CPU 1's store. Therefore, if
1434 example runs on a non-multicopy-atomic system !! 1303 this example runs on a system where CPUs 1 and 2 share a store buffer
1435 store buffer or a level of cache, CPU 2 might !! 1304 or a level of cache, CPU 2 might have early access to CPU 1's writes.
1436 writes. General barriers are therefore requi !! 1305 General barriers are therefore required to ensure that all CPUs agree
1437 agree on the combined order of multiple acces !! 1306 on the combined order of CPU 1's and CPU 2's accesses.
1438 <<
1439 General barriers can compensate not only for <<
1440 but can also generate additional ordering tha <<
1441 CPUs will perceive the same order of -all- op <<
1442 chain of release-acquire pairs do not provide <<
1443 which means that only those CPUs on the chain <<
1444 on the combined order of the accesses. For e <<
1445 in deference to the ghost of Herman Hollerith <<
1446 <<
1447 int u, v, x, y, z; <<
1448 <<
1449 void cpu0(void) <<
1450 { <<
1451 r0 = smp_load_acquire(&x); <<
1452 WRITE_ONCE(u, 1); <<
1453 smp_store_release(&y, 1); <<
1454 } <<
1455 <<
1456 void cpu1(void) <<
1457 { <<
1458 r1 = smp_load_acquire(&y); <<
1459 r4 = READ_ONCE(v); <<
1460 r5 = READ_ONCE(u); <<
1461 smp_store_release(&z, 1); <<
1462 } <<
1463 <<
1464 void cpu2(void) <<
1465 { <<
1466 r2 = smp_load_acquire(&z); <<
1467 smp_store_release(&x, 1); <<
1468 } <<
1469 <<
1470 void cpu3(void) <<
1471 { <<
1472 WRITE_ONCE(v, 1); <<
1473 smp_mb(); <<
1474 r3 = READ_ONCE(u); <<
1475 } <<
1476 <<
1477 Because cpu0(), cpu1(), and cpu2() participat <<
1478 smp_store_release()/smp_load_acquire() pairs, <<
1479 is prohibited: <<
1480 <<
1481 r0 == 1 && r1 == 1 && r2 == 1 <<
1482 1307
1483 Furthermore, because of the release-acquire r !! 1308 To reiterate, if your code requires transitivity, use general barriers
1484 and cpu1(), cpu1() must see cpu0()'s writes, !! 1309 throughout.
1485 outcome is prohibited: <<
1486 <<
1487 r1 == 1 && r5 == 0 <<
1488 <<
1489 However, the ordering provided by a release-a <<
1490 to the CPUs participating in that chain and d <<
1491 at least aside from stores. Therefore, the f <<
1492 <<
1493 r0 == 0 && r1 == 1 && r2 == 1 && r3 = <<
1494 <<
1495 As an aside, the following outcome is also po <<
1496 <<
1497 r0 == 0 && r1 == 1 && r2 == 1 && r3 = <<
1498 <<
1499 Although cpu0(), cpu1(), and cpu2() will see <<
1500 writes in order, CPUs not involved in the rel <<
1501 well disagree on the order. This disagreemen <<
1502 the weak memory-barrier instructions used to <<
1503 and smp_store_release() are not required to o <<
1504 subsequent loads in all cases. This means th <<
1505 store to u as happening -after- cpu1()'s load <<
1506 both cpu0() and cpu1() agree that these two o <<
1507 intended order. <<
1508 <<
1509 However, please keep in mind that smp_load_ac <<
1510 In particular, it simply reads from its argum <<
1511 -not- ensure that any particular value will b <<
1512 following outcome is possible: <<
1513 <<
1514 r0 == 0 && r1 == 0 && r2 == 0 && r5 = <<
1515 <<
1516 Note that this outcome can happen even on a m <<
1517 consistent system where nothing is ever reord <<
1518 <<
1519 To reiterate, if your code requires full orde <<
1520 use general barriers throughout. <<
1521 1310
1522 1311
1523 ======================== 1312 ========================
1524 EXPLICIT KERNEL BARRIERS 1313 EXPLICIT KERNEL BARRIERS
1525 ======================== 1314 ========================
1526 1315
1527 The Linux kernel has a variety of different b 1316 The Linux kernel has a variety of different barriers that act at different
1528 levels: 1317 levels:
1529 1318
1530 (*) Compiler barrier. 1319 (*) Compiler barrier.
1531 1320
1532 (*) CPU memory barriers. 1321 (*) CPU memory barriers.
1533 1322
>> 1323 (*) MMIO write barrier.
>> 1324
1534 1325
1535 COMPILER BARRIER 1326 COMPILER BARRIER
1536 ---------------- 1327 ----------------
1537 1328
1538 The Linux kernel has an explicit compiler bar 1329 The Linux kernel has an explicit compiler barrier function that prevents the
1539 compiler from moving the memory accesses eith 1330 compiler from moving the memory accesses either side of it to the other side:
1540 1331
1541 barrier(); 1332 barrier();
1542 1333
1543 This is a general barrier -- there are no rea 1334 This is a general barrier -- there are no read-read or write-write
1544 variants of barrier(). However, READ_ONCE() 1335 variants of barrier(). However, READ_ONCE() and WRITE_ONCE() can be
1545 thought of as weak forms of barrier() that af 1336 thought of as weak forms of barrier() that affect only the specific
1546 accesses flagged by the READ_ONCE() or WRITE_ 1337 accesses flagged by the READ_ONCE() or WRITE_ONCE().
1547 1338
1548 The barrier() function has the following effe 1339 The barrier() function has the following effects:
1549 1340
1550 (*) Prevents the compiler from reordering ac 1341 (*) Prevents the compiler from reordering accesses following the
1551 barrier() to precede any accesses preced 1342 barrier() to precede any accesses preceding the barrier().
1552 One example use for this property is to 1343 One example use for this property is to ease communication between
1553 interrupt-handler code and the code that 1344 interrupt-handler code and the code that was interrupted.
1554 1345
1555 (*) Within a loop, forces the compiler to lo 1346 (*) Within a loop, forces the compiler to load the variables used
1556 in that loop's conditional on each pass 1347 in that loop's conditional on each pass through that loop.
1557 1348
1558 The READ_ONCE() and WRITE_ONCE() functions ca 1349 The READ_ONCE() and WRITE_ONCE() functions can prevent any number of
1559 optimizations that, while perfectly safe in s 1350 optimizations that, while perfectly safe in single-threaded code, can
1560 be fatal in concurrent code. Here are some e 1351 be fatal in concurrent code. Here are some examples of these sorts
1561 of optimizations: 1352 of optimizations:
1562 1353
1563 (*) The compiler is within its rights to reo 1354 (*) The compiler is within its rights to reorder loads and stores
1564 to the same variable, and in some cases, 1355 to the same variable, and in some cases, the CPU is within its
1565 rights to reorder loads to the same vari 1356 rights to reorder loads to the same variable. This means that
1566 the following code: 1357 the following code:
1567 1358
1568 a[0] = x; 1359 a[0] = x;
1569 a[1] = x; 1360 a[1] = x;
1570 1361
1571 Might result in an older value of x stor 1362 Might result in an older value of x stored in a[1] than in a[0].
1572 Prevent both the compiler and the CPU fr 1363 Prevent both the compiler and the CPU from doing this as follows:
1573 1364
1574 a[0] = READ_ONCE(x); 1365 a[0] = READ_ONCE(x);
1575 a[1] = READ_ONCE(x); 1366 a[1] = READ_ONCE(x);
1576 1367
1577 In short, READ_ONCE() and WRITE_ONCE() p 1368 In short, READ_ONCE() and WRITE_ONCE() provide cache coherence for
1578 accesses from multiple CPUs to a single 1369 accesses from multiple CPUs to a single variable.
1579 1370
1580 (*) The compiler is within its rights to mer 1371 (*) The compiler is within its rights to merge successive loads from
1581 the same variable. Such merging can cau 1372 the same variable. Such merging can cause the compiler to "optimize"
1582 the following code: 1373 the following code:
1583 1374
1584 while (tmp = a) 1375 while (tmp = a)
1585 do_something_with(tmp); 1376 do_something_with(tmp);
1586 1377
1587 into the following code, which, although 1378 into the following code, which, although in some sense legitimate
1588 for single-threaded code, is almost cert 1379 for single-threaded code, is almost certainly not what the developer
1589 intended: 1380 intended:
1590 1381
1591 if (tmp = a) 1382 if (tmp = a)
1592 for (;;) 1383 for (;;)
1593 do_something_with(tmp 1384 do_something_with(tmp);
1594 1385
1595 Use READ_ONCE() to prevent the compiler 1386 Use READ_ONCE() to prevent the compiler from doing this to you:
1596 1387
1597 while (tmp = READ_ONCE(a)) 1388 while (tmp = READ_ONCE(a))
1598 do_something_with(tmp); 1389 do_something_with(tmp);
1599 1390
1600 (*) The compiler is within its rights to rel 1391 (*) The compiler is within its rights to reload a variable, for example,
1601 in cases where high register pressure pr 1392 in cases where high register pressure prevents the compiler from
1602 keeping all data of interest in register 1393 keeping all data of interest in registers. The compiler might
1603 therefore optimize the variable 'tmp' ou 1394 therefore optimize the variable 'tmp' out of our previous example:
1604 1395
1605 while (tmp = a) 1396 while (tmp = a)
1606 do_something_with(tmp); 1397 do_something_with(tmp);
1607 1398
1608 This could result in the following code, 1399 This could result in the following code, which is perfectly safe in
1609 single-threaded code, but can be fatal i 1400 single-threaded code, but can be fatal in concurrent code:
1610 1401
1611 while (a) 1402 while (a)
1612 do_something_with(a); 1403 do_something_with(a);
1613 1404
1614 For example, the optimized version of th 1405 For example, the optimized version of this code could result in
1615 passing a zero to do_something_with() in 1406 passing a zero to do_something_with() in the case where the variable
1616 a was modified by some other CPU between 1407 a was modified by some other CPU between the "while" statement and
1617 the call to do_something_with(). 1408 the call to do_something_with().
1618 1409
1619 Again, use READ_ONCE() to prevent the co 1410 Again, use READ_ONCE() to prevent the compiler from doing this:
1620 1411
1621 while (tmp = READ_ONCE(a)) 1412 while (tmp = READ_ONCE(a))
1622 do_something_with(tmp); 1413 do_something_with(tmp);
1623 1414
1624 Note that if the compiler runs short of 1415 Note that if the compiler runs short of registers, it might save
1625 tmp onto the stack. The overhead of thi 1416 tmp onto the stack. The overhead of this saving and later restoring
1626 is why compilers reload variables. Doin 1417 is why compilers reload variables. Doing so is perfectly safe for
1627 single-threaded code, so you need to tel 1418 single-threaded code, so you need to tell the compiler about cases
1628 where it is not safe. 1419 where it is not safe.
1629 1420
1630 (*) The compiler is within its rights to omi 1421 (*) The compiler is within its rights to omit a load entirely if it knows
1631 what the value will be. For example, if 1422 what the value will be. For example, if the compiler can prove that
1632 the value of variable 'a' is always zero 1423 the value of variable 'a' is always zero, it can optimize this code:
1633 1424
1634 while (tmp = a) 1425 while (tmp = a)
1635 do_something_with(tmp); 1426 do_something_with(tmp);
1636 1427
1637 Into this: 1428 Into this:
1638 1429
1639 do { } while (0); 1430 do { } while (0);
1640 1431
1641 This transformation is a win for single- 1432 This transformation is a win for single-threaded code because it
1642 gets rid of a load and a branch. The pr 1433 gets rid of a load and a branch. The problem is that the compiler
1643 will carry out its proof assuming that t 1434 will carry out its proof assuming that the current CPU is the only
1644 one updating variable 'a'. If variable 1435 one updating variable 'a'. If variable 'a' is shared, then the
1645 compiler's proof will be erroneous. Use 1436 compiler's proof will be erroneous. Use READ_ONCE() to tell the
1646 compiler that it doesn't know as much as 1437 compiler that it doesn't know as much as it thinks it does:
1647 1438
1648 while (tmp = READ_ONCE(a)) 1439 while (tmp = READ_ONCE(a))
1649 do_something_with(tmp); 1440 do_something_with(tmp);
1650 1441
1651 But please note that the compiler is als 1442 But please note that the compiler is also closely watching what you
1652 do with the value after the READ_ONCE(). 1443 do with the value after the READ_ONCE(). For example, suppose you
1653 do the following and MAX is a preprocess 1444 do the following and MAX is a preprocessor macro with the value 1:
1654 1445
1655 while ((tmp = READ_ONCE(a)) % MAX) 1446 while ((tmp = READ_ONCE(a)) % MAX)
1656 do_something_with(tmp); 1447 do_something_with(tmp);
1657 1448
1658 Then the compiler knows that the result 1449 Then the compiler knows that the result of the "%" operator applied
1659 to MAX will always be zero, again allowi 1450 to MAX will always be zero, again allowing the compiler to optimize
1660 the code into near-nonexistence. (It wi 1451 the code into near-nonexistence. (It will still load from the
1661 variable 'a'.) 1452 variable 'a'.)
1662 1453
1663 (*) Similarly, the compiler is within its ri 1454 (*) Similarly, the compiler is within its rights to omit a store entirely
1664 if it knows that the variable already ha 1455 if it knows that the variable already has the value being stored.
1665 Again, the compiler assumes that the cur 1456 Again, the compiler assumes that the current CPU is the only one
1666 storing into the variable, which can cau 1457 storing into the variable, which can cause the compiler to do the
1667 wrong thing for shared variables. For e 1458 wrong thing for shared variables. For example, suppose you have
1668 the following: 1459 the following:
1669 1460
1670 a = 0; 1461 a = 0;
1671 ... Code that does not store to varia !! 1462 /* Code that does not store to variable a. */
1672 a = 0; 1463 a = 0;
1673 1464
1674 The compiler sees that the value of vari 1465 The compiler sees that the value of variable 'a' is already zero, so
1675 it might well omit the second store. Th 1466 it might well omit the second store. This would come as a fatal
1676 surprise if some other CPU might have st 1467 surprise if some other CPU might have stored to variable 'a' in the
1677 meantime. 1468 meantime.
1678 1469
1679 Use WRITE_ONCE() to prevent the compiler 1470 Use WRITE_ONCE() to prevent the compiler from making this sort of
1680 wrong guess: 1471 wrong guess:
1681 1472
1682 WRITE_ONCE(a, 0); 1473 WRITE_ONCE(a, 0);
1683 ... Code that does not store to varia !! 1474 /* Code that does not store to variable a. */
1684 WRITE_ONCE(a, 0); 1475 WRITE_ONCE(a, 0);
1685 1476
1686 (*) The compiler is within its rights to reo 1477 (*) The compiler is within its rights to reorder memory accesses unless
1687 you tell it not to. For example, consid 1478 you tell it not to. For example, consider the following interaction
1688 between process-level code and an interr 1479 between process-level code and an interrupt handler:
1689 1480
1690 void process_level(void) 1481 void process_level(void)
1691 { 1482 {
1692 msg = get_message(); 1483 msg = get_message();
1693 flag = true; 1484 flag = true;
1694 } 1485 }
1695 1486
1696 void interrupt_handler(void) 1487 void interrupt_handler(void)
1697 { 1488 {
1698 if (flag) 1489 if (flag)
1699 process_message(msg); 1490 process_message(msg);
1700 } 1491 }
1701 1492
1702 There is nothing to prevent the compiler 1493 There is nothing to prevent the compiler from transforming
1703 process_level() to the following, in fac 1494 process_level() to the following, in fact, this might well be a
1704 win for single-threaded code: 1495 win for single-threaded code:
1705 1496
1706 void process_level(void) 1497 void process_level(void)
1707 { 1498 {
1708 flag = true; 1499 flag = true;
1709 msg = get_message(); 1500 msg = get_message();
1710 } 1501 }
1711 1502
1712 If the interrupt occurs between these tw 1503 If the interrupt occurs between these two statement, then
1713 interrupt_handler() might be passed a ga 1504 interrupt_handler() might be passed a garbled msg. Use WRITE_ONCE()
1714 to prevent this as follows: 1505 to prevent this as follows:
1715 1506
1716 void process_level(void) 1507 void process_level(void)
1717 { 1508 {
1718 WRITE_ONCE(msg, get_message() 1509 WRITE_ONCE(msg, get_message());
1719 WRITE_ONCE(flag, true); 1510 WRITE_ONCE(flag, true);
1720 } 1511 }
1721 1512
1722 void interrupt_handler(void) 1513 void interrupt_handler(void)
1723 { 1514 {
1724 if (READ_ONCE(flag)) 1515 if (READ_ONCE(flag))
1725 process_message(READ_ 1516 process_message(READ_ONCE(msg));
1726 } 1517 }
1727 1518
1728 Note that the READ_ONCE() and WRITE_ONCE 1519 Note that the READ_ONCE() and WRITE_ONCE() wrappers in
1729 interrupt_handler() are needed if this i 1520 interrupt_handler() are needed if this interrupt handler can itself
1730 be interrupted by something that also ac 1521 be interrupted by something that also accesses 'flag' and 'msg',
1731 for example, a nested interrupt or an NM 1522 for example, a nested interrupt or an NMI. Otherwise, READ_ONCE()
1732 and WRITE_ONCE() are not needed in inter 1523 and WRITE_ONCE() are not needed in interrupt_handler() other than
1733 for documentation purposes. (Note also 1524 for documentation purposes. (Note also that nested interrupts
1734 do not typically occur in modern Linux k 1525 do not typically occur in modern Linux kernels, in fact, if an
1735 interrupt handler returns with interrupt 1526 interrupt handler returns with interrupts enabled, you will get a
1736 WARN_ONCE() splat.) 1527 WARN_ONCE() splat.)
1737 1528
1738 You should assume that the compiler can 1529 You should assume that the compiler can move READ_ONCE() and
1739 WRITE_ONCE() past code not containing RE 1530 WRITE_ONCE() past code not containing READ_ONCE(), WRITE_ONCE(),
1740 barrier(), or similar primitives. 1531 barrier(), or similar primitives.
1741 1532
1742 This effect could also be achieved using 1533 This effect could also be achieved using barrier(), but READ_ONCE()
1743 and WRITE_ONCE() are more selective: Wi 1534 and WRITE_ONCE() are more selective: With READ_ONCE() and
1744 WRITE_ONCE(), the compiler need only for 1535 WRITE_ONCE(), the compiler need only forget the contents of the
1745 indicated memory locations, while with b 1536 indicated memory locations, while with barrier() the compiler must
1746 discard the value of all memory location !! 1537 discard the value of all memory locations that it has currented
1747 cached in any machine registers. Of cou 1538 cached in any machine registers. Of course, the compiler must also
1748 respect the order in which the READ_ONCE 1539 respect the order in which the READ_ONCE()s and WRITE_ONCE()s occur,
1749 though the CPU of course need not do so. 1540 though the CPU of course need not do so.
1750 1541
1751 (*) The compiler is within its rights to inv 1542 (*) The compiler is within its rights to invent stores to a variable,
1752 as in the following example: 1543 as in the following example:
1753 1544
1754 if (a) 1545 if (a)
1755 b = a; 1546 b = a;
1756 else 1547 else
1757 b = 42; 1548 b = 42;
1758 1549
1759 The compiler might save a branch by opti 1550 The compiler might save a branch by optimizing this as follows:
1760 1551
1761 b = 42; 1552 b = 42;
1762 if (a) 1553 if (a)
1763 b = a; 1554 b = a;
1764 1555
1765 In single-threaded code, this is not onl 1556 In single-threaded code, this is not only safe, but also saves
1766 a branch. Unfortunately, in concurrent 1557 a branch. Unfortunately, in concurrent code, this optimization
1767 could cause some other CPU to see a spur 1558 could cause some other CPU to see a spurious value of 42 -- even
1768 if variable 'a' was never zero -- when l 1559 if variable 'a' was never zero -- when loading variable 'b'.
1769 Use WRITE_ONCE() to prevent this as foll 1560 Use WRITE_ONCE() to prevent this as follows:
1770 1561
1771 if (a) 1562 if (a)
1772 WRITE_ONCE(b, a); 1563 WRITE_ONCE(b, a);
1773 else 1564 else
1774 WRITE_ONCE(b, 42); 1565 WRITE_ONCE(b, 42);
1775 1566
1776 The compiler can also invent loads. The 1567 The compiler can also invent loads. These are usually less
1777 damaging, but they can result in cache-l 1568 damaging, but they can result in cache-line bouncing and thus in
1778 poor performance and scalability. Use R 1569 poor performance and scalability. Use READ_ONCE() to prevent
1779 invented loads. 1570 invented loads.
1780 1571
1781 (*) For aligned memory locations whose size 1572 (*) For aligned memory locations whose size allows them to be accessed
1782 with a single memory-reference instructi 1573 with a single memory-reference instruction, prevents "load tearing"
1783 and "store tearing," in which a single l 1574 and "store tearing," in which a single large access is replaced by
1784 multiple smaller accesses. For example, 1575 multiple smaller accesses. For example, given an architecture having
1785 16-bit store instructions with 7-bit imm 1576 16-bit store instructions with 7-bit immediate fields, the compiler
1786 might be tempted to use two 16-bit store 1577 might be tempted to use two 16-bit store-immediate instructions to
1787 implement the following 32-bit store: 1578 implement the following 32-bit store:
1788 1579
1789 p = 0x00010002; 1580 p = 0x00010002;
1790 1581
1791 Please note that GCC really does use thi 1582 Please note that GCC really does use this sort of optimization,
1792 which is not surprising given that it wo 1583 which is not surprising given that it would likely take more
1793 than two instructions to build the const 1584 than two instructions to build the constant and then store it.
1794 This optimization can therefore be a win 1585 This optimization can therefore be a win in single-threaded code.
1795 In fact, a recent bug (since fixed) caus 1586 In fact, a recent bug (since fixed) caused GCC to incorrectly use
1796 this optimization in a volatile store. 1587 this optimization in a volatile store. In the absence of such bugs,
1797 use of WRITE_ONCE() prevents store teari 1588 use of WRITE_ONCE() prevents store tearing in the following example:
1798 1589
1799 WRITE_ONCE(p, 0x00010002); 1590 WRITE_ONCE(p, 0x00010002);
1800 1591
1801 Use of packed structures can also result 1592 Use of packed structures can also result in load and store tearing,
1802 as in this example: 1593 as in this example:
1803 1594
1804 struct __attribute__((__packed__)) fo 1595 struct __attribute__((__packed__)) foo {
1805 short a; 1596 short a;
1806 int b; 1597 int b;
1807 short c; 1598 short c;
1808 }; 1599 };
1809 struct foo foo1, foo2; 1600 struct foo foo1, foo2;
1810 ... 1601 ...
1811 1602
1812 foo2.a = foo1.a; 1603 foo2.a = foo1.a;
1813 foo2.b = foo1.b; 1604 foo2.b = foo1.b;
1814 foo2.c = foo1.c; 1605 foo2.c = foo1.c;
1815 1606
1816 Because there are no READ_ONCE() or WRIT 1607 Because there are no READ_ONCE() or WRITE_ONCE() wrappers and no
1817 volatile markings, the compiler would be 1608 volatile markings, the compiler would be well within its rights to
1818 implement these three assignment stateme 1609 implement these three assignment statements as a pair of 32-bit
1819 loads followed by a pair of 32-bit store 1610 loads followed by a pair of 32-bit stores. This would result in
1820 load tearing on 'foo1.b' and store teari 1611 load tearing on 'foo1.b' and store tearing on 'foo2.b'. READ_ONCE()
1821 and WRITE_ONCE() again prevent tearing i 1612 and WRITE_ONCE() again prevent tearing in this example:
1822 1613
1823 foo2.a = foo1.a; 1614 foo2.a = foo1.a;
1824 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b)) 1615 WRITE_ONCE(foo2.b, READ_ONCE(foo1.b));
1825 foo2.c = foo1.c; 1616 foo2.c = foo1.c;
1826 1617
1827 All that aside, it is never necessary to use 1618 All that aside, it is never necessary to use READ_ONCE() and
1828 WRITE_ONCE() on a variable that has been mark 1619 WRITE_ONCE() on a variable that has been marked volatile. For example,
1829 because 'jiffies' is marked volatile, it is n 1620 because 'jiffies' is marked volatile, it is never necessary to
1830 say READ_ONCE(jiffies). The reason for this 1621 say READ_ONCE(jiffies). The reason for this is that READ_ONCE() and
1831 WRITE_ONCE() are implemented as volatile cast 1622 WRITE_ONCE() are implemented as volatile casts, which has no effect when
1832 its argument is already marked volatile. 1623 its argument is already marked volatile.
1833 1624
1834 Please note that these compiler barriers have 1625 Please note that these compiler barriers have no direct effect on the CPU,
1835 which may then reorder things however it wish 1626 which may then reorder things however it wishes.
1836 1627
1837 1628
1838 CPU MEMORY BARRIERS 1629 CPU MEMORY BARRIERS
1839 ------------------- 1630 -------------------
1840 1631
1841 The Linux kernel has seven basic CPU memory b !! 1632 The Linux kernel has eight basic CPU memory barriers:
1842 1633
1843 TYPE MANDATORY !! 1634 TYPE MANDATORY SMP CONDITIONAL
1844 ======================= ============= !! 1635 =============== ======================= ===========================
1845 GENERAL mb() !! 1636 GENERAL mb() smp_mb()
1846 WRITE wmb() !! 1637 WRITE wmb() smp_wmb()
1847 READ rmb() !! 1638 READ rmb() smp_rmb()
1848 ADDRESS DEPENDENCY !! 1639 DATA DEPENDENCY read_barrier_depends() smp_read_barrier_depends()
1849 1640
1850 1641
1851 All memory barriers except the address-depend !! 1642 All memory barriers except the data dependency barriers imply a compiler
1852 barrier. Address dependencies do not impose !! 1643 barrier. Data dependencies do not impose any additional compiler ordering.
1853 1644
1854 Aside: In the case of address dependencies, t !! 1645 Aside: In the case of data dependencies, the compiler would be expected
1855 to issue the loads in the correct order (eg. 1646 to issue the loads in the correct order (eg. `a[b]` would have to load
1856 the value of b before loading a[b]), however 1647 the value of b before loading a[b]), however there is no guarantee in
1857 the C specification that the compiler may not 1648 the C specification that the compiler may not speculate the value of b
1858 (eg. is equal to 1) and load a[b] before b (e !! 1649 (eg. is equal to 1) and load a before b (eg. tmp = a[1]; if (b != 1)
1859 tmp = a[b]; ). There is also the problem of !! 1650 tmp = a[b]; ). There is also the problem of a compiler reloading b after
1860 having loaded a[b], thus having a newer copy !! 1651 having loaded a[b], thus having a newer copy of b than a[b]. A consensus
1861 has not yet been reached about these problems 1652 has not yet been reached about these problems, however the READ_ONCE()
1862 macro is a good place to start looking. 1653 macro is a good place to start looking.
1863 1654
1864 SMP memory barriers are reduced to compiler b 1655 SMP memory barriers are reduced to compiler barriers on uniprocessor compiled
1865 systems because it is assumed that a CPU will 1656 systems because it is assumed that a CPU will appear to be self-consistent,
1866 and will order overlapping accesses correctly 1657 and will order overlapping accesses correctly with respect to itself.
1867 However, see the subsection on "Virtual Machi <<
1868 1658
1869 [!] Note that SMP memory barriers _must_ be u 1659 [!] Note that SMP memory barriers _must_ be used to control the ordering of
1870 references to shared memory on SMP systems, t 1660 references to shared memory on SMP systems, though the use of locking instead
1871 is sufficient. 1661 is sufficient.
1872 1662
1873 Mandatory barriers should not be used to cont 1663 Mandatory barriers should not be used to control SMP effects, since mandatory
1874 barriers impose unnecessary overhead on both !! 1664 barriers unnecessarily impose overhead on UP systems. They may, however, be
1875 however, be used to control MMIO effects on a !! 1665 used to control MMIO effects on accesses through relaxed memory I/O windows.
1876 windows. These barriers are required even on !! 1666 These are required even on non-SMP systems as they affect the order in which
1877 the order in which memory operations appear t !! 1667 memory operations appear to a device by prohibiting both the compiler and the
1878 compiler and the CPU from reordering them. !! 1668 CPU from reordering them.
1879 1669
1880 1670
1881 There are some more advanced barrier function 1671 There are some more advanced barrier functions:
1882 1672
1883 (*) smp_store_mb(var, value) 1673 (*) smp_store_mb(var, value)
1884 1674
1885 This assigns the value to the variable a 1675 This assigns the value to the variable and then inserts a full memory
1886 barrier after it. It isn't guaranteed t !! 1676 barrier after it, depending on the function. It isn't guaranteed to
1887 compiler barrier in a UP compilation. !! 1677 insert anything more than a compiler barrier in a UP compilation.
1888 1678
1889 1679
1890 (*) smp_mb__before_atomic(); 1680 (*) smp_mb__before_atomic();
1891 (*) smp_mb__after_atomic(); 1681 (*) smp_mb__after_atomic();
1892 1682
1893 These are for use with atomic RMW functi !! 1683 These are for use with atomic (such as add, subtract, increment and
1894 barriers, but where the code needs a mem !! 1684 decrement) functions that don't return a value, especially when used for
1895 RMW functions that do not imply a memory !! 1685 reference counting. These functions do not imply memory barriers.
1896 subtract, (failed) conditional operation <<
1897 but not atomic_read or atomic_set. A com <<
1898 barrier may be required is when atomic o <<
1899 counting. <<
1900 1686
1901 These are also used for atomic RMW bitop !! 1687 These are also used for atomic bitop functions that do not return a
1902 memory barrier (such as set_bit and clea !! 1688 value (such as set_bit and clear_bit).
1903 1689
1904 As an example, consider a piece of code 1690 As an example, consider a piece of code that marks an object as being dead
1905 and then decrements the object's referen 1691 and then decrements the object's reference count:
1906 1692
1907 obj->dead = 1; 1693 obj->dead = 1;
1908 smp_mb__before_atomic(); 1694 smp_mb__before_atomic();
1909 atomic_dec(&obj->ref_count); 1695 atomic_dec(&obj->ref_count);
1910 1696
1911 This makes sure that the death mark on t 1697 This makes sure that the death mark on the object is perceived to be set
1912 *before* the reference counter is decrem 1698 *before* the reference counter is decremented.
1913 1699
1914 See Documentation/atomic_{t,bitops}.txt !! 1700 See Documentation/atomic_ops.txt for more information. See the "Atomic
>> 1701 operations" subsection for information on where to use these.
>> 1702
>> 1703
>> 1704 (*) lockless_dereference();
>> 1705 This can be thought of as a pointer-fetch wrapper around the
>> 1706 smp_read_barrier_depends() data-dependency barrier.
>> 1707
>> 1708 This is also similar to rcu_dereference(), but in cases where
>> 1709 object lifetime is handled by some mechanism other than RCU, for
>> 1710 example, when the objects removed only when the system goes down.
>> 1711 In addition, lockless_dereference() is used in some data structures
>> 1712 that can be used both with and without RCU.
1915 1713
1916 1714
1917 (*) dma_wmb(); 1715 (*) dma_wmb();
1918 (*) dma_rmb(); 1716 (*) dma_rmb();
1919 (*) dma_mb(); <<
1920 1717
1921 These are for use with consistent memory 1718 These are for use with consistent memory to guarantee the ordering
1922 of writes or reads of shared memory acce 1719 of writes or reads of shared memory accessible to both the CPU and a
1923 DMA capable device. See Documentation/co !! 1720 DMA capable device.
1924 information about consistent memory. <<
1925 1721
1926 For example, consider a device driver th 1722 For example, consider a device driver that shares memory with a device
1927 and uses a descriptor status value to in 1723 and uses a descriptor status value to indicate if the descriptor belongs
1928 to the device or the CPU, and a doorbell 1724 to the device or the CPU, and a doorbell to notify it when new
1929 descriptors are available: 1725 descriptors are available:
1930 1726
1931 if (desc->status != DEVICE_OWN) { 1727 if (desc->status != DEVICE_OWN) {
1932 /* do not read data until we 1728 /* do not read data until we own descriptor */
1933 dma_rmb(); 1729 dma_rmb();
1934 1730
1935 /* read/modify data */ 1731 /* read/modify data */
1936 read_data = desc->data; 1732 read_data = desc->data;
1937 desc->data = write_data; 1733 desc->data = write_data;
1938 1734
1939 /* flush modifications before 1735 /* flush modifications before status update */
1940 dma_wmb(); 1736 dma_wmb();
1941 1737
1942 /* assign ownership */ 1738 /* assign ownership */
1943 desc->status = DEVICE_OWN; 1739 desc->status = DEVICE_OWN;
1944 1740
1945 /* Make descriptor status vis !! 1741 /* force memory to sync before notifying device via MMIO */
1946 * notify device of new descr !! 1742 wmb();
1947 */ !! 1743
>> 1744 /* notify device of new descriptors */
1948 writel(DESC_NOTIFY, doorbell) 1745 writel(DESC_NOTIFY, doorbell);
1949 } 1746 }
1950 1747
1951 The dma_rmb() allows us to guarantee tha !! 1748 The dma_rmb() allows us guarantee the device has released ownership
1952 before we read the data from the descrip 1749 before we read the data from the descriptor, and the dma_wmb() allows
1953 us to guarantee the data is written to t 1750 us to guarantee the data is written to the descriptor before the device
1954 can see it now has ownership. The dma_m !! 1751 can see it now has ownership. The wmb() is needed to guarantee that the
1955 a dma_wmb(). !! 1752 cache coherent memory writes have completed before attempting a write to
>> 1753 the cache incoherent MMIO region.
>> 1754
>> 1755 See Documentation/DMA-API.txt for more information on consistent memory.
>> 1756
>> 1757 MMIO WRITE BARRIER
>> 1758 ------------------
>> 1759
>> 1760 The Linux kernel also has a special barrier for use with memory-mapped I/O
>> 1761 writes:
>> 1762
>> 1763 mmiowb();
>> 1764
>> 1765 This is a variation on the mandatory write barrier that causes writes to weakly
>> 1766 ordered I/O regions to be partially ordered. Its effects may go beyond the
>> 1767 CPU->Hardware interface and actually affect the hardware at some level.
>> 1768
>> 1769 See the subsection "Locks vs I/O accesses" for more information.
1956 1770
1957 Note that the dma_*() barriers do not pr <<
1958 accesses to MMIO regions. See the later <<
1959 subsection for more information about I/ <<
1960 <<
1961 (*) pmem_wmb(); <<
1962 <<
1963 This is for use with persistent memory t <<
1964 modifications are written to persistent <<
1965 durability domain. <<
1966 <<
1967 For example, after a non-temporal write <<
1968 to ensure that stores have reached a pla <<
1969 that stores have updated persistent stor <<
1970 data transfer caused by subsequent instr <<
1971 in addition to the ordering done by wmb( <<
1972 <<
1973 For load from persistent memory, existin <<
1974 to ensure read ordering. <<
1975 <<
1976 (*) io_stop_wc(); <<
1977 <<
1978 For memory accesses with write-combining <<
1979 by ioremap_wc()), the CPU may wait for p <<
1980 subsequent ones. io_stop_wc() can be use <<
1981 write-combining memory accesses before t <<
1982 such wait has performance implications. <<
1983 1771
1984 =============================== 1772 ===============================
1985 IMPLICIT KERNEL MEMORY BARRIERS 1773 IMPLICIT KERNEL MEMORY BARRIERS
1986 =============================== 1774 ===============================
1987 1775
1988 Some of the other functions in the linux kern 1776 Some of the other functions in the linux kernel imply memory barriers, amongst
1989 which are locking and scheduling functions. 1777 which are locking and scheduling functions.
1990 1778
1991 This specification is a _minimum_ guarantee; 1779 This specification is a _minimum_ guarantee; any particular architecture may
1992 provide more substantial guarantees, but thes 1780 provide more substantial guarantees, but these may not be relied upon outside
1993 of arch specific code. 1781 of arch specific code.
1994 1782
1995 1783
1996 LOCK ACQUISITION FUNCTIONS !! 1784 ACQUIRING FUNCTIONS
1997 -------------------------- !! 1785 -------------------
1998 1786
1999 The Linux kernel has a number of locking cons 1787 The Linux kernel has a number of locking constructs:
2000 1788
2001 (*) spin locks 1789 (*) spin locks
2002 (*) R/W spin locks 1790 (*) R/W spin locks
2003 (*) mutexes 1791 (*) mutexes
2004 (*) semaphores 1792 (*) semaphores
2005 (*) R/W semaphores 1793 (*) R/W semaphores
2006 1794
2007 In all cases there are variants on "ACQUIRE" 1795 In all cases there are variants on "ACQUIRE" operations and "RELEASE" operations
2008 for each construct. These operations all imp 1796 for each construct. These operations all imply certain barriers:
2009 1797
2010 (1) ACQUIRE operation implication: 1798 (1) ACQUIRE operation implication:
2011 1799
2012 Memory operations issued after the ACQUI 1800 Memory operations issued after the ACQUIRE will be completed after the
2013 ACQUIRE operation has completed. 1801 ACQUIRE operation has completed.
2014 1802
2015 Memory operations issued before the ACQU 1803 Memory operations issued before the ACQUIRE may be completed after
2016 the ACQUIRE operation has completed. !! 1804 the ACQUIRE operation has completed. An smp_mb__before_spinlock(),
>> 1805 combined with a following ACQUIRE, orders prior stores against
>> 1806 subsequent loads and stores. Note that this is weaker than smp_mb()!
>> 1807 The smp_mb__before_spinlock() primitive is free on many architectures.
2017 1808
2018 (2) RELEASE operation implication: 1809 (2) RELEASE operation implication:
2019 1810
2020 Memory operations issued before the RELE 1811 Memory operations issued before the RELEASE will be completed before the
2021 RELEASE operation has completed. 1812 RELEASE operation has completed.
2022 1813
2023 Memory operations issued after the RELEA 1814 Memory operations issued after the RELEASE may be completed before the
2024 RELEASE operation has completed. 1815 RELEASE operation has completed.
2025 1816
2026 (3) ACQUIRE vs ACQUIRE implication: 1817 (3) ACQUIRE vs ACQUIRE implication:
2027 1818
2028 All ACQUIRE operations issued before ano 1819 All ACQUIRE operations issued before another ACQUIRE operation will be
2029 completed before that ACQUIRE operation. 1820 completed before that ACQUIRE operation.
2030 1821
2031 (4) ACQUIRE vs RELEASE implication: 1822 (4) ACQUIRE vs RELEASE implication:
2032 1823
2033 All ACQUIRE operations issued before a R 1824 All ACQUIRE operations issued before a RELEASE operation will be
2034 completed before the RELEASE operation. 1825 completed before the RELEASE operation.
2035 1826
2036 (5) Failed conditional ACQUIRE implication: 1827 (5) Failed conditional ACQUIRE implication:
2037 1828
2038 Certain locking variants of the ACQUIRE 1829 Certain locking variants of the ACQUIRE operation may fail, either due to
2039 being unable to get the lock immediately 1830 being unable to get the lock immediately, or due to receiving an unblocked
2040 signal while asleep waiting for the lock !! 1831 signal whilst asleep waiting for the lock to become available. Failed
2041 locks do not imply any sort of barrier. 1832 locks do not imply any sort of barrier.
2042 1833
2043 [!] Note: one of the consequences of lock ACQ 1834 [!] Note: one of the consequences of lock ACQUIREs and RELEASEs being only
2044 one-way barriers is that the effects of instr 1835 one-way barriers is that the effects of instructions outside of a critical
2045 section may seep into the inside of the criti 1836 section may seep into the inside of the critical section.
2046 1837
2047 An ACQUIRE followed by a RELEASE may not be a 1838 An ACQUIRE followed by a RELEASE may not be assumed to be full memory barrier
2048 because it is possible for an access precedin 1839 because it is possible for an access preceding the ACQUIRE to happen after the
2049 ACQUIRE, and an access following the RELEASE 1840 ACQUIRE, and an access following the RELEASE to happen before the RELEASE, and
2050 the two accesses can themselves then cross: 1841 the two accesses can themselves then cross:
2051 1842
2052 *A = a; 1843 *A = a;
2053 ACQUIRE M 1844 ACQUIRE M
2054 RELEASE M 1845 RELEASE M
2055 *B = b; 1846 *B = b;
2056 1847
2057 may occur as: 1848 may occur as:
2058 1849
2059 ACQUIRE M, STORE *B, STORE *A, RELEAS 1850 ACQUIRE M, STORE *B, STORE *A, RELEASE M
2060 1851
2061 When the ACQUIRE and RELEASE are a lock acqui 1852 When the ACQUIRE and RELEASE are a lock acquisition and release,
2062 respectively, this same reordering can occur 1853 respectively, this same reordering can occur if the lock's ACQUIRE and
2063 RELEASE are to the same lock variable, but on 1854 RELEASE are to the same lock variable, but only from the perspective of
2064 another CPU not holding that lock. In short, 1855 another CPU not holding that lock. In short, a ACQUIRE followed by an
2065 RELEASE may -not- be assumed to be a full mem 1856 RELEASE may -not- be assumed to be a full memory barrier.
2066 1857
2067 Similarly, the reverse case of a RELEASE foll 1858 Similarly, the reverse case of a RELEASE followed by an ACQUIRE does
2068 not imply a full memory barrier. Therefore, 1859 not imply a full memory barrier. Therefore, the CPU's execution of the
2069 critical sections corresponding to the RELEAS 1860 critical sections corresponding to the RELEASE and the ACQUIRE can cross,
2070 so that: 1861 so that:
2071 1862
2072 *A = a; 1863 *A = a;
2073 RELEASE M 1864 RELEASE M
2074 ACQUIRE N 1865 ACQUIRE N
2075 *B = b; 1866 *B = b;
2076 1867
2077 could occur as: 1868 could occur as:
2078 1869
2079 ACQUIRE N, STORE *B, STORE *A, RELEAS 1870 ACQUIRE N, STORE *B, STORE *A, RELEASE M
2080 1871
2081 It might appear that this reordering could in 1872 It might appear that this reordering could introduce a deadlock.
2082 However, this cannot happen because if such a 1873 However, this cannot happen because if such a deadlock threatened,
2083 the RELEASE would simply complete, thereby av 1874 the RELEASE would simply complete, thereby avoiding the deadlock.
2084 1875
2085 Why does this work? 1876 Why does this work?
2086 1877
2087 One key point is that we are only tal 1878 One key point is that we are only talking about the CPU doing
2088 the reordering, not the compiler. If 1879 the reordering, not the compiler. If the compiler (or, for
2089 that matter, the developer) switched 1880 that matter, the developer) switched the operations, deadlock
2090 -could- occur. 1881 -could- occur.
2091 1882
2092 But suppose the CPU reordered the ope 1883 But suppose the CPU reordered the operations. In this case,
2093 the unlock precedes the lock in the a 1884 the unlock precedes the lock in the assembly code. The CPU
2094 simply elected to try executing the l 1885 simply elected to try executing the later lock operation first.
2095 If there is a deadlock, this lock ope 1886 If there is a deadlock, this lock operation will simply spin (or
2096 try to sleep, but more on that later) 1887 try to sleep, but more on that later). The CPU will eventually
2097 execute the unlock operation (which p 1888 execute the unlock operation (which preceded the lock operation
2098 in the assembly code), which will unr 1889 in the assembly code), which will unravel the potential deadlock,
2099 allowing the lock operation to succee 1890 allowing the lock operation to succeed.
2100 1891
2101 But what if the lock is a sleeplock? 1892 But what if the lock is a sleeplock? In that case, the code will
2102 try to enter the scheduler, where it 1893 try to enter the scheduler, where it will eventually encounter
2103 a memory barrier, which will force th 1894 a memory barrier, which will force the earlier unlock operation
2104 to complete, again unraveling the dea 1895 to complete, again unraveling the deadlock. There might be
2105 a sleep-unlock race, but the locking 1896 a sleep-unlock race, but the locking primitive needs to resolve
2106 such races properly in any case. 1897 such races properly in any case.
2107 1898
2108 Locks and semaphores may not provide any guar 1899 Locks and semaphores may not provide any guarantee of ordering on UP compiled
2109 systems, and so cannot be counted on in such 1900 systems, and so cannot be counted on in such a situation to actually achieve
2110 anything at all - especially with respect to 1901 anything at all - especially with respect to I/O accesses - unless combined
2111 with interrupt disabling operations. 1902 with interrupt disabling operations.
2112 1903
2113 See also the section on "Inter-CPU acquiring !! 1904 See also the section on "Inter-CPU locking barrier effects".
2114 1905
2115 1906
2116 As an example, consider the following: 1907 As an example, consider the following:
2117 1908
2118 *A = a; 1909 *A = a;
2119 *B = b; 1910 *B = b;
2120 ACQUIRE 1911 ACQUIRE
2121 *C = c; 1912 *C = c;
2122 *D = d; 1913 *D = d;
2123 RELEASE 1914 RELEASE
2124 *E = e; 1915 *E = e;
2125 *F = f; 1916 *F = f;
2126 1917
2127 The following sequence of events is acceptabl 1918 The following sequence of events is acceptable:
2128 1919
2129 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RE 1920 ACQUIRE, {*F,*A}, *E, {*C,*D}, *B, RELEASE
2130 1921
2131 [+] Note that {*F,*A} indicates a com 1922 [+] Note that {*F,*A} indicates a combined access.
2132 1923
2133 But none of the following are: 1924 But none of the following are:
2134 1925
2135 {*F,*A}, *B, ACQUIRE, *C, *D, 1926 {*F,*A}, *B, ACQUIRE, *C, *D, RELEASE, *E
2136 *A, *B, *C, ACQUIRE, *D, 1927 *A, *B, *C, ACQUIRE, *D, RELEASE, *E, *F
2137 *A, *B, ACQUIRE, *C, 1928 *A, *B, ACQUIRE, *C, RELEASE, *D, *E, *F
2138 *B, ACQUIRE, *C, *D, 1929 *B, ACQUIRE, *C, *D, RELEASE, {*F,*A}, *E
2139 1930
2140 1931
2141 1932
2142 INTERRUPT DISABLING FUNCTIONS 1933 INTERRUPT DISABLING FUNCTIONS
2143 ----------------------------- 1934 -----------------------------
2144 1935
2145 Functions that disable interrupts (ACQUIRE eq 1936 Functions that disable interrupts (ACQUIRE equivalent) and enable interrupts
2146 (RELEASE equivalent) will act as compiler bar 1937 (RELEASE equivalent) will act as compiler barriers only. So if memory or I/O
2147 barriers are required in such a situation, th 1938 barriers are required in such a situation, they must be provided from some
2148 other means. 1939 other means.
2149 1940
2150 1941
2151 SLEEP AND WAKE-UP FUNCTIONS 1942 SLEEP AND WAKE-UP FUNCTIONS
2152 --------------------------- 1943 ---------------------------
2153 1944
2154 Sleeping and waking on an event flagged in gl 1945 Sleeping and waking on an event flagged in global data can be viewed as an
2155 interaction between two pieces of data: the t 1946 interaction between two pieces of data: the task state of the task waiting for
2156 the event and the global data used to indicat 1947 the event and the global data used to indicate the event. To make sure that
2157 these appear to happen in the right order, th 1948 these appear to happen in the right order, the primitives to begin the process
2158 of going to sleep, and the primitives to init 1949 of going to sleep, and the primitives to initiate a wake up imply certain
2159 barriers. 1950 barriers.
2160 1951
2161 Firstly, the sleeper normally follows somethi 1952 Firstly, the sleeper normally follows something like this sequence of events:
2162 1953
2163 for (;;) { 1954 for (;;) {
2164 set_current_state(TASK_UNINTE 1955 set_current_state(TASK_UNINTERRUPTIBLE);
2165 if (event_indicated) 1956 if (event_indicated)
2166 break; 1957 break;
2167 schedule(); 1958 schedule();
2168 } 1959 }
2169 1960
2170 A general memory barrier is interpolated auto 1961 A general memory barrier is interpolated automatically by set_current_state()
2171 after it has altered the task state: 1962 after it has altered the task state:
2172 1963
2173 CPU 1 1964 CPU 1
2174 =============================== 1965 ===============================
2175 set_current_state(); 1966 set_current_state();
2176 smp_store_mb(); 1967 smp_store_mb();
2177 STORE current->state 1968 STORE current->state
2178 <general barrier> 1969 <general barrier>
2179 LOAD event_indicated 1970 LOAD event_indicated
2180 1971
2181 set_current_state() may be wrapped by: 1972 set_current_state() may be wrapped by:
2182 1973
2183 prepare_to_wait(); 1974 prepare_to_wait();
2184 prepare_to_wait_exclusive(); 1975 prepare_to_wait_exclusive();
2185 1976
2186 which therefore also imply a general memory b 1977 which therefore also imply a general memory barrier after setting the state.
2187 The whole sequence above is available in vari 1978 The whole sequence above is available in various canned forms, all of which
2188 interpolate the memory barrier in the right p 1979 interpolate the memory barrier in the right place:
2189 1980
2190 wait_event(); 1981 wait_event();
2191 wait_event_interruptible(); 1982 wait_event_interruptible();
2192 wait_event_interruptible_exclusive(); 1983 wait_event_interruptible_exclusive();
2193 wait_event_interruptible_timeout(); 1984 wait_event_interruptible_timeout();
2194 wait_event_killable(); 1985 wait_event_killable();
2195 wait_event_timeout(); 1986 wait_event_timeout();
2196 wait_on_bit(); 1987 wait_on_bit();
2197 wait_on_bit_lock(); 1988 wait_on_bit_lock();
2198 1989
2199 1990
2200 Secondly, code that performs a wake up normal 1991 Secondly, code that performs a wake up normally follows something like this:
2201 1992
2202 event_indicated = 1; 1993 event_indicated = 1;
2203 wake_up(&event_wait_queue); 1994 wake_up(&event_wait_queue);
2204 1995
2205 or: 1996 or:
2206 1997
2207 event_indicated = 1; 1998 event_indicated = 1;
2208 wake_up_process(event_daemon); 1999 wake_up_process(event_daemon);
2209 2000
2210 A general memory barrier is executed by wake_ !! 2001 A write memory barrier is implied by wake_up() and co. if and only if they wake
2211 If it doesn't wake anything up then a memory !! 2002 something up. The barrier occurs before the task state is cleared, and so sits
2212 executed; you must not rely on it. The barri !! 2003 between the STORE to indicate the event and the STORE to set TASK_RUNNING:
2213 is accessed, in particular, it sits between t <<
2214 and the STORE to set TASK_RUNNING: <<
2215 2004
2216 CPU 1 (Sleeper) CPU 2 !! 2005 CPU 1 CPU 2
2217 =============================== ===== 2006 =============================== ===============================
2218 set_current_state(); STORE 2007 set_current_state(); STORE event_indicated
2219 smp_store_mb(); wake_ 2008 smp_store_mb(); wake_up();
2220 STORE current->state ... !! 2009 STORE current->state <write barrier>
2221 <general barrier> <ge !! 2010 <general barrier> STORE current->state
2222 LOAD event_indicated if !! 2011 LOAD event_indicated
2223 S !! 2012
2224 !! 2013 To repeat, this write memory barrier is present if and only if something
2225 where "task" is the thread being woken up and !! 2014 is actually awakened. To see this, consider the following sequence of
2226 !! 2015 events, where X and Y are both initially zero:
2227 To repeat, a general memory barrier is guaran <<
2228 if something is actually awakened, but otherw <<
2229 To see this, consider the following sequence <<
2230 initially zero: <<
2231 2016
2232 CPU 1 CPU 2 2017 CPU 1 CPU 2
2233 =============================== ===== 2018 =============================== ===============================
2234 X = 1; Y = 1 !! 2019 X = 1; STORE event_indicated
2235 smp_mb(); wake_ 2020 smp_mb(); wake_up();
2236 LOAD Y LOAD !! 2021 Y = 1; wait_event(wq, Y == 1);
2237 !! 2022 wake_up(); load from Y sees 1, no memory barrier
2238 If a wakeup does occur, one (at least) of the !! 2023 load from X might see 0
2239 the other hand, a wakeup does not occur, both <<
2240 2024
2241 wake_up_process() always executes a general m !! 2025 In contrast, if a wakeup does occur, CPU 2's load from X would be guaranteed
2242 occurs before the task state is accessed. In !! 2026 to see 1.
2243 the previous snippet were replaced by a call <<
2244 the two loads would be guaranteed to see 1. <<
2245 2027
2246 The available waker functions include: 2028 The available waker functions include:
2247 2029
2248 complete(); 2030 complete();
2249 wake_up(); 2031 wake_up();
2250 wake_up_all(); 2032 wake_up_all();
2251 wake_up_bit(); 2033 wake_up_bit();
2252 wake_up_interruptible(); 2034 wake_up_interruptible();
2253 wake_up_interruptible_all(); 2035 wake_up_interruptible_all();
2254 wake_up_interruptible_nr(); 2036 wake_up_interruptible_nr();
2255 wake_up_interruptible_poll(); 2037 wake_up_interruptible_poll();
2256 wake_up_interruptible_sync(); 2038 wake_up_interruptible_sync();
2257 wake_up_interruptible_sync_poll(); 2039 wake_up_interruptible_sync_poll();
2258 wake_up_locked(); 2040 wake_up_locked();
2259 wake_up_locked_poll(); 2041 wake_up_locked_poll();
2260 wake_up_nr(); 2042 wake_up_nr();
2261 wake_up_poll(); 2043 wake_up_poll();
2262 wake_up_process(); 2044 wake_up_process();
2263 2045
2264 In terms of memory ordering, these functions <<
2265 a wake_up() (or stronger). <<
2266 2046
2267 [!] Note that the memory barriers implied by 2047 [!] Note that the memory barriers implied by the sleeper and the waker do _not_
2268 order multiple stores before the wake-up with 2048 order multiple stores before the wake-up with respect to loads of those stored
2269 values after the sleeper has called set_curre 2049 values after the sleeper has called set_current_state(). For instance, if the
2270 sleeper does: 2050 sleeper does:
2271 2051
2272 set_current_state(TASK_INTERRUPTIBLE) 2052 set_current_state(TASK_INTERRUPTIBLE);
2273 if (event_indicated) 2053 if (event_indicated)
2274 break; 2054 break;
2275 __set_current_state(TASK_RUNNING); 2055 __set_current_state(TASK_RUNNING);
2276 do_something(my_data); 2056 do_something(my_data);
2277 2057
2278 and the waker does: 2058 and the waker does:
2279 2059
2280 my_data = value; 2060 my_data = value;
2281 event_indicated = 1; 2061 event_indicated = 1;
2282 wake_up(&event_wait_queue); 2062 wake_up(&event_wait_queue);
2283 2063
2284 there's no guarantee that the change to event 2064 there's no guarantee that the change to event_indicated will be perceived by
2285 the sleeper as coming after the change to my_ 2065 the sleeper as coming after the change to my_data. In such a circumstance, the
2286 code on both sides must interpolate its own m 2066 code on both sides must interpolate its own memory barriers between the
2287 separate data accesses. Thus the above sleep 2067 separate data accesses. Thus the above sleeper ought to do:
2288 2068
2289 set_current_state(TASK_INTERRUPTIBLE) 2069 set_current_state(TASK_INTERRUPTIBLE);
2290 if (event_indicated) { 2070 if (event_indicated) {
2291 smp_rmb(); 2071 smp_rmb();
2292 do_something(my_data); 2072 do_something(my_data);
2293 } 2073 }
2294 2074
2295 and the waker should do: 2075 and the waker should do:
2296 2076
2297 my_data = value; 2077 my_data = value;
2298 smp_wmb(); 2078 smp_wmb();
2299 event_indicated = 1; 2079 event_indicated = 1;
2300 wake_up(&event_wait_queue); 2080 wake_up(&event_wait_queue);
2301 2081
2302 2082
2303 MISCELLANEOUS FUNCTIONS 2083 MISCELLANEOUS FUNCTIONS
2304 ----------------------- 2084 -----------------------
2305 2085
2306 Other functions that imply barriers: 2086 Other functions that imply barriers:
2307 2087
2308 (*) schedule() and similar imply full memory 2088 (*) schedule() and similar imply full memory barriers.
2309 2089
2310 2090
2311 =================================== 2091 ===================================
2312 INTER-CPU ACQUIRING BARRIER EFFECTS 2092 INTER-CPU ACQUIRING BARRIER EFFECTS
2313 =================================== 2093 ===================================
2314 2094
2315 On SMP systems locking primitives give a more 2095 On SMP systems locking primitives give a more substantial form of barrier: one
2316 that does affect memory access ordering on ot 2096 that does affect memory access ordering on other CPUs, within the context of
2317 conflict on any particular lock. 2097 conflict on any particular lock.
2318 2098
2319 2099
2320 ACQUIRES VS MEMORY ACCESSES 2100 ACQUIRES VS MEMORY ACCESSES
2321 --------------------------- 2101 ---------------------------
2322 2102
2323 Consider the following: the system has a pair 2103 Consider the following: the system has a pair of spinlocks (M) and (Q), and
2324 three CPUs; then should the following sequenc 2104 three CPUs; then should the following sequence of events occur:
2325 2105
2326 CPU 1 CPU 2 2106 CPU 1 CPU 2
2327 =============================== ===== 2107 =============================== ===============================
2328 WRITE_ONCE(*A, a); WRITE 2108 WRITE_ONCE(*A, a); WRITE_ONCE(*E, e);
2329 ACQUIRE M ACQUI 2109 ACQUIRE M ACQUIRE Q
2330 WRITE_ONCE(*B, b); WRITE 2110 WRITE_ONCE(*B, b); WRITE_ONCE(*F, f);
2331 WRITE_ONCE(*C, c); WRITE 2111 WRITE_ONCE(*C, c); WRITE_ONCE(*G, g);
2332 RELEASE M RELEA 2112 RELEASE M RELEASE Q
2333 WRITE_ONCE(*D, d); WRITE 2113 WRITE_ONCE(*D, d); WRITE_ONCE(*H, h);
2334 2114
2335 Then there is no guarantee as to what order C 2115 Then there is no guarantee as to what order CPU 3 will see the accesses to *A
2336 through *H occur in, other than the constrain 2116 through *H occur in, other than the constraints imposed by the separate locks
2337 on the separate CPUs. It might, for example, !! 2117 on the separate CPUs. It might, for example, see:
2338 2118
2339 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, 2119 *E, ACQUIRE M, ACQUIRE Q, *G, *C, *F, *A, *B, RELEASE Q, *D, *H, RELEASE M
2340 2120
2341 But it won't see any of: 2121 But it won't see any of:
2342 2122
2343 *B, *C or *D preceding ACQUIRE M 2123 *B, *C or *D preceding ACQUIRE M
2344 *A, *B or *C following RELEASE M 2124 *A, *B or *C following RELEASE M
2345 *F, *G or *H preceding ACQUIRE Q 2125 *F, *G or *H preceding ACQUIRE Q
2346 *E, *F or *G following RELEASE Q 2126 *E, *F or *G following RELEASE Q
2347 2127
2348 2128
>> 2129
>> 2130 ACQUIRES VS I/O ACCESSES
>> 2131 ------------------------
>> 2132
>> 2133 Under certain circumstances (especially involving NUMA), I/O accesses within
>> 2134 two spinlocked sections on two different CPUs may be seen as interleaved by the
>> 2135 PCI bridge, because the PCI bridge does not necessarily participate in the
>> 2136 cache-coherence protocol, and is therefore incapable of issuing the required
>> 2137 read memory barriers.
>> 2138
>> 2139 For example:
>> 2140
>> 2141 CPU 1 CPU 2
>> 2142 =============================== ===============================
>> 2143 spin_lock(Q)
>> 2144 writel(0, ADDR)
>> 2145 writel(1, DATA);
>> 2146 spin_unlock(Q);
>> 2147 spin_lock(Q);
>> 2148 writel(4, ADDR);
>> 2149 writel(5, DATA);
>> 2150 spin_unlock(Q);
>> 2151
>> 2152 may be seen by the PCI bridge as follows:
>> 2153
>> 2154 STORE *ADDR = 0, STORE *ADDR = 4, STORE *DATA = 1, STORE *DATA = 5
>> 2155
>> 2156 which would probably cause the hardware to malfunction.
>> 2157
>> 2158
>> 2159 What is necessary here is to intervene with an mmiowb() before dropping the
>> 2160 spinlock, for example:
>> 2161
>> 2162 CPU 1 CPU 2
>> 2163 =============================== ===============================
>> 2164 spin_lock(Q)
>> 2165 writel(0, ADDR)
>> 2166 writel(1, DATA);
>> 2167 mmiowb();
>> 2168 spin_unlock(Q);
>> 2169 spin_lock(Q);
>> 2170 writel(4, ADDR);
>> 2171 writel(5, DATA);
>> 2172 mmiowb();
>> 2173 spin_unlock(Q);
>> 2174
>> 2175 this will ensure that the two stores issued on CPU 1 appear at the PCI bridge
>> 2176 before either of the stores issued on CPU 2.
>> 2177
>> 2178
>> 2179 Furthermore, following a store by a load from the same device obviates the need
>> 2180 for the mmiowb(), because the load forces the store to complete before the load
>> 2181 is performed:
>> 2182
>> 2183 CPU 1 CPU 2
>> 2184 =============================== ===============================
>> 2185 spin_lock(Q)
>> 2186 writel(0, ADDR)
>> 2187 a = readl(DATA);
>> 2188 spin_unlock(Q);
>> 2189 spin_lock(Q);
>> 2190 writel(4, ADDR);
>> 2191 b = readl(DATA);
>> 2192 spin_unlock(Q);
>> 2193
>> 2194
>> 2195 See Documentation/DocBook/deviceiobook.tmpl for more information.
>> 2196
>> 2197
2349 ================================= 2198 =================================
2350 WHERE ARE MEMORY BARRIERS NEEDED? 2199 WHERE ARE MEMORY BARRIERS NEEDED?
2351 ================================= 2200 =================================
2352 2201
2353 Under normal operation, memory operation reor 2202 Under normal operation, memory operation reordering is generally not going to
2354 be a problem as a single-threaded linear piec 2203 be a problem as a single-threaded linear piece of code will still appear to
2355 work correctly, even if it's in an SMP kernel 2204 work correctly, even if it's in an SMP kernel. There are, however, four
2356 circumstances in which reordering definitely 2205 circumstances in which reordering definitely _could_ be a problem:
2357 2206
2358 (*) Interprocessor interaction. 2207 (*) Interprocessor interaction.
2359 2208
2360 (*) Atomic operations. 2209 (*) Atomic operations.
2361 2210
2362 (*) Accessing devices. 2211 (*) Accessing devices.
2363 2212
2364 (*) Interrupts. 2213 (*) Interrupts.
2365 2214
2366 2215
2367 INTERPROCESSOR INTERACTION 2216 INTERPROCESSOR INTERACTION
2368 -------------------------- 2217 --------------------------
2369 2218
2370 When there's a system with more than one proc 2219 When there's a system with more than one processor, more than one CPU in the
2371 system may be working on the same data set at 2220 system may be working on the same data set at the same time. This can cause
2372 synchronisation problems, and the usual way o 2221 synchronisation problems, and the usual way of dealing with them is to use
2373 locks. Locks, however, are quite expensive, 2222 locks. Locks, however, are quite expensive, and so it may be preferable to
2374 operate without the use of a lock if at all p 2223 operate without the use of a lock if at all possible. In such a case
2375 operations that affect both CPUs may have to 2224 operations that affect both CPUs may have to be carefully ordered to prevent
2376 a malfunction. 2225 a malfunction.
2377 2226
2378 Consider, for example, the R/W semaphore slow 2227 Consider, for example, the R/W semaphore slow path. Here a waiting process is
2379 queued on the semaphore, by virtue of it havi 2228 queued on the semaphore, by virtue of it having a piece of its stack linked to
2380 the semaphore's list of waiting processes: 2229 the semaphore's list of waiting processes:
2381 2230
2382 struct rw_semaphore { 2231 struct rw_semaphore {
2383 ... 2232 ...
2384 spinlock_t lock; 2233 spinlock_t lock;
2385 struct list_head waiters; 2234 struct list_head waiters;
2386 }; 2235 };
2387 2236
2388 struct rwsem_waiter { 2237 struct rwsem_waiter {
2389 struct list_head list; 2238 struct list_head list;
2390 struct task_struct *task; 2239 struct task_struct *task;
2391 }; 2240 };
2392 2241
2393 To wake up a particular waiter, the up_read() 2242 To wake up a particular waiter, the up_read() or up_write() functions have to:
2394 2243
2395 (1) read the next pointer from this waiter's 2244 (1) read the next pointer from this waiter's record to know as to where the
2396 next waiter record is; 2245 next waiter record is;
2397 2246
2398 (2) read the pointer to the waiter's task st 2247 (2) read the pointer to the waiter's task structure;
2399 2248
2400 (3) clear the task pointer to tell the waite 2249 (3) clear the task pointer to tell the waiter it has been given the semaphore;
2401 2250
2402 (4) call wake_up_process() on the task; and 2251 (4) call wake_up_process() on the task; and
2403 2252
2404 (5) release the reference held on the waiter 2253 (5) release the reference held on the waiter's task struct.
2405 2254
2406 In other words, it has to perform this sequen 2255 In other words, it has to perform this sequence of events:
2407 2256
2408 LOAD waiter->list.next; 2257 LOAD waiter->list.next;
2409 LOAD waiter->task; 2258 LOAD waiter->task;
2410 STORE waiter->task; 2259 STORE waiter->task;
2411 CALL wakeup 2260 CALL wakeup
2412 RELEASE task 2261 RELEASE task
2413 2262
2414 and if any of these steps occur out of order, 2263 and if any of these steps occur out of order, then the whole thing may
2415 malfunction. 2264 malfunction.
2416 2265
2417 Once it has queued itself and dropped the sem 2266 Once it has queued itself and dropped the semaphore lock, the waiter does not
2418 get the lock again; it instead just waits for 2267 get the lock again; it instead just waits for its task pointer to be cleared
2419 before proceeding. Since the record is on th 2268 before proceeding. Since the record is on the waiter's stack, this means that
2420 if the task pointer is cleared _before_ the n 2269 if the task pointer is cleared _before_ the next pointer in the list is read,
2421 another CPU might start processing the waiter 2270 another CPU might start processing the waiter and might clobber the waiter's
2422 stack before the up*() function has a chance 2271 stack before the up*() function has a chance to read the next pointer.
2423 2272
2424 Consider then what might happen to the above 2273 Consider then what might happen to the above sequence of events:
2425 2274
2426 CPU 1 CPU 2 2275 CPU 1 CPU 2
2427 =============================== ===== 2276 =============================== ===============================
2428 down_ 2277 down_xxx()
2429 Queue 2278 Queue waiter
2430 Sleep 2279 Sleep
2431 up_yyy() 2280 up_yyy()
2432 LOAD waiter->task; 2281 LOAD waiter->task;
2433 STORE waiter->task; 2282 STORE waiter->task;
2434 Woken 2283 Woken up by other event
2435 <preempt> 2284 <preempt>
2436 Resum 2285 Resume processing
2437 down_ 2286 down_xxx() returns
2438 call 2287 call foo()
2439 foo() 2288 foo() clobbers *waiter
2440 </preempt> 2289 </preempt>
2441 LOAD waiter->list.next; 2290 LOAD waiter->list.next;
2442 --- OOPS --- 2291 --- OOPS ---
2443 2292
2444 This could be dealt with using the semaphore 2293 This could be dealt with using the semaphore lock, but then the down_xxx()
2445 function has to needlessly get the spinlock a 2294 function has to needlessly get the spinlock again after being woken up.
2446 2295
2447 The way to deal with this is to insert a gene 2296 The way to deal with this is to insert a general SMP memory barrier:
2448 2297
2449 LOAD waiter->list.next; 2298 LOAD waiter->list.next;
2450 LOAD waiter->task; 2299 LOAD waiter->task;
2451 smp_mb(); 2300 smp_mb();
2452 STORE waiter->task; 2301 STORE waiter->task;
2453 CALL wakeup 2302 CALL wakeup
2454 RELEASE task 2303 RELEASE task
2455 2304
2456 In this case, the barrier makes a guarantee t 2305 In this case, the barrier makes a guarantee that all memory accesses before the
2457 barrier will appear to happen before all the 2306 barrier will appear to happen before all the memory accesses after the barrier
2458 with respect to the other CPUs on the system. 2307 with respect to the other CPUs on the system. It does _not_ guarantee that all
2459 the memory accesses before the barrier will b 2308 the memory accesses before the barrier will be complete by the time the barrier
2460 instruction itself is complete. 2309 instruction itself is complete.
2461 2310
2462 On a UP system - where this wouldn't be a pro 2311 On a UP system - where this wouldn't be a problem - the smp_mb() is just a
2463 compiler barrier, thus making sure the compil 2312 compiler barrier, thus making sure the compiler emits the instructions in the
2464 right order without actually intervening in t 2313 right order without actually intervening in the CPU. Since there's only one
2465 CPU, that CPU's dependency ordering logic wil 2314 CPU, that CPU's dependency ordering logic will take care of everything else.
2466 2315
2467 2316
2468 ATOMIC OPERATIONS 2317 ATOMIC OPERATIONS
2469 ----------------- 2318 -----------------
2470 2319
2471 While they are technically interprocessor int !! 2320 Whilst they are technically interprocessor interaction considerations, atomic
2472 operations are noted specially as some of the 2321 operations are noted specially as some of them imply full memory barriers and
2473 some don't, but they're very heavily relied o 2322 some don't, but they're very heavily relied on as a group throughout the
2474 kernel. 2323 kernel.
2475 2324
2476 See Documentation/atomic_t.txt for more infor !! 2325 Any atomic operation that modifies some state in memory and returns information
>> 2326 about the state (old or new) implies an SMP-conditional general memory barrier
>> 2327 (smp_mb()) on each side of the actual operation (with the exception of
>> 2328 explicit lock operations, described later). These include:
>> 2329
>> 2330 xchg();
>> 2331 atomic_xchg(); atomic_long_xchg();
>> 2332 atomic_inc_return(); atomic_long_inc_return();
>> 2333 atomic_dec_return(); atomic_long_dec_return();
>> 2334 atomic_add_return(); atomic_long_add_return();
>> 2335 atomic_sub_return(); atomic_long_sub_return();
>> 2336 atomic_inc_and_test(); atomic_long_inc_and_test();
>> 2337 atomic_dec_and_test(); atomic_long_dec_and_test();
>> 2338 atomic_sub_and_test(); atomic_long_sub_and_test();
>> 2339 atomic_add_negative(); atomic_long_add_negative();
>> 2340 test_and_set_bit();
>> 2341 test_and_clear_bit();
>> 2342 test_and_change_bit();
>> 2343
>> 2344 /* when succeeds */
>> 2345 cmpxchg();
>> 2346 atomic_cmpxchg(); atomic_long_cmpxchg();
>> 2347 atomic_add_unless(); atomic_long_add_unless();
>> 2348
>> 2349 These are used for such things as implementing ACQUIRE-class and RELEASE-class
>> 2350 operations and adjusting reference counters towards object destruction, and as
>> 2351 such the implicit memory barrier effects are necessary.
>> 2352
>> 2353
>> 2354 The following operations are potential problems as they do _not_ imply memory
>> 2355 barriers, but might be used for implementing such things as RELEASE-class
>> 2356 operations:
>> 2357
>> 2358 atomic_set();
>> 2359 set_bit();
>> 2360 clear_bit();
>> 2361 change_bit();
>> 2362
>> 2363 With these the appropriate explicit memory barrier should be used if necessary
>> 2364 (smp_mb__before_atomic() for instance).
>> 2365
>> 2366
>> 2367 The following also do _not_ imply memory barriers, and so may require explicit
>> 2368 memory barriers under some circumstances (smp_mb__before_atomic() for
>> 2369 instance):
>> 2370
>> 2371 atomic_add();
>> 2372 atomic_sub();
>> 2373 atomic_inc();
>> 2374 atomic_dec();
>> 2375
>> 2376 If they're used for statistics generation, then they probably don't need memory
>> 2377 barriers, unless there's a coupling between statistical data.
>> 2378
>> 2379 If they're used for reference counting on an object to control its lifetime,
>> 2380 they probably don't need memory barriers because either the reference count
>> 2381 will be adjusted inside a locked section, or the caller will already hold
>> 2382 sufficient references to make the lock, and thus a memory barrier unnecessary.
>> 2383
>> 2384 If they're used for constructing a lock of some description, then they probably
>> 2385 do need memory barriers as a lock primitive generally has to do things in a
>> 2386 specific order.
>> 2387
>> 2388 Basically, each usage case has to be carefully considered as to whether memory
>> 2389 barriers are needed or not.
>> 2390
>> 2391 The following operations are special locking primitives:
>> 2392
>> 2393 test_and_set_bit_lock();
>> 2394 clear_bit_unlock();
>> 2395 __clear_bit_unlock();
>> 2396
>> 2397 These implement ACQUIRE-class and RELEASE-class operations. These should be used in
>> 2398 preference to other operations when implementing locking primitives, because
>> 2399 their implementations can be optimised on many architectures.
>> 2400
>> 2401 [!] Note that special memory barrier primitives are available for these
>> 2402 situations because on some CPUs the atomic instructions used imply full memory
>> 2403 barriers, and so barrier instructions are superfluous in conjunction with them,
>> 2404 and in such cases the special barrier primitives will be no-ops.
>> 2405
>> 2406 See Documentation/atomic_ops.txt for more information.
2477 2407
2478 2408
2479 ACCESSING DEVICES 2409 ACCESSING DEVICES
2480 ----------------- 2410 -----------------
2481 2411
2482 Many devices can be memory mapped, and so app 2412 Many devices can be memory mapped, and so appear to the CPU as if they're just
2483 a set of memory locations. To control such a 2413 a set of memory locations. To control such a device, the driver usually has to
2484 make the right memory accesses in exactly the 2414 make the right memory accesses in exactly the right order.
2485 2415
2486 However, having a clever CPU or a clever comp 2416 However, having a clever CPU or a clever compiler creates a potential problem
2487 in that the carefully sequenced accesses in t 2417 in that the carefully sequenced accesses in the driver code won't reach the
2488 device in the requisite order if the CPU or t 2418 device in the requisite order if the CPU or the compiler thinks it is more
2489 efficient to reorder, combine or merge access 2419 efficient to reorder, combine or merge accesses - something that would cause
2490 the device to malfunction. 2420 the device to malfunction.
2491 2421
2492 Inside of the Linux kernel, I/O should be don 2422 Inside of the Linux kernel, I/O should be done through the appropriate accessor
2493 routines - such as inb() or writel() - which 2423 routines - such as inb() or writel() - which know how to make such accesses
2494 appropriately sequential. While this, for th !! 2424 appropriately sequential. Whilst this, for the most part, renders the explicit
2495 use of memory barriers unnecessary, if the ac !! 2425 use of memory barriers unnecessary, there are a couple of situations where they
2496 to an I/O memory window with relaxed memory a !! 2426 might be needed:
2497 memory barriers are required to enforce order !! 2427
>> 2428 (1) On some systems, I/O stores are not strongly ordered across all CPUs, and
>> 2429 so for _all_ general drivers locks should be used and mmiowb() must be
>> 2430 issued prior to unlocking the critical section.
>> 2431
>> 2432 (2) If the accessor functions are used to refer to an I/O memory window with
>> 2433 relaxed memory access properties, then _mandatory_ memory barriers are
>> 2434 required to enforce ordering.
2498 2435
2499 See Documentation/driver-api/device-io.rst fo !! 2436 See Documentation/DocBook/deviceiobook.tmpl for more information.
2500 2437
2501 2438
2502 INTERRUPTS 2439 INTERRUPTS
2503 ---------- 2440 ----------
2504 2441
2505 A driver may be interrupted by its own interr 2442 A driver may be interrupted by its own interrupt service routine, and thus the
2506 two parts of the driver may interfere with ea 2443 two parts of the driver may interfere with each other's attempts to control or
2507 access the device. 2444 access the device.
2508 2445
2509 This may be alleviated - at least in part - b 2446 This may be alleviated - at least in part - by disabling local interrupts (a
2510 form of locking), such that the critical oper 2447 form of locking), such that the critical operations are all contained within
2511 the interrupt-disabled section in the driver. !! 2448 the interrupt-disabled section in the driver. Whilst the driver's interrupt
2512 routine is executing, the driver's core may n 2449 routine is executing, the driver's core may not run on the same CPU, and its
2513 interrupt is not permitted to happen again un 2450 interrupt is not permitted to happen again until the current interrupt has been
2514 handled, thus the interrupt handler does not 2451 handled, thus the interrupt handler does not need to lock against that.
2515 2452
2516 However, consider a driver that was talking t 2453 However, consider a driver that was talking to an ethernet card that sports an
2517 address register and a data register. If tha 2454 address register and a data register. If that driver's core talks to the card
2518 under interrupt-disablement and then the driv 2455 under interrupt-disablement and then the driver's interrupt handler is invoked:
2519 2456
2520 LOCAL IRQ DISABLE 2457 LOCAL IRQ DISABLE
2521 writew(ADDR, 3); 2458 writew(ADDR, 3);
2522 writew(DATA, y); 2459 writew(DATA, y);
2523 LOCAL IRQ ENABLE 2460 LOCAL IRQ ENABLE
2524 <interrupt> 2461 <interrupt>
2525 writew(ADDR, 4); 2462 writew(ADDR, 4);
2526 q = readw(DATA); 2463 q = readw(DATA);
2527 </interrupt> 2464 </interrupt>
2528 2465
2529 The store to the data register might happen a 2466 The store to the data register might happen after the second store to the
2530 address register if ordering rules are suffic 2467 address register if ordering rules are sufficiently relaxed:
2531 2468
2532 STORE *ADDR = 3, STORE *ADDR = 4, STO 2469 STORE *ADDR = 3, STORE *ADDR = 4, STORE *DATA = y, q = LOAD *DATA
2533 2470
2534 2471
2535 If ordering rules are relaxed, it must be ass 2472 If ordering rules are relaxed, it must be assumed that accesses done inside an
2536 interrupt disabled section may leak outside o 2473 interrupt disabled section may leak outside of it and may interleave with
2537 accesses performed in an interrupt - and vice 2474 accesses performed in an interrupt - and vice versa - unless implicit or
2538 explicit barriers are used. 2475 explicit barriers are used.
2539 2476
2540 Normally this won't be a problem because the 2477 Normally this won't be a problem because the I/O accesses done inside such
2541 sections will include synchronous load operat 2478 sections will include synchronous load operations on strictly ordered I/O
2542 registers that form implicit I/O barriers. !! 2479 registers that form implicit I/O barriers. If this isn't sufficient then an
>> 2480 mmiowb() may need to be used explicitly.
2543 2481
2544 2482
2545 A similar situation may occur between an inte 2483 A similar situation may occur between an interrupt routine and two routines
2546 running on separate CPUs that communicate wit !! 2484 running on separate CPUs that communicate with each other. If such a case is
2547 likely, then interrupt-disabling locks should 2485 likely, then interrupt-disabling locks should be used to guarantee ordering.
2548 2486
2549 2487
2550 ========================== 2488 ==========================
2551 KERNEL I/O BARRIER EFFECTS 2489 KERNEL I/O BARRIER EFFECTS
2552 ========================== 2490 ==========================
2553 2491
2554 Interfacing with peripherals via I/O accesses !! 2492 When accessing I/O memory, drivers should use the appropriate accessor
2555 specific. Therefore, drivers which are inhere !! 2493 functions:
2556 specific behaviours of their target systems i !! 2494
2557 in the most lightweight manner possible. For !! 2495 (*) inX(), outX():
2558 between multiple architectures and bus implem !! 2496
2559 series of accessor functions that provide var !! 2497 These are intended to talk to I/O space rather than memory space, but
2560 guarantees: !! 2498 that's primarily a CPU-specific concept. The i386 and x86_64 processors do
>> 2499 indeed have special I/O space access cycles and instructions, but many
>> 2500 CPUs don't have such a concept.
>> 2501
>> 2502 The PCI bus, amongst others, defines an I/O space concept which - on such
>> 2503 CPUs as i386 and x86_64 - readily maps to the CPU's concept of I/O
>> 2504 space. However, it may also be mapped as a virtual I/O space in the CPU's
>> 2505 memory map, particularly on those CPUs that don't support alternate I/O
>> 2506 spaces.
>> 2507
>> 2508 Accesses to this space may be fully synchronous (as on i386), but
>> 2509 intermediary bridges (such as the PCI host bridge) may not fully honour
>> 2510 that.
>> 2511
>> 2512 They are guaranteed to be fully ordered with respect to each other.
>> 2513
>> 2514 They are not guaranteed to be fully ordered with respect to other types of
>> 2515 memory and I/O operation.
2561 2516
2562 (*) readX(), writeX(): 2517 (*) readX(), writeX():
2563 2518
2564 The readX() and writeX() MMIO accesso !! 2519 Whether these are guaranteed to be fully ordered and uncombined with
2565 peripheral being accessed as an __iom !! 2520 respect to each other on the issuing CPU depends on the characteristics
2566 mapped with the default I/O attribute !! 2521 defined for the memory window through which they're accessing. On later
2567 ioremap()), the ordering guarantees a !! 2522 i386 architecture machines, for example, this is controlled by way of the
2568 !! 2523 MTRR registers.
2569 1. All readX() and writeX() accesses !! 2524
2570 with respect to each other. This e !! 2525 Ordinarily, these will be guaranteed to be fully ordered and uncombined,
2571 by the same CPU thread to a partic !! 2526 provided they're not accessing a prefetchable device.
2572 order. !! 2527
2573 !! 2528 However, intermediary hardware (such as a PCI bridge) may indulge in
2574 2. A writeX() issued by a CPU thread !! 2529 deferral if it so wishes; to flush a store, a load from the same location
2575 before a writeX() to the same peri !! 2530 is preferred[*], but a load from the same device or from configuration
2576 issued after a later acquisition o !! 2531 space should suffice for PCI.
2577 that MMIO register writes to a par !! 2532
2578 a spinlock will arrive in an order !! 2533 [*] NOTE! attempting to load from the same location as was written to may
2579 the lock. !! 2534 cause a malfunction - consider the 16550 Rx/Tx serial registers for
2580 !! 2535 example.
2581 3. A writeX() by a CPU thread to the !! 2536
2582 completion of all prior writes to !! 2537 Used with prefetchable I/O memory, an mmiowb() barrier may be required to
2583 propagated to, the same thread. Th !! 2538 force stores to be ordered.
2584 to an outbound DMA buffer allocate !! 2539
2585 visible to a DMA engine when the C !! 2540 Please refer to the PCI specification for more information on interactions
2586 register to trigger the transfer. !! 2541 between PCI transactions.
2587 !! 2542
2588 4. A readX() by a CPU thread from the !! 2543 (*) readX_relaxed(), writeX_relaxed()
2589 any subsequent reads from memory b !! 2544
2590 ensures that reads by the CPU from !! 2545 These are similar to readX() and writeX(), but provide weaker memory
2591 by dma_alloc_coherent() will not s !! 2546 ordering guarantees. Specifically, they do not guarantee ordering with
2592 the DMA engine's MMIO status regis !! 2547 respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee
2593 transfer has completed. !! 2548 ordering with respect to LOCK or UNLOCK operations. If the latter is
2594 !! 2549 required, an mmiowb() barrier can be used. Note that relaxed accesses to
2595 5. A readX() by a CPU thread from the !! 2550 the same peripheral are guaranteed to be ordered with respect to each
2596 any subsequent delay() loop can be !! 2551 other.
2597 This ensures that two MMIO registe <<
2598 will arrive at least 1us apart if <<
2599 back with readX() and udelay(1) is <<
2600 writeX(): <<
2601 <<
2602 writel(42, DEVICE_REGISTER_0) <<
2603 readl(DEVICE_REGISTER_0); <<
2604 udelay(1); <<
2605 writel(42, DEVICE_REGISTER_1) <<
2606 <<
2607 The ordering properties of __iomem po <<
2608 attributes (e.g. those returned by io <<
2609 underlying architecture and therefore <<
2610 generally be relied upon for accesses <<
2611 <<
2612 (*) readX_relaxed(), writeX_relaxed(): <<
2613 <<
2614 These are similar to readX() and writ <<
2615 ordering guarantees. Specifically, th <<
2616 respect to locking, normal memory acc <<
2617 bullets 2-5 above) but they are still <<
2618 respect to other accesses from the sa <<
2619 peripheral when operating on __iomem <<
2620 I/O attributes. <<
2621 <<
2622 (*) readsX(), writesX(): <<
2623 <<
2624 The readsX() and writesX() MMIO acces <<
2625 register-based, memory-mapped FIFOs r <<
2626 capable of performing DMA. Consequent <<
2627 guarantees of readX_relaxed() and wri <<
2628 2552
2629 (*) inX(), outX(): !! 2553 (*) ioreadX(), iowriteX()
2630 2554
2631 The inX() and outX() accessors are in !! 2555 These will perform appropriately for the type of access they're actually
2632 I/O peripherals, which may require sp !! 2556 doing, be it inX()/outX() or readX()/writeX().
2633 architectures (notably x86). The port <<
2634 accessed is passed as an argument. <<
2635 <<
2636 Since many CPU architectures ultimate <<
2637 internal virtual memory mapping, the <<
2638 provided by inX() and outX() are the <<
2639 and writeX() respectively when access <<
2640 attributes. <<
2641 <<
2642 Device drivers may expect outX() to e <<
2643 that waits for a completion response <<
2644 returning. This is not guaranteed by <<
2645 not part of the portable ordering sem <<
2646 <<
2647 (*) insX(), outsX(): <<
2648 <<
2649 As above, the insX() and outsX() acce <<
2650 guarantees as readsX() and writesX() <<
2651 mapping with the default I/O attribut <<
2652 <<
2653 (*) ioreadX(), iowriteX(): <<
2654 <<
2655 These will perform appropriately for <<
2656 doing, be it inX()/outX() or readX()/ <<
2657 <<
2658 With the exception of the string accessors (i <<
2659 writesX()), all of the above assume that the <<
2660 little-endian and will therefore perform byte <<
2661 architectures. <<
2662 2557
2663 2558
2664 ======================================== 2559 ========================================
2665 ASSUMED MINIMUM EXECUTION ORDERING MODEL 2560 ASSUMED MINIMUM EXECUTION ORDERING MODEL
2666 ======================================== 2561 ========================================
2667 2562
2668 It has to be assumed that the conceptual CPU 2563 It has to be assumed that the conceptual CPU is weakly-ordered but that it will
2669 maintain the appearance of program causality 2564 maintain the appearance of program causality with respect to itself. Some CPUs
2670 (such as i386 or x86_64) are more constrained 2565 (such as i386 or x86_64) are more constrained than others (such as powerpc or
2671 frv), and so the most relaxed case (namely DE 2566 frv), and so the most relaxed case (namely DEC Alpha) must be assumed outside
2672 of arch-specific code. 2567 of arch-specific code.
2673 2568
2674 This means that it must be considered that th 2569 This means that it must be considered that the CPU will execute its instruction
2675 stream in any order it feels like - or even i 2570 stream in any order it feels like - or even in parallel - provided that if an
2676 instruction in the stream depends on an earli 2571 instruction in the stream depends on an earlier instruction, then that
2677 earlier instruction must be sufficiently comp 2572 earlier instruction must be sufficiently complete[*] before the later
2678 instruction may proceed; in other words: prov 2573 instruction may proceed; in other words: provided that the appearance of
2679 causality is maintained. 2574 causality is maintained.
2680 2575
2681 [*] Some instructions have more than one eff 2576 [*] Some instructions have more than one effect - such as changing the
2682 condition codes, changing registers or c 2577 condition codes, changing registers or changing memory - and different
2683 instructions may depend on different eff 2578 instructions may depend on different effects.
2684 2579
2685 A CPU may also discard any instruction sequen 2580 A CPU may also discard any instruction sequence that winds up having no
2686 ultimate effect. For example, if two adjacen 2581 ultimate effect. For example, if two adjacent instructions both load an
2687 immediate value into the same register, the f 2582 immediate value into the same register, the first may be discarded.
2688 2583
2689 2584
2690 Similarly, it has to be assumed that compiler 2585 Similarly, it has to be assumed that compiler might reorder the instruction
2691 stream in any way it sees fit, again provided 2586 stream in any way it sees fit, again provided the appearance of causality is
2692 maintained. 2587 maintained.
2693 2588
2694 2589
2695 ============================ 2590 ============================
2696 THE EFFECTS OF THE CPU CACHE 2591 THE EFFECTS OF THE CPU CACHE
2697 ============================ 2592 ============================
2698 2593
2699 The way cached memory operations are perceive 2594 The way cached memory operations are perceived across the system is affected to
2700 a certain extent by the caches that lie betwe 2595 a certain extent by the caches that lie between CPUs and memory, and by the
2701 memory coherence system that maintains the co 2596 memory coherence system that maintains the consistency of state in the system.
2702 2597
2703 As far as the way a CPU interacts with anothe 2598 As far as the way a CPU interacts with another part of the system through the
2704 caches goes, the memory system has to include 2599 caches goes, the memory system has to include the CPU's caches, and memory
2705 barriers for the most part act at the interfa 2600 barriers for the most part act at the interface between the CPU and its cache
2706 (memory barriers logically act on the dotted 2601 (memory barriers logically act on the dotted line in the following diagram):
2707 2602
2708 <--- CPU ---> : <-- 2603 <--- CPU ---> : <----------- Memory ----------->
2709 : 2604 :
2710 +--------+ +--------+ : +------ 2605 +--------+ +--------+ : +--------+ +-----------+
2711 | | | | : | 2606 | | | | : | | | | +--------+
2712 | CPU | | Memory | : | CPU 2607 | CPU | | Memory | : | CPU | | | | |
2713 | Core |--->| Access |----->| Cache 2608 | Core |--->| Access |----->| Cache |<-->| | | |
2714 | | | Queue | : | 2609 | | | Queue | : | | | |--->| Memory |
2715 | | | | : | 2610 | | | | : | | | | | |
2716 +--------+ +--------+ : +------ 2611 +--------+ +--------+ : +--------+ | | | |
2717 : 2612 : | Cache | +--------+
2718 : 2613 : | Coherency |
2719 : 2614 : | Mechanism | +--------+
2720 +--------+ +--------+ : +------ 2615 +--------+ +--------+ : +--------+ | | | |
2721 | | | | : | 2616 | | | | : | | | | | |
2722 | CPU | | Memory | : | CPU 2617 | CPU | | Memory | : | CPU | | |--->| Device |
2723 | Core |--->| Access |----->| Cache 2618 | Core |--->| Access |----->| Cache |<-->| | | |
2724 | | | Queue | : | 2619 | | | Queue | : | | | | | |
2725 | | | | : | 2620 | | | | : | | | | +--------+
2726 +--------+ +--------+ : +------ 2621 +--------+ +--------+ : +--------+ +-----------+
2727 : 2622 :
2728 : 2623 :
2729 2624
2730 Although any particular load or store may not 2625 Although any particular load or store may not actually appear outside of the
2731 CPU that issued it since it may have been sat 2626 CPU that issued it since it may have been satisfied within the CPU's own cache,
2732 it will still appear as if the full memory ac 2627 it will still appear as if the full memory access had taken place as far as the
2733 other CPUs are concerned since the cache cohe 2628 other CPUs are concerned since the cache coherency mechanisms will migrate the
2734 cacheline over to the accessing CPU and propa 2629 cacheline over to the accessing CPU and propagate the effects upon conflict.
2735 2630
2736 The CPU core may execute instructions in any 2631 The CPU core may execute instructions in any order it deems fit, provided the
2737 expected program causality appears to be main 2632 expected program causality appears to be maintained. Some of the instructions
2738 generate load and store operations which then 2633 generate load and store operations which then go into the queue of memory
2739 accesses to be performed. The core may place 2634 accesses to be performed. The core may place these in the queue in any order
2740 it wishes, and continue execution until it is 2635 it wishes, and continue execution until it is forced to wait for an instruction
2741 to complete. 2636 to complete.
2742 2637
2743 What memory barriers are concerned with is co 2638 What memory barriers are concerned with is controlling the order in which
2744 accesses cross from the CPU side of things to 2639 accesses cross from the CPU side of things to the memory side of things, and
2745 the order in which the effects are perceived 2640 the order in which the effects are perceived to happen by the other observers
2746 in the system. 2641 in the system.
2747 2642
2748 [!] Memory barriers are _not_ needed within a 2643 [!] Memory barriers are _not_ needed within a given CPU, as CPUs always see
2749 their own loads and stores as if they had hap 2644 their own loads and stores as if they had happened in program order.
2750 2645
2751 [!] MMIO or other device accesses may bypass 2646 [!] MMIO or other device accesses may bypass the cache system. This depends on
2752 the properties of the memory window through w 2647 the properties of the memory window through which devices are accessed and/or
2753 the use of any special device communication i 2648 the use of any special device communication instructions the CPU may have.
2754 2649
2755 2650
>> 2651 CACHE COHERENCY
>> 2652 ---------------
>> 2653
>> 2654 Life isn't quite as simple as it may appear above, however: for while the
>> 2655 caches are expected to be coherent, there's no guarantee that that coherency
>> 2656 will be ordered. This means that whilst changes made on one CPU will
>> 2657 eventually become visible on all CPUs, there's no guarantee that they will
>> 2658 become apparent in the same order on those other CPUs.
>> 2659
>> 2660
>> 2661 Consider dealing with a system that has a pair of CPUs (1 & 2), each of which
>> 2662 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
>> 2663
>> 2664 :
>> 2665 : +--------+
>> 2666 : +---------+ | |
>> 2667 +--------+ : +--->| Cache A |<------->| |
>> 2668 | | : | +---------+ | |
>> 2669 | CPU 1 |<---+ | |
>> 2670 | | : | +---------+ | |
>> 2671 +--------+ : +--->| Cache B |<------->| |
>> 2672 : +---------+ | |
>> 2673 : | Memory |
>> 2674 : +---------+ | System |
>> 2675 +--------+ : +--->| Cache C |<------->| |
>> 2676 | | : | +---------+ | |
>> 2677 | CPU 2 |<---+ | |
>> 2678 | | : | +---------+ | |
>> 2679 +--------+ : +--->| Cache D |<------->| |
>> 2680 : +---------+ | |
>> 2681 : +--------+
>> 2682 :
>> 2683
>> 2684 Imagine the system has the following properties:
>> 2685
>> 2686 (*) an odd-numbered cache line may be in cache A, cache C or it may still be
>> 2687 resident in memory;
>> 2688
>> 2689 (*) an even-numbered cache line may be in cache B, cache D or it may still be
>> 2690 resident in memory;
>> 2691
>> 2692 (*) whilst the CPU core is interrogating one cache, the other cache may be
>> 2693 making use of the bus to access the rest of the system - perhaps to
>> 2694 displace a dirty cacheline or to do a speculative load;
>> 2695
>> 2696 (*) each cache has a queue of operations that need to be applied to that cache
>> 2697 to maintain coherency with the rest of the system;
>> 2698
>> 2699 (*) the coherency queue is not flushed by normal loads to lines already
>> 2700 present in the cache, even though the contents of the queue may
>> 2701 potentially affect those loads.
>> 2702
>> 2703 Imagine, then, that two writes are made on the first CPU, with a write barrier
>> 2704 between them to guarantee that they will appear to reach that CPU's caches in
>> 2705 the requisite order:
>> 2706
>> 2707 CPU 1 CPU 2 COMMENT
>> 2708 =============== =============== =======================================
>> 2709 u == 0, v == 1 and p == &u, q == &u
>> 2710 v = 2;
>> 2711 smp_wmb(); Make sure change to v is visible before
>> 2712 change to p
>> 2713 <A:modify v=2> v is now in cache A exclusively
>> 2714 p = &v;
>> 2715 <B:modify p=&v> p is now in cache B exclusively
>> 2716
>> 2717 The write memory barrier forces the other CPUs in the system to perceive that
>> 2718 the local CPU's caches have apparently been updated in the correct order. But
>> 2719 now imagine that the second CPU wants to read those values:
>> 2720
>> 2721 CPU 1 CPU 2 COMMENT
>> 2722 =============== =============== =======================================
>> 2723 ...
>> 2724 q = p;
>> 2725 x = *q;
>> 2726
>> 2727 The above pair of reads may then fail to happen in the expected order, as the
>> 2728 cacheline holding p may get updated in one of the second CPU's caches whilst
>> 2729 the update to the cacheline holding v is delayed in the other of the second
>> 2730 CPU's caches by some other cache event:
>> 2731
>> 2732 CPU 1 CPU 2 COMMENT
>> 2733 =============== =============== =======================================
>> 2734 u == 0, v == 1 and p == &u, q == &u
>> 2735 v = 2;
>> 2736 smp_wmb();
>> 2737 <A:modify v=2> <C:busy>
>> 2738 <C:queue v=2>
>> 2739 p = &v; q = p;
>> 2740 <D:request p>
>> 2741 <B:modify p=&v> <D:commit p=&v>
>> 2742 <D:read p>
>> 2743 x = *q;
>> 2744 <C:read *q> Reads from v before v updated in cache
>> 2745 <C:unbusy>
>> 2746 <C:commit v=2>
>> 2747
>> 2748 Basically, whilst both cachelines will be updated on CPU 2 eventually, there's
>> 2749 no guarantee that, without intervention, the order of update will be the same
>> 2750 as that committed on CPU 1.
>> 2751
>> 2752
>> 2753 To intervene, we need to interpolate a data dependency barrier or a read
>> 2754 barrier between the loads. This will force the cache to commit its coherency
>> 2755 queue before processing any further requests:
>> 2756
>> 2757 CPU 1 CPU 2 COMMENT
>> 2758 =============== =============== =======================================
>> 2759 u == 0, v == 1 and p == &u, q == &u
>> 2760 v = 2;
>> 2761 smp_wmb();
>> 2762 <A:modify v=2> <C:busy>
>> 2763 <C:queue v=2>
>> 2764 p = &v; q = p;
>> 2765 <D:request p>
>> 2766 <B:modify p=&v> <D:commit p=&v>
>> 2767 <D:read p>
>> 2768 smp_read_barrier_depends()
>> 2769 <C:unbusy>
>> 2770 <C:commit v=2>
>> 2771 x = *q;
>> 2772 <C:read *q> Reads from v after v updated in cache
>> 2773
>> 2774
>> 2775 This sort of problem can be encountered on DEC Alpha processors as they have a
>> 2776 split cache that improves performance by making better use of the data bus.
>> 2777 Whilst most CPUs do imply a data dependency barrier on the read when a memory
>> 2778 access depends on a read, not all do, so it may not be relied on.
>> 2779
>> 2780 Other CPUs may also have split caches, but must coordinate between the various
>> 2781 cachelets for normal memory accesses. The semantics of the Alpha removes the
>> 2782 need for coordination in the absence of memory barriers.
>> 2783
>> 2784
2756 CACHE COHERENCY VS DMA 2785 CACHE COHERENCY VS DMA
2757 ---------------------- 2786 ----------------------
2758 2787
2759 Not all systems maintain cache coherency with 2788 Not all systems maintain cache coherency with respect to devices doing DMA. In
2760 such cases, a device attempting DMA may obtai 2789 such cases, a device attempting DMA may obtain stale data from RAM because
2761 dirty cache lines may be resident in the cach 2790 dirty cache lines may be resident in the caches of various CPUs, and may not
2762 have been written back to RAM yet. To deal w 2791 have been written back to RAM yet. To deal with this, the appropriate part of
2763 the kernel must flush the overlapping bits of 2792 the kernel must flush the overlapping bits of cache on each CPU (and maybe
2764 invalidate them as well). 2793 invalidate them as well).
2765 2794
2766 In addition, the data DMA'd to RAM by a devic 2795 In addition, the data DMA'd to RAM by a device may be overwritten by dirty
2767 cache lines being written back to RAM from a 2796 cache lines being written back to RAM from a CPU's cache after the device has
2768 installed its own data, or cache lines presen 2797 installed its own data, or cache lines present in the CPU's cache may simply
2769 obscure the fact that RAM has been updated, u 2798 obscure the fact that RAM has been updated, until at such time as the cacheline
2770 is discarded from the CPU's cache and reloade 2799 is discarded from the CPU's cache and reloaded. To deal with this, the
2771 appropriate part of the kernel must invalidat 2800 appropriate part of the kernel must invalidate the overlapping bits of the
2772 cache on each CPU. 2801 cache on each CPU.
2773 2802
2774 See Documentation/core-api/cachetlb.rst for m !! 2803 See Documentation/cachetlb.txt for more information on cache management.
2775 management. <<
2776 2804
2777 2805
2778 CACHE COHERENCY VS MMIO 2806 CACHE COHERENCY VS MMIO
2779 ----------------------- 2807 -----------------------
2780 2808
2781 Memory mapped I/O usually takes place through 2809 Memory mapped I/O usually takes place through memory locations that are part of
2782 a window in the CPU's memory space that has d 2810 a window in the CPU's memory space that has different properties assigned than
2783 the usual RAM directed window. 2811 the usual RAM directed window.
2784 2812
2785 Amongst these properties is usually the fact 2813 Amongst these properties is usually the fact that such accesses bypass the
2786 caching entirely and go directly to the devic 2814 caching entirely and go directly to the device buses. This means MMIO accesses
2787 may, in effect, overtake accesses to cached m 2815 may, in effect, overtake accesses to cached memory that were emitted earlier.
2788 A memory barrier isn't sufficient in such a c 2816 A memory barrier isn't sufficient in such a case, but rather the cache must be
2789 flushed between the cached memory write and t 2817 flushed between the cached memory write and the MMIO access if the two are in
2790 any way dependent. 2818 any way dependent.
2791 2819
2792 2820
2793 ========================= 2821 =========================
2794 THE THINGS CPUS GET UP TO 2822 THE THINGS CPUS GET UP TO
2795 ========================= 2823 =========================
2796 2824
2797 A programmer might take it for granted that t 2825 A programmer might take it for granted that the CPU will perform memory
2798 operations in exactly the order specified, so 2826 operations in exactly the order specified, so that if the CPU is, for example,
2799 given the following piece of code to execute: 2827 given the following piece of code to execute:
2800 2828
2801 a = READ_ONCE(*A); 2829 a = READ_ONCE(*A);
2802 WRITE_ONCE(*B, b); 2830 WRITE_ONCE(*B, b);
2803 c = READ_ONCE(*C); 2831 c = READ_ONCE(*C);
2804 d = READ_ONCE(*D); 2832 d = READ_ONCE(*D);
2805 WRITE_ONCE(*E, e); 2833 WRITE_ONCE(*E, e);
2806 2834
2807 they would then expect that the CPU will comp 2835 they would then expect that the CPU will complete the memory operation for each
2808 instruction before moving on to the next one, 2836 instruction before moving on to the next one, leading to a definite sequence of
2809 operations as seen by external observers in t 2837 operations as seen by external observers in the system:
2810 2838
2811 LOAD *A, STORE *B, LOAD *C, LOAD *D, 2839 LOAD *A, STORE *B, LOAD *C, LOAD *D, STORE *E.
2812 2840
2813 2841
2814 Reality is, of course, much messier. With ma 2842 Reality is, of course, much messier. With many CPUs and compilers, the above
2815 assumption doesn't hold because: 2843 assumption doesn't hold because:
2816 2844
2817 (*) loads are more likely to need to be comp 2845 (*) loads are more likely to need to be completed immediately to permit
2818 execution progress, whereas stores can o 2846 execution progress, whereas stores can often be deferred without a
2819 problem; 2847 problem;
2820 2848
2821 (*) loads may be done speculatively, and the 2849 (*) loads may be done speculatively, and the result discarded should it prove
2822 to have been unnecessary; 2850 to have been unnecessary;
2823 2851
2824 (*) loads may be done speculatively, leading 2852 (*) loads may be done speculatively, leading to the result having been fetched
2825 at the wrong time in the expected sequen 2853 at the wrong time in the expected sequence of events;
2826 2854
2827 (*) the order of the memory accesses may be 2855 (*) the order of the memory accesses may be rearranged to promote better use
2828 of the CPU buses and caches; 2856 of the CPU buses and caches;
2829 2857
2830 (*) loads and stores may be combined to impr 2858 (*) loads and stores may be combined to improve performance when talking to
2831 memory or I/O hardware that can do batch 2859 memory or I/O hardware that can do batched accesses of adjacent locations,
2832 thus cutting down on transaction setup c 2860 thus cutting down on transaction setup costs (memory and PCI devices may
2833 both be able to do this); and 2861 both be able to do this); and
2834 2862
2835 (*) the CPU's data cache may affect the orde !! 2863 (*) the CPU's data cache may affect the ordering, and whilst cache-coherency
2836 mechanisms may alleviate this - once the 2864 mechanisms may alleviate this - once the store has actually hit the cache
2837 - there's no guarantee that the coherenc 2865 - there's no guarantee that the coherency management will be propagated in
2838 order to other CPUs. 2866 order to other CPUs.
2839 2867
2840 So what another CPU, say, might actually obse 2868 So what another CPU, say, might actually observe from the above piece of code
2841 is: 2869 is:
2842 2870
2843 LOAD *A, ..., LOAD {*C,*D}, STORE *E, 2871 LOAD *A, ..., LOAD {*C,*D}, STORE *E, STORE *B
2844 2872
2845 (Where "LOAD {*C,*D}" is a combined l 2873 (Where "LOAD {*C,*D}" is a combined load)
2846 2874
2847 2875
2848 However, it is guaranteed that a CPU will be 2876 However, it is guaranteed that a CPU will be self-consistent: it will see its
2849 _own_ accesses appear to be correctly ordered 2877 _own_ accesses appear to be correctly ordered, without the need for a memory
2850 barrier. For instance with the following cod 2878 barrier. For instance with the following code:
2851 2879
2852 U = READ_ONCE(*A); 2880 U = READ_ONCE(*A);
2853 WRITE_ONCE(*A, V); 2881 WRITE_ONCE(*A, V);
2854 WRITE_ONCE(*A, W); 2882 WRITE_ONCE(*A, W);
2855 X = READ_ONCE(*A); 2883 X = READ_ONCE(*A);
2856 WRITE_ONCE(*A, Y); 2884 WRITE_ONCE(*A, Y);
2857 Z = READ_ONCE(*A); 2885 Z = READ_ONCE(*A);
2858 2886
2859 and assuming no intervention by an external i 2887 and assuming no intervention by an external influence, it can be assumed that
2860 the final result will appear to be: 2888 the final result will appear to be:
2861 2889
2862 U == the original value of *A 2890 U == the original value of *A
2863 X == W 2891 X == W
2864 Z == Y 2892 Z == Y
2865 *A == Y 2893 *A == Y
2866 2894
2867 The code above may cause the CPU to generate 2895 The code above may cause the CPU to generate the full sequence of memory
2868 accesses: 2896 accesses:
2869 2897
2870 U=LOAD *A, STORE *A=V, STORE *A=W, X= 2898 U=LOAD *A, STORE *A=V, STORE *A=W, X=LOAD *A, STORE *A=Y, Z=LOAD *A
2871 2899
2872 in that order, but, without intervention, the 2900 in that order, but, without intervention, the sequence may have almost any
2873 combination of elements combined or discarded 2901 combination of elements combined or discarded, provided the program's view
2874 of the world remains consistent. Note that R 2902 of the world remains consistent. Note that READ_ONCE() and WRITE_ONCE()
2875 are -not- optional in the above example, as t 2903 are -not- optional in the above example, as there are architectures
2876 where a given CPU might reorder successive lo 2904 where a given CPU might reorder successive loads to the same location.
2877 On such architectures, READ_ONCE() and WRITE_ 2905 On such architectures, READ_ONCE() and WRITE_ONCE() do whatever is
2878 necessary to prevent this, for example, on It 2906 necessary to prevent this, for example, on Itanium the volatile casts
2879 used by READ_ONCE() and WRITE_ONCE() cause GC 2907 used by READ_ONCE() and WRITE_ONCE() cause GCC to emit the special ld.acq
2880 and st.rel instructions (respectively) that p 2908 and st.rel instructions (respectively) that prevent such reordering.
2881 2909
2882 The compiler may also combine, discard or def 2910 The compiler may also combine, discard or defer elements of the sequence before
2883 the CPU even sees them. 2911 the CPU even sees them.
2884 2912
2885 For instance: 2913 For instance:
2886 2914
2887 *A = V; 2915 *A = V;
2888 *A = W; 2916 *A = W;
2889 2917
2890 may be reduced to: 2918 may be reduced to:
2891 2919
2892 *A = W; 2920 *A = W;
2893 2921
2894 since, without either a write barrier or an W 2922 since, without either a write barrier or an WRITE_ONCE(), it can be
2895 assumed that the effect of the storage of V t 2923 assumed that the effect of the storage of V to *A is lost. Similarly:
2896 2924
2897 *A = Y; 2925 *A = Y;
2898 Z = *A; 2926 Z = *A;
2899 2927
2900 may, without a memory barrier or an READ_ONCE 2928 may, without a memory barrier or an READ_ONCE() and WRITE_ONCE(), be
2901 reduced to: 2929 reduced to:
2902 2930
2903 *A = Y; 2931 *A = Y;
2904 Z = Y; 2932 Z = Y;
2905 2933
2906 and the LOAD operation never appear outside o 2934 and the LOAD operation never appear outside of the CPU.
2907 2935
2908 2936
2909 AND THEN THERE'S THE ALPHA 2937 AND THEN THERE'S THE ALPHA
2910 -------------------------- 2938 --------------------------
2911 2939
2912 The DEC Alpha CPU is one of the most relaxed 2940 The DEC Alpha CPU is one of the most relaxed CPUs there is. Not only that,
2913 some versions of the Alpha CPU have a split d 2941 some versions of the Alpha CPU have a split data cache, permitting them to have
2914 two semantically-related cache lines updated 2942 two semantically-related cache lines updated at separate times. This is where
2915 the address-dependency barrier really becomes !! 2943 the data dependency barrier really becomes necessary as this synchronises both
2916 both caches with the memory coherence system, !! 2944 caches with the memory coherence system, thus making it seem like pointer
2917 changes vs new data occur in the right order. 2945 changes vs new data occur in the right order.
2918 2946
2919 The Alpha defines the Linux kernel's memory m !! 2947 The Alpha defines the Linux kernel's memory barrier model.
2920 the Linux kernel's addition of smp_mb() to RE <<
2921 reduced its impact on the memory model. <<
2922 <<
2923 2948
2924 VIRTUAL MACHINE GUESTS !! 2949 See the subsection on "Cache Coherency" above.
2925 ---------------------- <<
2926 <<
2927 Guests running within virtual machines might <<
2928 the guest itself is compiled without SMP supp <<
2929 interfacing with an SMP host while running an <<
2930 barriers for this use-case would be possible <<
2931 <<
2932 To handle this case optimally, low-level virt <<
2933 These have the same effect as smp_mb() etc wh <<
2934 identical code for SMP and non-SMP systems. <<
2935 should use virt_mb() rather than smp_mb() whe <<
2936 (possibly SMP) host. <<
2937 <<
2938 These are equivalent to smp_mb() etc counterp <<
2939 in particular, they do not control MMIO effec <<
2940 MMIO effects, use mandatory barriers. <<
2941 2950
2942 2951
2943 ============ 2952 ============
2944 EXAMPLE USES 2953 EXAMPLE USES
2945 ============ 2954 ============
2946 2955
2947 CIRCULAR BUFFERS 2956 CIRCULAR BUFFERS
2948 ---------------- 2957 ----------------
2949 2958
2950 Memory barriers can be used to implement circ 2959 Memory barriers can be used to implement circular buffering without the need
2951 of a lock to serialise the producer with the 2960 of a lock to serialise the producer with the consumer. See:
2952 2961
2953 Documentation/core-api/circular-buffe !! 2962 Documentation/circular-buffers.txt
2954 2963
2955 for details. 2964 for details.
2956 2965
2957 2966
2958 ========== 2967 ==========
2959 REFERENCES 2968 REFERENCES
2960 ========== 2969 ==========
2961 2970
2962 Alpha AXP Architecture Reference Manual, Seco 2971 Alpha AXP Architecture Reference Manual, Second Edition (Sites & Witek,
2963 Digital Press) 2972 Digital Press)
2964 Chapter 5.2: Physical Address Space C 2973 Chapter 5.2: Physical Address Space Characteristics
2965 Chapter 5.4: Caches and Write Buffers 2974 Chapter 5.4: Caches and Write Buffers
2966 Chapter 5.5: Data Sharing 2975 Chapter 5.5: Data Sharing
2967 Chapter 5.6: Read/Write Ordering 2976 Chapter 5.6: Read/Write Ordering
2968 2977
2969 AMD64 Architecture Programmer's Manual Volume 2978 AMD64 Architecture Programmer's Manual Volume 2: System Programming
2970 Chapter 7.1: Memory-Access Ordering 2979 Chapter 7.1: Memory-Access Ordering
2971 Chapter 7.4: Buffering and Combining 2980 Chapter 7.4: Buffering and Combining Memory Writes
2972 2981
2973 ARM Architecture Reference Manual (ARMv8, for <<
2974 Chapter B2: The AArch64 Application L <<
2975 <<
2976 IA-32 Intel Architecture Software Developer's 2982 IA-32 Intel Architecture Software Developer's Manual, Volume 3:
2977 System Programming Guide 2983 System Programming Guide
2978 Chapter 7.1: Locked Atomic Operations 2984 Chapter 7.1: Locked Atomic Operations
2979 Chapter 7.2: Memory Ordering 2985 Chapter 7.2: Memory Ordering
2980 Chapter 7.4: Serializing Instructions 2986 Chapter 7.4: Serializing Instructions
2981 2987
2982 The SPARC Architecture Manual, Version 9 2988 The SPARC Architecture Manual, Version 9
2983 Chapter 8: Memory Models 2989 Chapter 8: Memory Models
2984 Appendix D: Formal Specification of t 2990 Appendix D: Formal Specification of the Memory Models
2985 Appendix J: Programming with the Memo 2991 Appendix J: Programming with the Memory Models
2986 <<
2987 Storage in the PowerPC (Stone and Fitzgerald) <<
2988 2992
2989 UltraSPARC Programmer Reference Manual 2993 UltraSPARC Programmer Reference Manual
2990 Chapter 5: Memory Accesses and Cachea 2994 Chapter 5: Memory Accesses and Cacheability
2991 Chapter 15: Sparc-V9 Memory Models 2995 Chapter 15: Sparc-V9 Memory Models
2992 2996
2993 UltraSPARC III Cu User's Manual 2997 UltraSPARC III Cu User's Manual
2994 Chapter 9: Memory Models 2998 Chapter 9: Memory Models
2995 2999
2996 UltraSPARC IIIi Processor User's Manual 3000 UltraSPARC IIIi Processor User's Manual
2997 Chapter 8: Memory Models 3001 Chapter 8: Memory Models
2998 3002
2999 UltraSPARC Architecture 2005 3003 UltraSPARC Architecture 2005
3000 Chapter 9: Memory 3004 Chapter 9: Memory
3001 Appendix D: Formal Specifications of 3005 Appendix D: Formal Specifications of the Memory Models
3002 3006
3003 UltraSPARC T1 Supplement to the UltraSPARC Ar 3007 UltraSPARC T1 Supplement to the UltraSPARC Architecture 2005
3004 Chapter 8: Memory Models 3008 Chapter 8: Memory Models
3005 Appendix F: Caches and Cache Coherenc 3009 Appendix F: Caches and Cache Coherency
3006 3010
3007 Solaris Internals, Core Kernel Architecture, 3011 Solaris Internals, Core Kernel Architecture, p63-68:
3008 Chapter 3.3: Hardware Considerations 3012 Chapter 3.3: Hardware Considerations for Locks and
3009 Synchronization 3013 Synchronization
3010 3014
3011 Unix Systems for Modern Architectures, Symmet 3015 Unix Systems for Modern Architectures, Symmetric Multiprocessing and Caching
3012 for Kernel Programmers: 3016 for Kernel Programmers:
3013 Chapter 13: Other Memory Models 3017 Chapter 13: Other Memory Models
3014 3018
3015 Intel Itanium Architecture Software Developer 3019 Intel Itanium Architecture Software Developer's Manual: Volume 1:
3016 Section 2.6: Speculation 3020 Section 2.6: Speculation
3017 Section 4.4: Memory Access 3021 Section 4.4: Memory Access
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