1 .. SPDX-License-Identifier: GPL-2.0
2
3 ==========================
4 MHI (Modem Host Interface)
5 ==========================
6
7 This document provides information about the M
8
9 Overview
10 ========
11
12 MHI is a protocol developed by Qualcomm Innova
13 by the host processors to control and communic
14 speed peripheral buses or shared memory. Even
15 to any peripheral buses, it is primarily used
16 provides logical channels over the physical bu
17 modem protocols, such as IP data packets, mode
18 diagnostics over at least one of those logical
19 protocol provides data acknowledgment feature
20 modems via one or more logical channels.
21
22 MHI Internals
23 =============
24
25 MMIO
26 ----
27
28 MMIO (Memory mapped IO) consists of a set of r
29 which are mapped to the host memory space by t
30 Following are the major components of MMIO reg
31
32 MHI control registers: Access to MHI configura
33
34 MHI BHI registers: BHI (Boot Host Interface) r
35 for downloading the firmware to the device bef
36
37 Channel Doorbell array: Channel Doorbell (DB)
38 notify the device when there is new work to do
39
40 Event Doorbell array: Associated with event co
41 (DB) registers are used by the host to notify
42 available.
43
44 Debug registers: A set of registers and counte
45 debugging information like performance, functi
46
47 Data structures
48 ---------------
49
50 All data structures used by MHI are in the hos
51 physical interface, the device accesses those
52 structures and data buffers in the host system
53 the device.
54
55 Channel context array: All channel configurati
56 context data array.
57
58 Transfer rings: Used by the host to schedule w
59 transfer rings are organized as a circular que
60
61 Event context array: All event configurations
62 data array.
63
64 Event rings: Used by the device to send comple
65 to the host
66
67 Command context array: All command configurati
68 context data array.
69
70 Command rings: Used by the host to send MHI co
71 rings are organized as a circular queue of Com
72
73 Channels
74 --------
75
76 MHI channels are logical, unidirectional data
77 The concept of channels in MHI is similar to e
78 to 256 channels. However, specific device impl
79 the maximum number of channels allowed.
80
81 Two unidirectional channels with their associa
82 bidirectional data pipe, which can be used by
83 transport application data packets (such as IP
84 diagnostics messages, and so on). Each channel
85 transfer ring.
86
87 Transfer rings
88 --------------
89
90 Transfers between the host and device are orga
91 Transfer Descriptors (TD). TDs are managed thr
92 defined for each channel between the device an
93 memory. TDs consist of one or more ring elemen
94
95 [Read Pointer (RP)] ----------->[Ring
96 [Write Pointer (WP)]- [Ring
97 - [Ring
98 --------->[Ring
99 [Ring
100
101 Below is the basic usage of transfer rings:
102
103 * Host allocates memory for transfer ring.
104 * Host sets the base pointer, read pointer, an
105 channel context.
106 * Ring is considered empty when RP == WP.
107 * Ring is considered full when WP + 1 == RP.
108 * RP indicates the next element to be serviced
109 * When the host has a new buffer to send, it u
110 buffer information, increments the WP to the
111 associated channel DB.
112
113 Event rings
114 -----------
115
116 Events from the device to host are organized i
117 Descriptors (ED). Event rings are used by the
118 data transfer completion status, command compl
119 to the host. Event rings are the array of EDs
120 memory. EDs consist of one or more ring elemen
121
122 [Read Pointer (RP)] ----------->[Ring
123 [Write Pointer (WP)]- [Ring
124 - [Ring
125 --------->[Ring
126 [Ring
127
128 Below is the basic usage of event rings:
129
130 * Host allocates memory for event ring.
131 * Host sets the base pointer, read pointer, an
132 channel context.
133 * Both host and device has a local copy of RP,
134 * Ring is considered empty (no events to servi
135 * Ring is considered full of events when RP ==
136 * When there is a new event the device needs t
137 pointed by RP, increments the RP to the next
138 interrupt.
139
140 Ring Element
141 ------------
142
143 A Ring Element is a data structure used to tra
144 of data between the host and the device. Trans
145 single buffer pointer, the size of the buffer,
146 information. Other ring element types may only
147 information. For single buffer operations, a r
148 single element. For large multi-buffer operati
149 elements can be chained to form a longer descr
150
151 MHI Operations
152 ==============
153
154 MHI States
155 ----------
156
157 MHI_STATE_RESET
158 ~~~~~~~~~~~~~~~
159 MHI is in reset state after power-up or hardwa
160 to access device MMIO register space.
161
162 MHI_STATE_READY
163 ~~~~~~~~~~~~~~~
164 MHI is ready for initialization. The host can
165 programming MMIO registers.
166
167 MHI_STATE_M0
168 ~~~~~~~~~~~~
169 MHI is running and operational in the device.
170 issuing channel start command.
171
172 MHI_STATE_M1
173 ~~~~~~~~~~~~
174 MHI operation is suspended by the device. This
175 device detects inactivity at the physical inte
176
177 MHI_STATE_M2
178 ~~~~~~~~~~~~
179 MHI is in low power state. MHI operation is su
180 enter lower power mode.
181
182 MHI_STATE_M3
183 ~~~~~~~~~~~~
184 MHI operation stopped by the host. This state
185 MHI operation.
186
187 MHI Initialization
188 ------------------
189
190 After system boots, the device is enumerated o
191 In the case of PCIe, the device is enumerated
192 the device's MMIO register space. To initializ
193 the host performs the following operations:
194
195 * Allocates the MHI context for event, channel
196 * Initializes the context array, and prepares
197 * Waits until the device enters READY state.
198 * Programs MHI MMIO registers and sets device
199 * Waits for the device to enter M0 state.
200
201 MHI Data Transfer
202 -----------------
203
204 MHI data transfer is initiated by the host to
205 Following are the sequence of operations perfo
206 data to device:
207
208 * Host prepares TD with buffer information.
209 * Host increments the WP of the corresponding
210 * Host rings the channel DB register.
211 * Device wakes up to process the TD.
212 * Device generates a completion event for the
213 * Device increments the RP of the correspondin
214 * Device triggers IRQ to wake up the host.
215 * Host wakes up and checks the event ring for
216 * Host updates the WP of the corresponding eve
217 data transfer has been completed successfull
218
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