1 .. SPDX-License-Identifier: GPL-2.0 1 .. SPDX-License-Identifier: GPL-2.0
2 2
3 ======================== 3 ========================
4 Spear PCIe Gadget Driver 4 Spear PCIe Gadget Driver
5 ======================== 5 ========================
6 6
7 Author 7 Author
8 ====== 8 ======
9 Pratyush Anand (pratyush.anand@gmail.com) 9 Pratyush Anand (pratyush.anand@gmail.com)
10 10
11 Location 11 Location
12 ======== 12 ========
13 driver/misc/spear13xx_pcie_gadget.c 13 driver/misc/spear13xx_pcie_gadget.c
14 14
15 Supported Chip: 15 Supported Chip:
16 =============== 16 ===============
17 SPEAr1300 17 SPEAr1300
18 SPEAr1310 18 SPEAr1310
19 19
20 Menuconfig option: 20 Menuconfig option:
21 ================== 21 ==================
22 Device Drivers 22 Device Drivers
23 Misc devices 23 Misc devices
24 PCIe gadget support for SPEAr1 24 PCIe gadget support for SPEAr13XX platform
25 25
26 purpose 26 purpose
27 ======= 27 =======
28 This driver has several nodes which can be rea 28 This driver has several nodes which can be read/written by configfs interface.
29 Its main purpose is to configure selected dual 29 Its main purpose is to configure selected dual mode PCIe controller as device
30 and then program its various registers to conf 30 and then program its various registers to configure it as a particular device
31 type. This driver can be used to show spear's 31 type. This driver can be used to show spear's PCIe device capability.
32 32
33 Description of different nodes: 33 Description of different nodes:
34 =============================== 34 ===============================
35 35
36 read behavior of nodes: 36 read behavior of nodes:
37 ----------------------- 37 -----------------------
38 38
39 =============== ============================== 39 =============== ==============================================================
40 link gives ltssm status. 40 link gives ltssm status.
41 int_type type of supported interrupt 41 int_type type of supported interrupt
42 no_of_msi zero if MSI is not enabled by 42 no_of_msi zero if MSI is not enabled by host. A positive value is the
43 number of MSI vector granted. 43 number of MSI vector granted.
44 vendor_id returns programmed vendor id ( 44 vendor_id returns programmed vendor id (hex)
45 device_id returns programmed device id(h 45 device_id returns programmed device id(hex)
46 bar0_size: returns size of bar0 in hex. 46 bar0_size: returns size of bar0 in hex.
47 bar0_address returns address of bar0 mapped 47 bar0_address returns address of bar0 mapped area in hex.
48 bar0_rw_offset returns offset of bar0 for whi 48 bar0_rw_offset returns offset of bar0 for which bar0_data will return value.
49 bar0_data returns data at bar0_rw_offset 49 bar0_data returns data at bar0_rw_offset.
50 =============== ============================== 50 =============== ==============================================================
51 51
52 write behavior of nodes: 52 write behavior of nodes:
53 ------------------------ 53 ------------------------
54 54
55 =============== ============================== 55 =============== ================================================================
56 link write UP to enable ltsmm DOWN 56 link write UP to enable ltsmm DOWN to disable
57 int_type write interrupt type to be con 57 int_type write interrupt type to be configured and (int_type could be
58 INTA, MSI or NO_INT). Select M 58 INTA, MSI or NO_INT). Select MSI only when you have programmed
59 no_of_msi node. 59 no_of_msi node.
60 no_of_msi number of MSI vector needed. 60 no_of_msi number of MSI vector needed.
61 inta write 1 to assert INTA and 0 t 61 inta write 1 to assert INTA and 0 to de-assert.
62 send_msi write MSI vector to be sent. 62 send_msi write MSI vector to be sent.
63 vendor_id write vendor id(hex) to be pro 63 vendor_id write vendor id(hex) to be programmed.
64 device_id write device id(hex) to be pro 64 device_id write device id(hex) to be programmed.
65 bar0_size write size of bar0 in hex. def 65 bar0_size write size of bar0 in hex. default bar0 size is 1000 (hex)
66 bytes. 66 bytes.
67 bar0_address write address of bar0 mapped 67 bar0_address write address of bar0 mapped area in hex. (default mapping of
68 bar0 is SYSRAM1(E0800000). Alw 68 bar0 is SYSRAM1(E0800000). Always program bar size before bar
69 address. Kernel might modify b 69 address. Kernel might modify bar size and address for alignment,
70 so read back bar size and addr 70 so read back bar size and address after writing to cross check.
71 bar0_rw_offset write offset of bar0 for which 71 bar0_rw_offset write offset of bar0 for which bar0_data will write value.
72 bar0_data write data to be written at ba 72 bar0_data write data to be written at bar0_rw_offset.
73 =============== ============================== 73 =============== ================================================================
74 74
75 Node programming example 75 Node programming example
76 ======================== 76 ========================
77 77
78 Program all PCIe registers in such a way that 78 Program all PCIe registers in such a way that when this device is connected
79 to the PCIe host, then host sees this device a 79 to the PCIe host, then host sees this device as 1MB RAM.
80 80
81 :: 81 ::
82 82
83 #mount -t configfs none /Config 83 #mount -t configfs none /Config
84 84
85 For nth PCIe Device Controller:: 85 For nth PCIe Device Controller::
86 86
87 # cd /config/pcie_gadget.n/ 87 # cd /config/pcie_gadget.n/
88 88
89 Now you have all the nodes in this directory. 89 Now you have all the nodes in this directory.
90 program vendor id as 0x104a:: 90 program vendor id as 0x104a::
91 91
92 # echo 104A >> vendor_id 92 # echo 104A >> vendor_id
93 93
94 program device id as 0xCD80:: 94 program device id as 0xCD80::
95 95
96 # echo CD80 >> device_id 96 # echo CD80 >> device_id
97 97
98 program BAR0 size as 1MB:: 98 program BAR0 size as 1MB::
99 99
100 # echo 100000 >> bar0_size 100 # echo 100000 >> bar0_size
101 101
102 check for programmed bar0 size:: 102 check for programmed bar0 size::
103 103
104 # cat bar0_size 104 # cat bar0_size
105 105
106 Program BAR0 Address as DDR (0x2100000). This 106 Program BAR0 Address as DDR (0x2100000). This is the physical address of
107 memory, which is to be made visible to PCIe ho 107 memory, which is to be made visible to PCIe host. Similarly any other peripheral
108 can also be made visible to PCIe host. E.g., i 108 can also be made visible to PCIe host. E.g., if you program base address of UART
109 as BAR0 address then when this device will be 109 as BAR0 address then when this device will be connected to a host, it will be
110 visible as UART. 110 visible as UART.
111 111
112 :: 112 ::
113 113
114 # echo 2100000 >> bar0_address 114 # echo 2100000 >> bar0_address
115 115
116 program interrupt type : INTA:: 116 program interrupt type : INTA::
117 117
118 # echo INTA >> int_type 118 # echo INTA >> int_type
119 119
120 go for link up now:: 120 go for link up now::
121 121
122 # echo UP >> link 122 # echo UP >> link
123 123
124 It will have to be insured that, once link up 124 It will have to be insured that, once link up is done on gadget, then only host
125 is initialized and start to search PCIe device 125 is initialized and start to search PCIe devices on its port.
126 126
127 :: 127 ::
128 128
129 /*wait till link is up*/ 129 /*wait till link is up*/
130 # cat link 130 # cat link
131 131
132 Wait till it returns UP. 132 Wait till it returns UP.
133 133
134 To assert INTA:: 134 To assert INTA::
135 135
136 # echo 1 >> inta 136 # echo 1 >> inta
137 137
138 To de-assert INTA:: 138 To de-assert INTA::
139 139
140 # echo 0 >> inta 140 # echo 0 >> inta
141 141
142 if MSI is to be used as interrupt, program no 142 if MSI is to be used as interrupt, program no of msi vector needed (say4)::
143 143
144 # echo 4 >> no_of_msi 144 # echo 4 >> no_of_msi
145 145
146 select MSI as interrupt type:: 146 select MSI as interrupt type::
147 147
148 # echo MSI >> int_type 148 # echo MSI >> int_type
149 149
150 go for link up now:: 150 go for link up now::
151 151
152 # echo UP >> link 152 # echo UP >> link
153 153
154 wait till link is up:: 154 wait till link is up::
155 155
156 # cat link 156 # cat link
157 157
158 An application can repetitively read this node 158 An application can repetitively read this node till link is found UP. It can
159 sleep between two read. 159 sleep between two read.
160 160
161 wait till msi is enabled:: 161 wait till msi is enabled::
162 162
163 # cat no_of_msi 163 # cat no_of_msi
164 164
165 Should return 4 (number of requested MSI vecto 165 Should return 4 (number of requested MSI vector)
166 166
167 to send msi vector 2:: 167 to send msi vector 2::
168 168
169 # echo 2 >> send_msi 169 # echo 2 >> send_msi
170 # cd - 170 # cd -
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