1 .. SPDX-License-Identifier: GPL-2.0+ 1 .. SPDX-License-Identifier: GPL-2.0+
2 2
3 ============================================== 3 =========================================================================
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interf 4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
5 ============================================== 5 =========================================================================
6 6
7 Introduction 7 Introduction
8 ------------ 8 ------------
9 9
10 The IEEE 802.3cg project defines two 10 Mbit/s 10 The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
11 single pair of conductors. The 10BASE-T1L (Cla 11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point oper 12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (C 13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-poi 14 PHY supporting full / half duplex point-to-point operation over 15 m of
15 single balanced pair of conductors, or half du 15 single balanced pair of conductors, or half duplex multidrop bus
16 operation over 25 m of single balanced pair of 16 operation over 25 m of single balanced pair of conductors.
17 17
18 Furthermore, the IEEE 802.3cg project defines 18 Furthermore, the IEEE 802.3cg project defines the new Physical Layer
19 Collision Avoidance (PLCA) Reconciliation Subl 19 Collision Avoidance (PLCA) Reconciliation Sublayer (Clause 148) meant to
20 provide improved determinism to the CSMA/CD me 20 provide improved determinism to the CSMA/CD media access method. PLCA
21 works in conjunction with the 10BASE-T1S PHY o 21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
22 22
23 The aforementioned PHYs are intended to cover 23 The aforementioned PHYs are intended to cover the low-speed / low-cost
24 applications in industrial and automotive envi 24 applications in industrial and automotive environment. The large number
25 of pins (16) required by the MII interface, wh 25 of pins (16) required by the MII interface, which is specified by the
26 IEEE 802.3 in Clause 22, is one of the major c 26 IEEE 802.3 in Clause 22, is one of the major cost factors that need to be
27 addressed to fulfil this objective. 27 addressed to fulfil this objective.
28 28
29 The MAC-PHY solution integrates an IEEE Clause 29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
30 exposing a low pin count Serial Peripheral Int 30 exposing a low pin count Serial Peripheral Interface (SPI) to the host
31 microcontroller. This also enables the additio 31 microcontroller. This also enables the addition of Ethernet functionality
32 to existing low-end microcontrollers which do 32 to existing low-end microcontrollers which do not integrate a MAC
33 controller. 33 controller.
34 34
35 Overview 35 Overview
36 -------- 36 --------
37 37
38 The MAC-PHY is specified to carry both data (E 38 The MAC-PHY is specified to carry both data (Ethernet frames) and control
39 (register access) transactions over a single f 39 (register access) transactions over a single full-duplex serial peripheral
40 interface. 40 interface.
41 41
42 Protocol Overview 42 Protocol Overview
43 ----------------- 43 -----------------
44 44
45 Two types of transactions are defined in the p 45 Two types of transactions are defined in the protocol: data transactions
46 for Ethernet frame transfers and control trans 46 for Ethernet frame transfers and control transactions for register
47 read/write transfers. A chunk is the basic ele 47 read/write transfers. A chunk is the basic element of data transactions
48 and is composed of 4 bytes of overhead plus 64 48 and is composed of 4 bytes of overhead plus 64 bytes of payload size for
49 each chunk. Ethernet frames are transferred ov 49 each chunk. Ethernet frames are transferred over one or more data chunks.
50 Control transactions consist of one or more re 50 Control transactions consist of one or more register read/write control
51 commands. 51 commands.
52 52
53 SPI transactions are initiated by the SPI host 53 SPI transactions are initiated by the SPI host with the assertion of CSn
54 low to the MAC-PHY and ends with the deasserti 54 low to the MAC-PHY and ends with the deassertion of CSn high. In between
55 each SPI transaction, the SPI host may need ti 55 each SPI transaction, the SPI host may need time for additional
56 processing and to setup the next SPI data or c 56 processing and to setup the next SPI data or control transaction.
57 57
58 SPI data transactions consist of an equal numb 58 SPI data transactions consist of an equal number of transmit (TX) and
59 receive (RX) chunks. Chunks in both transmit a 59 receive (RX) chunks. Chunks in both transmit and receive directions may
60 or may not contain valid frame data independen 60 or may not contain valid frame data independent from each other, allowing
61 for the simultaneous transmission and receptio 61 for the simultaneous transmission and reception of different length
62 frames. 62 frames.
63 63
64 Each transmit data chunk begins with a 32-bit 64 Each transmit data chunk begins with a 32-bit data header followed by a
65 data chunk payload on MOSI. The data header in 65 data chunk payload on MOSI. The data header indicates whether transmit
66 frame data is present and provides the informa 66 frame data is present and provides the information to determine which
67 bytes of the payload contain valid frame data. 67 bytes of the payload contain valid frame data.
68 68
69 In parallel, receive data chunks are received 69 In parallel, receive data chunks are received on MISO. Each receive data
70 chunk consists of a data chunk payload ending 70 chunk consists of a data chunk payload ending with a 32-bit data footer.
71 The data footer indicates if there is receive 71 The data footer indicates if there is receive frame data present within
72 the payload or not and provides the informatio 72 the payload or not and provides the information to determine which bytes
73 of the payload contain valid frame data. 73 of the payload contain valid frame data.
74 74
75 Reference 75 Reference
76 --------- 76 ---------
77 77
78 10BASE-T1x MAC-PHY Serial Interface Specificat 78 10BASE-T1x MAC-PHY Serial Interface Specification,
79 79
80 Link: https://opensig.org/download/document/OP 80 Link: https://opensig.org/download/document/OPEN_Alliance_10BASET1x_MAC-PHY_Serial_Interface_V1.1.pdf
81 81
82 Hardware Architecture 82 Hardware Architecture
83 --------------------- 83 ---------------------
84 84
85 .. code-block:: none 85 .. code-block:: none
86 86
87 +----------+ +------------------------- 87 +----------+ +-------------------------------------+
88 | | | MAC-PHY 88 | | | MAC-PHY |
89 | |<---->| +-----------+ +-------+ 89 | |<---->| +-----------+ +-------+ +-------+ |
90 | SPI Host | | | SPI Slave | | MAC | 90 | SPI Host | | | SPI Slave | | MAC | | PHY | |
91 | | | +-----------+ +-------+ 91 | | | +-----------+ +-------+ +-------+ |
92 +----------+ +------------------------- 92 +----------+ +-------------------------------------+
93 93
94 Software Architecture 94 Software Architecture
95 --------------------- 95 ---------------------
96 96
97 .. code-block:: none 97 .. code-block:: none
98 98
99 +------------------------------------------- 99 +----------------------------------------------------------+
100 | Networking Subsystem 100 | Networking Subsystem |
101 +------------------------------------------- 101 +----------------------------------------------------------+
102 / \ / 102 / \ / \
103 | | 103 | |
104 | | 104 | |
105 \ / | 105 \ / |
106 +----------------------+ +-------------- 106 +----------------------+ +-----------------------------+
107 | MAC Driver |<--->| OPEN Alliance 107 | MAC Driver |<--->| OPEN Alliance TC6 Framework |
108 +----------------------+ +-------------- 108 +----------------------+ +-----------------------------+
109 / \ / 109 / \ / \
110 | | 110 | |
111 | | 111 | |
112 | \ 112 | \ /
113 +------------------------------------------- 113 +----------------------------------------------------------+
114 | SPI Subsystem 114 | SPI Subsystem |
115 +------------------------------------------- 115 +----------------------------------------------------------+
116 / \ 116 / \
117 | 117 |
118 | 118 |
119 \ / 119 \ /
120 +------------------------------------------- 120 +----------------------------------------------------------+
121 | 10BASE-T1x MAC-PHY Device 121 | 10BASE-T1x MAC-PHY Device |
122 +------------------------------------------- 122 +----------------------------------------------------------+
123 123
124 Implementation 124 Implementation
125 -------------- 125 --------------
126 126
127 MAC Driver 127 MAC Driver
128 ~~~~~~~~~~ 128 ~~~~~~~~~~
129 129
130 - Probed by SPI subsystem. 130 - Probed by SPI subsystem.
131 131
132 - Initializes OA TC6 framework for the MAC-PHY 132 - Initializes OA TC6 framework for the MAC-PHY.
133 133
134 - Registers and configures the network device. 134 - Registers and configures the network device.
135 135
136 - Sends the tx ethernet frames from n/w subsys 136 - Sends the tx ethernet frames from n/w subsystem to OA TC6 framework.
137 137
138 OPEN Alliance TC6 Framework 138 OPEN Alliance TC6 Framework
139 ~~~~~~~~~~~~~~~~~~~~~~~~~~~ 139 ~~~~~~~~~~~~~~~~~~~~~~~~~~~
140 140
141 - Initializes PHYLIB interface. 141 - Initializes PHYLIB interface.
142 142
143 - Registers mac-phy interrupt. 143 - Registers mac-phy interrupt.
144 144
145 - Performs mac-phy register read/write operati 145 - Performs mac-phy register read/write operation using the control
146 transaction protocol specified in the OPEN A 146 transaction protocol specified in the OPEN Alliance 10BASE-T1x MAC-PHY
147 Serial Interface specification. 147 Serial Interface specification.
148 148
149 - Performs Ethernet frames transaction using t 149 - Performs Ethernet frames transaction using the data transaction protocol
150 for Ethernet frames specified in the OPEN Al 150 for Ethernet frames specified in the OPEN Alliance 10BASE-T1x MAC-PHY
151 Serial Interface specification. 151 Serial Interface specification.
152 152
153 - Forwards the received Ethernet frame from 10 153 - Forwards the received Ethernet frame from 10Base-T1x MAC-PHY to n/w
154 subsystem. 154 subsystem.
155 155
156 Data Transaction 156 Data Transaction
157 ~~~~~~~~~~~~~~~~ 157 ~~~~~~~~~~~~~~~~
158 158
159 The Ethernet frames that are typically transfe 159 The Ethernet frames that are typically transferred from the SPI host to
160 the MAC-PHY will be converted into multiple tr 160 the MAC-PHY will be converted into multiple transmit data chunks. Each
161 transmit data chunk will have a 4 bytes header 161 transmit data chunk will have a 4 bytes header which contains the
162 information needed to determine the validity a 162 information needed to determine the validity and the location of the
163 transmit frame data within the 64 bytes data c 163 transmit frame data within the 64 bytes data chunk payload.
164 164
165 .. code-block:: none 165 .. code-block:: none
166 166
167 +------------------------------------------- 167 +---------------------------------------------------+
168 | Tx Chunk 168 | Tx Chunk |
169 | +---------------------------+ +---------- 169 | +---------------------------+ +----------------+ | MOSI
170 | | 64 bytes chunk payload | | 4 bytes h 170 | | 64 bytes chunk payload | | 4 bytes header | |------------>
171 | +---------------------------+ +---------- 171 | +---------------------------+ +----------------+ |
172 +------------------------------------------- 172 +---------------------------------------------------+
173 173
174 4 bytes header contains the below fields, 174 4 bytes header contains the below fields,
175 175
176 DNC (Bit 31) - Data-Not-Control flag. This fla 176 DNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI
177 transaction. For TX data chunks 177 transaction. For TX data chunks, this bit shall be ’1’.
178 0 - Control command 178 0 - Control command
179 1 - Data chunk 179 1 - Data chunk
180 180
181 SEQ (Bit 30) - Data Chunk Sequence. This bit i 181 SEQ (Bit 30) - Data Chunk Sequence. This bit is used to indicate an
182 even/odd transmit data chunk se 182 even/odd transmit data chunk sequence to the MAC-PHY.
183 183
184 NORX (Bit 29) - No Receive flag. The SPI host 184 NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent
185 the MAC-PHY from conveying RX 185 the MAC-PHY from conveying RX data on the MISO for the
186 current chunk (DV = 0 in the f 186 current chunk (DV = 0 in the footer), indicating that the
187 host would not process it. Typ 187 host would not process it. Typically, the SPI host should
188 set NORX = 0 indicating that i 188 set NORX = 0 indicating that it will accept and process
189 any receive frame data within 189 any receive frame data within the current chunk.
190 190
191 RSVD (Bit 28..24) - Reserved: All reserved bit 191 RSVD (Bit 28..24) - Reserved: All reserved bits shall be ‘0’.
192 192
193 VS (Bit 23..22) - Vendor Specific. These bits 193 VS (Bit 23..22) - Vendor Specific. These bits are implementation specific.
194 If the MAC-PHY does not impl 194 If the MAC-PHY does not implement these bits, the host
195 shall set them to ‘0’. 195 shall set them to ‘0’.
196 196
197 DV (Bit 21) - Data Valid flag. The SPI host us 197 DV (Bit 21) - Data Valid flag. The SPI host uses this bit to indicate
198 whether the current chunk contai 198 whether the current chunk contains valid transmit frame data
199 (DV = 1) or not (DV = 0). When â 199 (DV = 1) or not (DV = 0). When ‘0’, the MAC-PHY ignores the
200 chunk payload. Note that the rec 200 chunk payload. Note that the receive path is unaffected by
201 the setting of the DV bit in the 201 the setting of the DV bit in the data header.
202 202
203 SV (Bit 20) - Start Valid flag. The SPI host s 203 SV (Bit 20) - Start Valid flag. The SPI host shall set this bit when the
204 beginning of an Ethernet frame i 204 beginning of an Ethernet frame is present in the current
205 transmit data chunk payload. Oth 205 transmit data chunk payload. Otherwise, this bit shall be
206 zero. This bit is not to be conf 206 zero. This bit is not to be confused with the Start-of-Frame
207 Delimiter (SFD) byte described i 207 Delimiter (SFD) byte described in IEEE 802.3 [2].
208 208
209 SWO (Bit 19..16) - Start Word Offset. When SV 209 SWO (Bit 19..16) - Start Word Offset. When SV = 1, this field shall
210 contain the 32-bit word off 210 contain the 32-bit word offset into the transmit data
211 chunk payload that points t 211 chunk payload that points to the start of a new
212 Ethernet frame to be transm 212 Ethernet frame to be transmitted. The host shall write
213 this field as zero when SV 213 this field as zero when SV = 0.
214 214
215 RSVD (Bit 15) - Reserved: All reserved bits sh 215 RSVD (Bit 15) - Reserved: All reserved bits shall be ‘0’.
216 216
217 EV (Bit 14) - End Valid flag. The SPI host sha 217 EV (Bit 14) - End Valid flag. The SPI host shall set this bit when the end
218 of an Ethernet frame is present 218 of an Ethernet frame is present in the current transmit data
219 chunk payload. Otherwise, this b 219 chunk payload. Otherwise, this bit shall be zero.
220 220
221 EBO (Bit 13..8) - End Byte Offset. When EV = 1 221 EBO (Bit 13..8) - End Byte Offset. When EV = 1, this field shall contain
222 the byte offset into the tra 222 the byte offset into the transmit data chunk payload
223 that points to the last byte 223 that points to the last byte of the Ethernet frame to
224 transmit. This field shall b 224 transmit. This field shall be zero when EV = 0.
225 225
226 TSC (Bit 7..6) - Timestamp Capture. Request a 226 TSC (Bit 7..6) - Timestamp Capture. Request a timestamp capture when the
227 frame is transmitted onto the 227 frame is transmitted onto the network.
228 00 - Do not capture a timesta 228 00 - Do not capture a timestamp
229 01 - Capture timestamp into t 229 01 - Capture timestamp into timestamp capture register A
230 10 - Capture timestamp into t 230 10 - Capture timestamp into timestamp capture register B
231 11 - Capture timestamp into t 231 11 - Capture timestamp into timestamp capture register C
232 232
233 RSVD (Bit 5..1) - Reserved: All reserved bits 233 RSVD (Bit 5..1) - Reserved: All reserved bits shall be ‘0’.
234 234
235 P (Bit 0) - Parity. Parity bit calculated over 235 P (Bit 0) - Parity. Parity bit calculated over the transmit data header.
236 Method used is odd parity. 236 Method used is odd parity.
237 237
238 The number of buffers available in the MAC-PHY 238 The number of buffers available in the MAC-PHY to store the incoming
239 transmit data chunk payloads is represented as 239 transmit data chunk payloads is represented as transmit credits. The
240 available transmit credits in the MAC-PHY can 240 available transmit credits in the MAC-PHY can be read either from the
241 Buffer Status Register or footer (Refer below 241 Buffer Status Register or footer (Refer below for the footer info)
242 received from the MAC-PHY. The SPI host should 242 received from the MAC-PHY. The SPI host should not write more data chunks
243 than the available transmit credits as this wi 243 than the available transmit credits as this will lead to transmit buffer
244 overflow error. 244 overflow error.
245 245
246 In case the previous data footer had no transm 246 In case the previous data footer had no transmit credits available and
247 once the transmit credits become available for 247 once the transmit credits become available for transmitting transmit data
248 chunks, the MAC-PHY interrupt is asserted to S 248 chunks, the MAC-PHY interrupt is asserted to SPI host. On reception of the
249 first data header this interrupt will be deass 249 first data header this interrupt will be deasserted and the received
250 footer for the first data chunk will have the 250 footer for the first data chunk will have the transmit credits available
251 information. 251 information.
252 252
253 The Ethernet frames that are typically transfe 253 The Ethernet frames that are typically transferred from MAC-PHY to SPI
254 host will be sent as multiple receive data chu 254 host will be sent as multiple receive data chunks. Each receive data
255 chunk will have 64 bytes of data chunk payload 255 chunk will have 64 bytes of data chunk payload followed by 4 bytes footer
256 which contains the information needed to deter 256 which contains the information needed to determine the validity and the
257 location of the receive frame data within the 257 location of the receive frame data within the 64 bytes data chunk payload.
258 258
259 .. code-block:: none 259 .. code-block:: none
260 260
261 +------------------------------------------- 261 +---------------------------------------------------+
262 | Rx Chunk 262 | Rx Chunk |
263 | +----------------+ +--------------------- 263 | +----------------+ +---------------------------+ | MISO
264 | | 4 bytes footer | | 64 bytes chunk paylo 264 | | 4 bytes footer | | 64 bytes chunk payload | |------------>
265 | +----------------+ +--------------------- 265 | +----------------+ +---------------------------+ |
266 +------------------------------------------- 266 +---------------------------------------------------+
267 267
268 4 bytes footer contains the below fields, 268 4 bytes footer contains the below fields,
269 269
270 EXST (Bit 31) - Extended Status. This bit is s 270 EXST (Bit 31) - Extended Status. This bit is set when any bit in the
271 STATUS0 or STATUS1 registers a 271 STATUS0 or STATUS1 registers are set and not masked.
272 272
273 HDRB (Bit 30) - Received Header Bad. When set, 273 HDRB (Bit 30) - Received Header Bad. When set, indicates that the MAC-PHY
274 received a control or data hea 274 received a control or data header with a parity error.
275 275
276 SYNC (Bit 29) - Configuration Synchronized fla 276 SYNC (Bit 29) - Configuration Synchronized flag. This bit reflects the
277 state of the SYNC bit in the C 277 state of the SYNC bit in the CONFIG0 configuration
278 register (see Table 12). A zer 278 register (see Table 12). A zero indicates that the MAC-PHY
279 configuration may not be as ex 279 configuration may not be as expected by the SPI host.
280 Following configuration, the S 280 Following configuration, the SPI host sets the
281 corresponding bitin the config 281 corresponding bitin the configuration register which is
282 reflected in this field. 282 reflected in this field.
283 283
284 RCA (Bit 28..24) - Receive Chunks Available. T 284 RCA (Bit 28..24) - Receive Chunks Available. The RCA field indicates to
285 the SPI host the minimum nu 285 the SPI host the minimum number of additional receive
286 data chunks of frame data t 286 data chunks of frame data that are available for
287 reading beyond the current 287 reading beyond the current receive data chunk. This
288 field is zero when there is 288 field is zero when there is no receive frame data
289 pending in the MAC-PHY’s 289 pending in the MAC-PHY’s buffer for reading.
290 290
291 VS (Bit 23..22) - Vendor Specific. These bits 291 VS (Bit 23..22) - Vendor Specific. These bits are implementation specific.
292 If not implemented, the MAC- 292 If not implemented, the MAC-PHY shall set these bits to
293 ‘0’. 293 ‘0’.
294 294
295 DV (Bit 21) - Data Valid flag. The MAC-PHY use 295 DV (Bit 21) - Data Valid flag. The MAC-PHY uses this bit to indicate
296 whether the current receive data 296 whether the current receive data chunk contains valid
297 receive frame data (DV = 1) or n 297 receive frame data (DV = 1) or not (DV = 0). When ‘0’, the
298 SPI host shall ignore the chunk 298 SPI host shall ignore the chunk payload.
299 299
300 SV (Bit 20) - Start Valid flag. The MAC-PHY se 300 SV (Bit 20) - Start Valid flag. The MAC-PHY sets this bit when the current
301 chunk payload contains the start 301 chunk payload contains the start of an Ethernet frame.
302 Otherwise, this bit is zero. The 302 Otherwise, this bit is zero. The SV bit is not to be
303 confused with the Start-of-Frame 303 confused with the Start-of-Frame Delimiter (SFD) byte
304 described in IEEE 802.3 [2]. 304 described in IEEE 802.3 [2].
305 305
306 SWO (Bit 19..16) - Start Word Offset. When SV 306 SWO (Bit 19..16) - Start Word Offset. When SV = 1, this field contains the
307 32-bit word offset into the 307 32-bit word offset into the receive data chunk payload
308 containing the first byte o 308 containing the first byte of a new received Ethernet
309 frame. When a receive times 309 frame. When a receive timestamp has been added to the
310 beginning of the received E 310 beginning of the received Ethernet frame (RTSA = 1)
311 then SWO points to the most 311 then SWO points to the most significant byte of the
312 timestamp. This field will 312 timestamp. This field will be zero when SV = 0.
313 313
314 FD (Bit 15) - Frame Drop. When set, this bit i 314 FD (Bit 15) - Frame Drop. When set, this bit indicates that the MAC has
315 detected a condition for which t 315 detected a condition for which the SPI host should drop the
316 received Ethernet frame. This bi 316 received Ethernet frame. This bit is only valid at the end
317 of a received Ethernet frame (EV 317 of a received Ethernet frame (EV = 1) and shall be zero at
318 all other times. 318 all other times.
319 319
320 EV (Bit 14) - End Valid flag. The MAC-PHY sets 320 EV (Bit 14) - End Valid flag. The MAC-PHY sets this bit when the end of a
321 received Ethernet frame is prese 321 received Ethernet frame is present in this receive data
322 chunk payload. 322 chunk payload.
323 323
324 EBO (Bit 13..8) - End Byte Offset: When EV = 1 324 EBO (Bit 13..8) - End Byte Offset: When EV = 1, this field contains the
325 byte offset into the receive 325 byte offset into the receive data chunk payload that
326 locates the last byte of the 326 locates the last byte of the received Ethernet frame.
327 This field is zero when EV = 327 This field is zero when EV = 0.
328 328
329 RTSA (Bit 7) - Receive Timestamp Added. This b 329 RTSA (Bit 7) - Receive Timestamp Added. This bit is set when a 32-bit or
330 64-bit timestamp has been added 330 64-bit timestamp has been added to the beginning of the
331 received Ethernet frame. The MA 331 received Ethernet frame. The MAC-PHY shall set this bit to
332 zero when SV = 0. 332 zero when SV = 0.
333 333
334 RTSP (Bit 6) - Receive Timestamp Parity. Parit 334 RTSP (Bit 6) - Receive Timestamp Parity. Parity bit calculated over the
335 32-bit/64-bit timestamp added t 335 32-bit/64-bit timestamp added to the beginning of the
336 received Ethernet frame. Method 336 received Ethernet frame. Method used is odd parity. The
337 MAC-PHY shall set this bit to z 337 MAC-PHY shall set this bit to zero when RTSA = 0.
338 338
339 TXC (Bit 5..1) - Transmit Credits. This field 339 TXC (Bit 5..1) - Transmit Credits. This field contains the minimum number
340 of transmit data chunks of fr 340 of transmit data chunks of frame data that the SPI host
341 can write in a single transac 341 can write in a single transaction without incurring a
342 transmit buffer overflow erro 342 transmit buffer overflow error.
343 343
344 P (Bit 0) - Parity. Parity bit calculated over 344 P (Bit 0) - Parity. Parity bit calculated over the receive data footer.
345 Method used is odd parity. 345 Method used is odd parity.
346 346
347 SPI host will initiate the data receive transa 347 SPI host will initiate the data receive transaction based on the receive
348 chunks available in the MAC-PHY which is provi 348 chunks available in the MAC-PHY which is provided in the receive chunk
349 footer (RCA - Receive Chunks Available). SPI h 349 footer (RCA - Receive Chunks Available). SPI host will create data invalid
350 transmit data chunks (empty chunks) or data va 350 transmit data chunks (empty chunks) or data valid transmit data chunks in
351 case there are valid Ethernet frames to transm 351 case there are valid Ethernet frames to transmit to the MAC-PHY. The
352 receive chunks available in MAC-PHY can be rea 352 receive chunks available in MAC-PHY can be read either from the Buffer
353 Status Register or footer. 353 Status Register or footer.
354 354
355 In case the previous data footer had no receiv 355 In case the previous data footer had no receive data chunks available and
356 once the receive data chunks become available 356 once the receive data chunks become available again for reading, the
357 MAC-PHY interrupt is asserted to SPI host. On 357 MAC-PHY interrupt is asserted to SPI host. On reception of the first data
358 header this interrupt will be deasserted and t 358 header this interrupt will be deasserted and the received footer for the
359 first data chunk will have the receive chunks 359 first data chunk will have the receive chunks available information.
360 360
361 MAC-PHY Interrupt 361 MAC-PHY Interrupt
362 ~~~~~~~~~~~~~~~~~ 362 ~~~~~~~~~~~~~~~~~
363 363
364 The MAC-PHY interrupt is asserted when the fol 364 The MAC-PHY interrupt is asserted when the following conditions are met.
365 365
366 Receive chunks available - This interrupt is a 366 Receive chunks available - This interrupt is asserted when the previous
367 data footer had no receive data chunks availab 367 data footer had no receive data chunks available and once the receive
368 data chunks become available for reading. On r 368 data chunks become available for reading. On reception of the first data
369 header this interrupt will be deasserted. 369 header this interrupt will be deasserted.
370 370
371 Transmit chunk credits available - This interr 371 Transmit chunk credits available - This interrupt is asserted when the
372 previous data footer indicated no transmit cre 372 previous data footer indicated no transmit credits available and once the
373 transmit credits become available for transmit 373 transmit credits become available for transmitting transmit data chunks.
374 On reception of the first data header this int 374 On reception of the first data header this interrupt will be deasserted.
375 375
376 Extended status event - This interrupt is asse 376 Extended status event - This interrupt is asserted when the previous data
377 footer indicated no extended status and once t 377 footer indicated no extended status and once the extended event become
378 available. In this case the host should read s 378 available. In this case the host should read status #0 register to know
379 the corresponding error/event. On reception of 379 the corresponding error/event. On reception of the first data header this
380 interrupt will be deasserted. 380 interrupt will be deasserted.
381 381
382 Control Transaction 382 Control Transaction
383 ~~~~~~~~~~~~~~~~~~~ 383 ~~~~~~~~~~~~~~~~~~~
384 384
385 4 bytes control header contains the below fiel 385 4 bytes control header contains the below fields,
386 386
387 DNC (Bit 31) - Data-Not-Control flag. This fla 387 DNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI
388 transaction. For control comman 388 transaction. For control commands, this bit shall be ‘0’.
389 0 - Control command 389 0 - Control command
390 1 - Data chunk 390 1 - Data chunk
391 391
392 HDRB (Bit 30) - Received Header Bad. When set 392 HDRB (Bit 30) - Received Header Bad. When set by the MAC-PHY, indicates
393 that a header was received wit 393 that a header was received with a parity error. The SPI
394 host should always clear this 394 host should always clear this bit. The MAC-PHY ignores the
395 HDRB value sent by the SPI hos 395 HDRB value sent by the SPI host on MOSI.
396 396
397 WNR (Bit 29) - Write-Not-Read. This bit indica 397 WNR (Bit 29) - Write-Not-Read. This bit indicates if data is to be written
398 to registers (when set) or read 398 to registers (when set) or read from registers
399 (when clear). 399 (when clear).
400 400
401 AID (Bit 28) - Address Increment Disable. When 401 AID (Bit 28) - Address Increment Disable. When clear, the address will be
402 automatically post-incremented 402 automatically post-incremented by one following each
403 register read or write. When se 403 register read or write. When set, address auto increment is
404 disabled allowing successive re 404 disabled allowing successive reads and writes to occur at
405 the same register address. 405 the same register address.
406 406
407 MMS (Bit 27..24) - Memory Map Selector. This f 407 MMS (Bit 27..24) - Memory Map Selector. This field selects the specific
408 register memory map to acce 408 register memory map to access.
409 409
410 ADDR (Bit 23..8) - Address. Address of the fir 410 ADDR (Bit 23..8) - Address. Address of the first register within the
411 selected memory map to acce 411 selected memory map to access.
412 412
413 LEN (Bit 7..1) - Length. Specifies the number 413 LEN (Bit 7..1) - Length. Specifies the number of registers to read/write.
414 This field is interpreted as 414 This field is interpreted as the number of registers
415 minus 1 allowing for up to 12 415 minus 1 allowing for up to 128 consecutive registers read
416 or written starting at the ad 416 or written starting at the address specified in ADDR. A
417 length of zero shall read or 417 length of zero shall read or write a single register.
418 418
419 P (Bit 0) - Parity. Parity bit calculated over 419 P (Bit 0) - Parity. Parity bit calculated over the control command header.
420 Method used is odd parity. 420 Method used is odd parity.
421 421
422 Control transactions consist of one or more co 422 Control transactions consist of one or more control commands. Control
423 commands are used by the SPI host to read and 423 commands are used by the SPI host to read and write registers within the
424 MAC-PHY. Each control commands are composed of 424 MAC-PHY. Each control commands are composed of a 4 bytes control command
425 header followed by register write data in case 425 header followed by register write data in case of control write command.
426 426
427 The MAC-PHY ignores the final 4 bytes of data 427 The MAC-PHY ignores the final 4 bytes of data from the SPI host at the end
428 of the control write command. The control writ 428 of the control write command. The control write command is also echoed
429 from the MAC-PHY back to the SPI host to ident 429 from the MAC-PHY back to the SPI host to identify which register write
430 failed in case of any bus errors. The echoed C 430 failed in case of any bus errors. The echoed Control write command will
431 have the first 4 bytes unused value to be igno 431 have the first 4 bytes unused value to be ignored by the SPI host
432 followed by 4 bytes echoed control header foll 432 followed by 4 bytes echoed control header followed by echoed register
433 write data. Control write commands can write e 433 write data. Control write commands can write either a single register or
434 multiple consecutive registers. When multiple 434 multiple consecutive registers. When multiple consecutive registers are
435 written, the address is automatically post-inc 435 written, the address is automatically post-incremented by the MAC-PHY.
436 Writing to any unimplemented or undefined regi 436 Writing to any unimplemented or undefined registers shall be ignored and
437 yield no effect. 437 yield no effect.
438 438
439 The MAC-PHY ignores all data from the SPI host 439 The MAC-PHY ignores all data from the SPI host following the control
440 header for the remainder of the control read c 440 header for the remainder of the control read command. The control read
441 command is also echoed from the MAC-PHY back t 441 command is also echoed from the MAC-PHY back to the SPI host to identify
442 which register read is failed in case of any b 442 which register read is failed in case of any bus errors. The echoed
443 Control read command will have the first 4 byt 443 Control read command will have the first 4 bytes of unused value to be
444 ignored by the SPI host followed by 4 bytes ec 444 ignored by the SPI host followed by 4 bytes echoed control header followed
445 by register read data. Control read commands c 445 by register read data. Control read commands can read either a single
446 register or multiple consecutive registers. Wh 446 register or multiple consecutive registers. When multiple consecutive
447 registers are read, the address is automatical 447 registers are read, the address is automatically post-incremented by the
448 MAC-PHY. Reading any unimplemented or undefine 448 MAC-PHY. Reading any unimplemented or undefined registers shall return
449 zero. 449 zero.
450 450
451 Device drivers API 451 Device drivers API
452 ================== 452 ==================
453 453
454 The include/linux/oa_tc6.h defines the followi 454 The include/linux/oa_tc6.h defines the following functions:
455 455
456 .. c:function:: struct oa_tc6 *oa_tc6_init(str 456 .. c:function:: struct oa_tc6 *oa_tc6_init(struct spi_device *spi, \
457 str 457 struct net_device *netdev)
458 458
459 Initialize OA TC6 lib. 459 Initialize OA TC6 lib.
460 460
461 .. c:function:: void oa_tc6_exit(struct oa_tc6 461 .. c:function:: void oa_tc6_exit(struct oa_tc6 *tc6)
462 462
463 Free allocated OA TC6 lib. 463 Free allocated OA TC6 lib.
464 464
465 .. c:function:: int oa_tc6_write_register(stru 465 .. c:function:: int oa_tc6_write_register(struct oa_tc6 *tc6, u32 address, \
466 u32 466 u32 value)
467 467
468 Write a single register in the MAC-PHY. 468 Write a single register in the MAC-PHY.
469 469
470 .. c:function:: int oa_tc6_write_registers(str 470 .. c:function:: int oa_tc6_write_registers(struct oa_tc6 *tc6, u32 address, \
471 u32 471 u32 value[], u8 length)
472 472
473 Writing multiple consecutive registers startin 473 Writing multiple consecutive registers starting from @address in the MAC-PHY.
474 Maximum of 128 consecutive registers can be wr 474 Maximum of 128 consecutive registers can be written starting at @address.
475 475
476 .. c:function:: int oa_tc6_read_register(struc 476 .. c:function:: int oa_tc6_read_register(struct oa_tc6 *tc6, u32 address, \
477 u32 * 477 u32 *value)
478 478
479 Read a single register in the MAC-PHY. 479 Read a single register in the MAC-PHY.
480 480
481 .. c:function:: int oa_tc6_read_registers(stru 481 .. c:function:: int oa_tc6_read_registers(struct oa_tc6 *tc6, u32 address, \
482 u32 482 u32 value[], u8 length)
483 483
484 Reading multiple consecutive registers startin 484 Reading multiple consecutive registers starting from @address in the MAC-PHY.
485 Maximum of 128 consecutive registers can be re 485 Maximum of 128 consecutive registers can be read starting at @address.
486 486
487 .. c:function:: netdev_tx_t oa_tc6_start_xmit( 487 .. c:function:: netdev_tx_t oa_tc6_start_xmit(struct oa_tc6 *tc6, \
488 488 struct sk_buff *skb);
489 489
490 The transmit Ethernet frame in the skb is or g 490 The transmit Ethernet frame in the skb is or going to be transmitted through
491 the MAC-PHY. 491 the MAC-PHY.
492 492
493 .. c:function:: int oa_tc6_zero_align_receive_ 493 .. c:function:: int oa_tc6_zero_align_receive_frame_enable(struct oa_tc6 *tc6);
494 494
495 Zero align receive frame feature can be enable 495 Zero align receive frame feature can be enabled to align all receive ethernet
496 frames data to start at the beginning of any r 496 frames data to start at the beginning of any receive data chunk payload with a
497 start word offset (SWO) of zero. 497 start word offset (SWO) of zero.
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