1 .. SPDX-License-Identifier: (GPL-2.0-only OR B 1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 .. include:: <isonum.txt> 2 .. include:: <isonum.txt>
3 3
4 ============================================== 4 ================================================
5 HDAudio multi-link extensions on Intel platfor 5 HDAudio multi-link extensions on Intel platforms
6 ============================================== 6 ================================================
7 7
8 :Copyright: |copy| 2023 Intel Corporation 8 :Copyright: |copy| 2023 Intel Corporation
9 9
10 This file documents the 'multi-link structure' 10 This file documents the 'multi-link structure' introduced in 2015 with
11 the Skylake processor and recently extended in 11 the Skylake processor and recently extended in newer Intel platforms
12 12
13 HDaudio existing link mapping (2015 addition i 13 HDaudio existing link mapping (2015 addition in SkyLake)
14 ============================================== 14 ========================================================
15 15
16 External HDAudio codecs are handled with link 16 External HDAudio codecs are handled with link #0, while iDISP codec
17 for HDMI/DisplayPort is handled with link #1. 17 for HDMI/DisplayPort is handled with link #1.
18 18
19 The only change to the 2015 definitions is the 19 The only change to the 2015 definitions is the declaration of the
20 LCAP.ALT=0x0 - since the ALT bit was previousl 20 LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a
21 backwards-compatible change. 21 backwards-compatible change.
22 22
23 LCTL.SPA and LCTL.CPA are automatically set wh 23 LCTL.SPA and LCTL.CPA are automatically set when exiting reset. They
24 are only used in existing drivers when the SCF 24 are only used in existing drivers when the SCF value needs to be
25 corrected. 25 corrected.
26 26
27 Basic structure for HDaudio codecs 27 Basic structure for HDaudio codecs
28 ---------------------------------- 28 ----------------------------------
29 29
30 :: 30 ::
31 31
32 +-----------+ 32 +-----------+
33 | ML cap #0 | 33 | ML cap #0 |
34 +-----------+ 34 +-----------+
35 | ML cap #1 |---+ 35 | ML cap #1 |---+
36 +-----------+ | 36 +-----------+ |
37 | 37 |
38 +--> 0x0 +---------------+ L 38 +--> 0x0 +---------------+ LCAP
39 | ALT=0 | 39 | ALT=0 |
40 +---------------+ 40 +---------------+
41 | S192 | 41 | S192 |
42 +---------------+ 42 +---------------+
43 | S96 | 43 | S96 |
44 +---------------+ 44 +---------------+
45 | S48 | 45 | S48 |
46 +---------------+ 46 +---------------+
47 | S24 | 47 | S24 |
48 +---------------+ 48 +---------------+
49 | S12 | 49 | S12 |
50 +---------------+ 50 +---------------+
51 | S6 | 51 | S6 |
52 +---------------+ 52 +---------------+
53 53
54 0x4 +---------------+ L 54 0x4 +---------------+ LCTL
55 | INTSTS | 55 | INTSTS |
56 +---------------+ 56 +---------------+
57 | CPA | 57 | CPA |
58 +---------------+ 58 +---------------+
59 | SPA | 59 | SPA |
60 +---------------+ 60 +---------------+
61 | SCF | 61 | SCF |
62 +---------------+ 62 +---------------+
63 63
64 0x8 +---------------+ L 64 0x8 +---------------+ LOSIDV
65 | L1OSIVD15 | 65 | L1OSIVD15 |
66 +---------------+ 66 +---------------+
67 | L1OSIDV.. | 67 | L1OSIDV.. |
68 +---------------+ 68 +---------------+
69 | L1OSIDV1 | 69 | L1OSIDV1 |
70 +---------------+ 70 +---------------+
71 71
72 0xC +---------------+ L 72 0xC +---------------+ LSDIID
73 | SDIID14 | 73 | SDIID14 |
74 +---------------+ 74 +---------------+
75 | SDIID... | 75 | SDIID... |
76 +---------------+ 76 +---------------+
77 | SDIID0 | 77 | SDIID0 |
78 +---------------+ 78 +---------------+
79 79
80 SoundWire HDaudio extended link mapping 80 SoundWire HDaudio extended link mapping
81 ======================================= 81 =======================================
82 82
83 A SoundWire extended link is identified when L 83 A SoundWire extended link is identified when LCAP.ALT=1 and
84 LEPTR.ID=0. 84 LEPTR.ID=0.
85 85
86 DMA control uses the existing LOSIDV register. 86 DMA control uses the existing LOSIDV register.
87 87
88 Changes include additional descriptions for en 88 Changes include additional descriptions for enumeration that were not
89 present in earlier generations. 89 present in earlier generations.
90 90
91 - multi-link synchronization: capabilities in 91 - multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
92 - number of sublinks (manager IP) in LCAP.LSCO 92 - number of sublinks (manager IP) in LCAP.LSCOUNT
93 - power management moved from SHIM to LCTL.SPA 93 - power management moved from SHIM to LCTL.SPA bits
94 - hand-over to the DSP for access to multi-lin 94 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
95 - mapping of SoundWire codecs to SDI ID bits 95 - mapping of SoundWire codecs to SDI ID bits
96 - move of SHIM and Cadence registers to differ 96 - move of SHIM and Cadence registers to different offsets, with no
97 change in functionality. The LEPTR.PTR value 97 change in functionality. The LEPTR.PTR value is an offset from the
98 ML address, with a default value of 0x30000. 98 ML address, with a default value of 0x30000.
99 99
100 Extended structure for SoundWire (assuming 4 M 100 Extended structure for SoundWire (assuming 4 Manager IP)
101 ---------------------------------------------- 101 --------------------------------------------------------
102 102
103 :: 103 ::
104 104
105 +-----------+ 105 +-----------+
106 | ML cap #0 | 106 | ML cap #0 |
107 +-----------+ 107 +-----------+
108 | ML cap #1 | 108 | ML cap #1 |
109 +-----------+ 109 +-----------+
110 | ML cap #2 |---+ 110 | ML cap #2 |---+
111 +-----------+ | 111 +-----------+ |
112 | 112 |
113 +--> 0x0 +---------------+ L 113 +--> 0x0 +---------------+ LCAP
114 | ALT=1 | 114 | ALT=1 |
115 +---------------+ 115 +---------------+
116 | INTC | 116 | INTC |
117 +---------------+ 117 +---------------+
118 | OFLS | 118 | OFLS |
119 +---------------+ 119 +---------------+
120 | LSS | 120 | LSS |
121 +---------------+ 121 +---------------+
122 | SLCOUNT=4 |-- 122 | SLCOUNT=4 |-----------+
123 +---------------+ 123 +---------------+ |
124 124 |
125 0x4 +---------------+ L 125 0x4 +---------------+ LCTL |
126 | INTSTS | 126 | INTSTS | |
127 +---------------+ 127 +---------------+ |
128 | CPA (x bits) | 128 | CPA (x bits) | |
129 +---------------+ 129 +---------------+ |
130 | SPA (x bits) | 130 | SPA (x bits) | |
131 +---------------+ 131 +---------------+ for each sublink x
132 | INTEN | 132 | INTEN | |
133 +---------------+ 133 +---------------+ |
134 | OFLEN | 134 | OFLEN | |
135 +---------------+ 135 +---------------+ |
136 136 |
137 0x8 +---------------+ L 137 0x8 +---------------+ LOSIDV |
138 | L1OSIVD15 | 138 | L1OSIVD15 | |
139 +---------------+ 139 +---------------+ |
140 | L1OSIDV.. | 140 | L1OSIDV.. | |
141 +---------------+ 141 +---------------+ |
142 | L1OSIDV1 | 142 | L1OSIDV1 | +---+----------------------------------------------------------+
143 +---------------+ 143 +---------------+ | |
144 144 v |
145 0xC + 0x2 * x +---------------+ L 145 0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 |
146 | SDIID14 | 146 | SDIID14 | | | SoundWire SHIM | |
147 +---------------+ 147 +---------------+ | | generic | |
148 | SDIID... | 148 | SDIID... | | +-----------------+ 0x00030100 |
149 +---------------+ 149 +---------------+ | | SoundWire IP | |
150 | SDIID0 | 150 | SDIID0 | | +-----------------+ 0x00036000 |
151 +---------------+ 151 +---------------+ | | SoundWire SHIM | |
152 152 | | vendor-specific | |
153 0x1C +---------------+ L 153 0x1C +---------------+ LSYNC | +-----------------+ |
154 | CMDSYNC | 154 | CMDSYNC | | v
155 +---------------+ 155 +---------------+ | +-----------------+ 0x00030000 + 0x8000 * x
156 | SYNCGO | 156 | SYNCGO | | | SoundWire SHIM |
157 +---------------+ 157 +---------------+ | | generic |
158 | SYNCPU | 158 | SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x
159 +---------------+ 159 +---------------+ | | SoundWire IP |
160 | SYNPRD | 160 | SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x
161 +---------------+ 161 +---------------+ | | SoundWire SHIM |
162 162 | | vendor-specific |
163 0x20 +---------------+ L 163 0x20 +---------------+ LEPTR | +-----------------+
164 | ID = 0 | 164 | ID = 0 | |
165 +---------------+ 165 +---------------+ |
166 | VER | 166 | VER | |
167 +---------------+ 167 +---------------+ |
168 | PTR |-- 168 | PTR |------------+
169 +---------------+ 169 +---------------+
170 170
171 171
172 DMIC HDaudio extended link mapping 172 DMIC HDaudio extended link mapping
173 ================================== 173 ==================================
174 174
175 A DMIC extended link is identified when LCAP.A 175 A DMIC extended link is identified when LCAP.ALT=1 and
176 LEPTR.ID=0xC1 are set. 176 LEPTR.ID=0xC1 are set.
177 177
178 DMA control uses the existing LOSIDV register 178 DMA control uses the existing LOSIDV register
179 179
180 Changes include additional descriptions for en 180 Changes include additional descriptions for enumeration that were not
181 present in earlier generations. 181 present in earlier generations.
182 182
183 - multi-link synchronization: capabilities in 183 - multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
184 - power management with LCTL.SPA bits 184 - power management with LCTL.SPA bits
185 - hand-over to the DSP for access to multi-lin 185 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
186 186
187 - move of DMIC registers to different offsets, 187 - move of DMIC registers to different offsets, with no change in
188 functionality. The LEPTR.PTR value is an off 188 functionality. The LEPTR.PTR value is an offset from the ML
189 address, with a default value of 0x10000. 189 address, with a default value of 0x10000.
190 190
191 Extended structure for DMIC 191 Extended structure for DMIC
192 --------------------------- 192 ---------------------------
193 193
194 :: 194 ::
195 195
196 +-----------+ 196 +-----------+
197 | ML cap #0 | 197 | ML cap #0 |
198 +-----------+ 198 +-----------+
199 | ML cap #1 | 199 | ML cap #1 |
200 +-----------+ 200 +-----------+
201 | ML cap #2 |---+ 201 | ML cap #2 |---+
202 +-----------+ | 202 +-----------+ |
203 | 203 |
204 +--> 0x0 +---------------+ L 204 +--> 0x0 +---------------+ LCAP
205 | ALT=1 | 205 | ALT=1 |
206 +---------------+ 206 +---------------+
207 | INTC | 207 | INTC |
208 +---------------+ 208 +---------------+
209 | OFLS | 209 | OFLS |
210 +---------------+ 210 +---------------+
211 | SLCOUNT=1 | 211 | SLCOUNT=1 |
212 +---------------+ 212 +---------------+
213 213
214 0x4 +---------------+ L 214 0x4 +---------------+ LCTL
215 | INTSTS | 215 | INTSTS |
216 +---------------+ 216 +---------------+
217 | CPA | 217 | CPA |
218 +---------------+ 218 +---------------+
219 | SPA | 219 | SPA |
220 +---------------+ 220 +---------------+
221 | INTEN | 221 | INTEN |
222 +---------------+ 222 +---------------+
223 | OFLEN | 223 | OFLEN |
224 +---------------+ 224 +---------------+ +---> 0x10000 +-----------------+ 0x00010000
225 225 | | DMIC SHIM |
226 0x8 +---------------+ L 226 0x8 +---------------+ LOSIDV | | generic |
227 | L1OSIVD15 | 227 | L1OSIVD15 | | +-----------------+ 0x00010100
228 +---------------+ 228 +---------------+ | | DMIC IP |
229 | L1OSIDV.. | 229 | L1OSIDV.. | | +-----------------+ 0x00016000
230 +---------------+ 230 +---------------+ | | DMIC SHIM |
231 | L1OSIDV1 | 231 | L1OSIDV1 | | | vendor-specific |
232 +---------------+ 232 +---------------+ | +-----------------+
233 233 |
234 0x20 +---------------+ L 234 0x20 +---------------+ LEPTR |
235 | ID = 0xC1 | 235 | ID = 0xC1 | |
236 +---------------+ 236 +---------------+ |
237 | VER | 237 | VER | |
238 +---------------+ 238 +---------------+ |
239 | PTR |-- 239 | PTR |-----------+
240 +---------------+ 240 +---------------+
241 241
242 242
243 SSP HDaudio extended link mapping 243 SSP HDaudio extended link mapping
244 ================================= 244 =================================
245 245
246 A DMIC extended link is identified when LCAP.A 246 A DMIC extended link is identified when LCAP.ALT=1 and
247 LEPTR.ID=0xC0 are set. 247 LEPTR.ID=0xC0 are set.
248 248
249 DMA control uses the existing LOSIDV register 249 DMA control uses the existing LOSIDV register
250 250
251 Changes include additional descriptions for en 251 Changes include additional descriptions for enumeration and control that were not
252 present in earlier generations: 252 present in earlier generations:
253 - number of sublinks (SSP IP instances) in LCA 253 - number of sublinks (SSP IP instances) in LCAP.LSCOUNT
254 - power management moved from SHIM to LCTL.SPA 254 - power management moved from SHIM to LCTL.SPA bits
255 - hand-over to the DSP for access to multi-lin 255 - hand-over to the DSP for access to multi-link registers, SHIM/IP
256 with LCTL.OFLEN 256 with LCTL.OFLEN
257 - move of SHIM and SSP IP registers to differe 257 - move of SHIM and SSP IP registers to different offsets, with no
258 change in functionality. The LEPTR.PTR value 258 change in functionality. The LEPTR.PTR value is an offset from the ML
259 address, with a default value of 0x28000. 259 address, with a default value of 0x28000.
260 260
261 Extended structure for SSP (assuming 3 instanc 261 Extended structure for SSP (assuming 3 instances of the IP)
262 ---------------------------------------------- 262 -----------------------------------------------------------
263 263
264 :: 264 ::
265 265
266 +-----------+ 266 +-----------+
267 | ML cap #0 | 267 | ML cap #0 |
268 +-----------+ 268 +-----------+
269 | ML cap #1 | 269 | ML cap #1 |
270 +-----------+ 270 +-----------+
271 | ML cap #2 |---+ 271 | ML cap #2 |---+
272 +-----------+ | 272 +-----------+ |
273 | 273 |
274 +--> 0x0 +---------------+ L 274 +--> 0x0 +---------------+ LCAP
275 | ALT=1 | 275 | ALT=1 |
276 +---------------+ 276 +---------------+
277 | INTC | 277 | INTC |
278 +---------------+ 278 +---------------+
279 | OFLS | 279 | OFLS |
280 +---------------+ 280 +---------------+
281 | SLCOUNT=3 |-- 281 | SLCOUNT=3 |-------------------------for each sublink x -------------------------+
282 +---------------+ 282 +---------------+ |
283 283 |
284 0x4 +---------------+ L 284 0x4 +---------------+ LCTL |
285 | INTSTS | 285 | INTSTS | |
286 +---------------+ 286 +---------------+ |
287 | CPA (x bits) | 287 | CPA (x bits) | |
288 +---------------+ 288 +---------------+ |
289 | SPA (x bits) | 289 | SPA (x bits) | |
290 +---------------+ 290 +---------------+ |
291 | INTEN | 291 | INTEN | |
292 +---------------+ 292 +---------------+ |
293 | OFLEN | 293 | OFLEN | |
294 +---------------+ 294 +---------------+ +---> 0x28000 +-----------------+ 0x00028000 |
295 295 | | SSP SHIM | |
296 0x8 +---------------+ L 296 0x8 +---------------+ LOSIDV | | generic | |
297 | L1OSIVD15 | 297 | L1OSIVD15 | | +-----------------+ 0x00028100 |
298 +---------------+ 298 +---------------+ | | SSP IP | |
299 | L1OSIDV.. | 299 | L1OSIDV.. | | +-----------------+ 0x00028C00 |
300 +---------------+ 300 +---------------+ | | SSP SHIM | |
301 | L1OSIDV1 | 301 | L1OSIDV1 | | | vendor-specific | |
302 +---------------+ 302 +---------------+ | +-----------------+ |
303 303 | v
304 0x20 +---------------+ L 304 0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x
305 | ID = 0xC0 | 305 | ID = 0xC0 | | | SSP SHIM |
306 +---------------+ 306 +---------------+ | | generic |
307 | VER | 307 | VER | | +-----------------+ 0x00028100 + 0x1000 * x
308 +---------------+ 308 +---------------+ | | SSP IP |
309 | PTR |-- 309 | PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x
310 +---------------+ 310 +---------------+ | SSP SHIM |
311 311 | vendor-specific |
312 312 +-----------------+
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.