1 .. SPDX-License-Identifier: (GPL-2.0-only OR B
2 .. include:: <isonum.txt>
3
4 ==============================================
5 HDAudio multi-link extensions on Intel platfor
6 ==============================================
7
8 :Copyright: |copy| 2023 Intel Corporation
9
10 This file documents the 'multi-link structure'
11 the Skylake processor and recently extended in
12
13 HDaudio existing link mapping (2015 addition i
14 ==============================================
15
16 External HDAudio codecs are handled with link
17 for HDMI/DisplayPort is handled with link #1.
18
19 The only change to the 2015 definitions is the
20 LCAP.ALT=0x0 - since the ALT bit was previousl
21 backwards-compatible change.
22
23 LCTL.SPA and LCTL.CPA are automatically set wh
24 are only used in existing drivers when the SCF
25 corrected.
26
27 Basic structure for HDaudio codecs
28 ----------------------------------
29
30 ::
31
32 +-----------+
33 | ML cap #0 |
34 +-----------+
35 | ML cap #1 |---+
36 +-----------+ |
37 |
38 +--> 0x0 +---------------+ L
39 | ALT=0 |
40 +---------------+
41 | S192 |
42 +---------------+
43 | S96 |
44 +---------------+
45 | S48 |
46 +---------------+
47 | S24 |
48 +---------------+
49 | S12 |
50 +---------------+
51 | S6 |
52 +---------------+
53
54 0x4 +---------------+ L
55 | INTSTS |
56 +---------------+
57 | CPA |
58 +---------------+
59 | SPA |
60 +---------------+
61 | SCF |
62 +---------------+
63
64 0x8 +---------------+ L
65 | L1OSIVD15 |
66 +---------------+
67 | L1OSIDV.. |
68 +---------------+
69 | L1OSIDV1 |
70 +---------------+
71
72 0xC +---------------+ L
73 | SDIID14 |
74 +---------------+
75 | SDIID... |
76 +---------------+
77 | SDIID0 |
78 +---------------+
79
80 SoundWire HDaudio extended link mapping
81 =======================================
82
83 A SoundWire extended link is identified when L
84 LEPTR.ID=0.
85
86 DMA control uses the existing LOSIDV register.
87
88 Changes include additional descriptions for en
89 present in earlier generations.
90
91 - multi-link synchronization: capabilities in
92 - number of sublinks (manager IP) in LCAP.LSCO
93 - power management moved from SHIM to LCTL.SPA
94 - hand-over to the DSP for access to multi-lin
95 - mapping of SoundWire codecs to SDI ID bits
96 - move of SHIM and Cadence registers to differ
97 change in functionality. The LEPTR.PTR value
98 ML address, with a default value of 0x30000.
99
100 Extended structure for SoundWire (assuming 4 M
101 ----------------------------------------------
102
103 ::
104
105 +-----------+
106 | ML cap #0 |
107 +-----------+
108 | ML cap #1 |
109 +-----------+
110 | ML cap #2 |---+
111 +-----------+ |
112 |
113 +--> 0x0 +---------------+ L
114 | ALT=1 |
115 +---------------+
116 | INTC |
117 +---------------+
118 | OFLS |
119 +---------------+
120 | LSS |
121 +---------------+
122 | SLCOUNT=4 |--
123 +---------------+
124
125 0x4 +---------------+ L
126 | INTSTS |
127 +---------------+
128 | CPA (x bits) |
129 +---------------+
130 | SPA (x bits) |
131 +---------------+
132 | INTEN |
133 +---------------+
134 | OFLEN |
135 +---------------+
136
137 0x8 +---------------+ L
138 | L1OSIVD15 |
139 +---------------+
140 | L1OSIDV.. |
141 +---------------+
142 | L1OSIDV1 |
143 +---------------+
144
145 0xC + 0x2 * x +---------------+ L
146 | SDIID14 |
147 +---------------+
148 | SDIID... |
149 +---------------+
150 | SDIID0 |
151 +---------------+
152
153 0x1C +---------------+ L
154 | CMDSYNC |
155 +---------------+
156 | SYNCGO |
157 +---------------+
158 | SYNCPU |
159 +---------------+
160 | SYNPRD |
161 +---------------+
162
163 0x20 +---------------+ L
164 | ID = 0 |
165 +---------------+
166 | VER |
167 +---------------+
168 | PTR |--
169 +---------------+
170
171
172 DMIC HDaudio extended link mapping
173 ==================================
174
175 A DMIC extended link is identified when LCAP.A
176 LEPTR.ID=0xC1 are set.
177
178 DMA control uses the existing LOSIDV register
179
180 Changes include additional descriptions for en
181 present in earlier generations.
182
183 - multi-link synchronization: capabilities in
184 - power management with LCTL.SPA bits
185 - hand-over to the DSP for access to multi-lin
186
187 - move of DMIC registers to different offsets,
188 functionality. The LEPTR.PTR value is an off
189 address, with a default value of 0x10000.
190
191 Extended structure for DMIC
192 ---------------------------
193
194 ::
195
196 +-----------+
197 | ML cap #0 |
198 +-----------+
199 | ML cap #1 |
200 +-----------+
201 | ML cap #2 |---+
202 +-----------+ |
203 |
204 +--> 0x0 +---------------+ L
205 | ALT=1 |
206 +---------------+
207 | INTC |
208 +---------------+
209 | OFLS |
210 +---------------+
211 | SLCOUNT=1 |
212 +---------------+
213
214 0x4 +---------------+ L
215 | INTSTS |
216 +---------------+
217 | CPA |
218 +---------------+
219 | SPA |
220 +---------------+
221 | INTEN |
222 +---------------+
223 | OFLEN |
224 +---------------+
225
226 0x8 +---------------+ L
227 | L1OSIVD15 |
228 +---------------+
229 | L1OSIDV.. |
230 +---------------+
231 | L1OSIDV1 |
232 +---------------+
233
234 0x20 +---------------+ L
235 | ID = 0xC1 |
236 +---------------+
237 | VER |
238 +---------------+
239 | PTR |--
240 +---------------+
241
242
243 SSP HDaudio extended link mapping
244 =================================
245
246 A DMIC extended link is identified when LCAP.A
247 LEPTR.ID=0xC0 are set.
248
249 DMA control uses the existing LOSIDV register
250
251 Changes include additional descriptions for en
252 present in earlier generations:
253 - number of sublinks (SSP IP instances) in LCA
254 - power management moved from SHIM to LCTL.SPA
255 - hand-over to the DSP for access to multi-lin
256 with LCTL.OFLEN
257 - move of SHIM and SSP IP registers to differe
258 change in functionality. The LEPTR.PTR value
259 address, with a default value of 0x28000.
260
261 Extended structure for SSP (assuming 3 instanc
262 ----------------------------------------------
263
264 ::
265
266 +-----------+
267 | ML cap #0 |
268 +-----------+
269 | ML cap #1 |
270 +-----------+
271 | ML cap #2 |---+
272 +-----------+ |
273 |
274 +--> 0x0 +---------------+ L
275 | ALT=1 |
276 +---------------+
277 | INTC |
278 +---------------+
279 | OFLS |
280 +---------------+
281 | SLCOUNT=3 |--
282 +---------------+
283
284 0x4 +---------------+ L
285 | INTSTS |
286 +---------------+
287 | CPA (x bits) |
288 +---------------+
289 | SPA (x bits) |
290 +---------------+
291 | INTEN |
292 +---------------+
293 | OFLEN |
294 +---------------+
295
296 0x8 +---------------+ L
297 | L1OSIVD15 |
298 +---------------+
299 | L1OSIDV.. |
300 +---------------+
301 | L1OSIDV1 |
302 +---------------+
303
304 0x20 +---------------+ L
305 | ID = 0xC0 |
306 +---------------+
307 | VER |
308 +---------------+
309 | PTR |--
310 +---------------+
311
312
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