1 ============================================== 1 ==============================================
2 spi_lm70llp : LM70-LLP parport-to-SPI adapter 2 spi_lm70llp : LM70-LLP parport-to-SPI adapter
3 ============================================== 3 ==============================================
4 4
5 Supported board/chip: 5 Supported board/chip:
6 6
7 * National Semiconductor LM70 LLP evaluation 7 * National Semiconductor LM70 LLP evaluation board
8 8
9 Datasheet: https://www.ti.com/lit/gpn/lm70 !! 9 Datasheet: http://www.national.com/pf/LM/LM70.html
10 10
11 Author: 11 Author:
12 Kaiwan N Billimoria <kaiwan@designergra 12 Kaiwan N Billimoria <kaiwan@designergraphix.com>
13 13
14 Description 14 Description
15 ----------- 15 -----------
16 This driver provides glue code connecting a Na 16 This driver provides glue code connecting a National Semiconductor LM70 LLP
17 temperature sensor evaluation board to the ker 17 temperature sensor evaluation board to the kernel's SPI core subsystem.
18 18
19 This is a SPI master controller driver. It can 19 This is a SPI master controller driver. It can be used in conjunction with
20 (layered under) the LM70 logical driver (a "SP 20 (layered under) the LM70 logical driver (a "SPI protocol driver").
21 In effect, this driver turns the parallel port 21 In effect, this driver turns the parallel port interface on the eval board
22 into a SPI bus with a single device, which wil 22 into a SPI bus with a single device, which will be driven by the generic
23 LM70 driver (drivers/hwmon/lm70.c). 23 LM70 driver (drivers/hwmon/lm70.c).
24 24
25 25
26 Hardware Interfacing 26 Hardware Interfacing
27 -------------------- 27 --------------------
28 The schematic for this particular board (the L 28 The schematic for this particular board (the LM70EVAL-LLP) is
29 available (on page 4) here: 29 available (on page 4) here:
30 30
31 https://download.datasheets.com/pdfs/documen !! 31 http://www.national.com/appinfo/tempsensors/files/LM70LLPEVALmanual.pdf
32 32
33 The hardware interfacing on the LM70 LLP eval 33 The hardware interfacing on the LM70 LLP eval board is as follows:
34 34
35 ======== == ========= ========== 35 ======== == ========= ==========
36 Parallel LM70 LLP 36 Parallel LM70 LLP
37 Port . Direction JP2 Header 37 Port . Direction JP2 Header
38 ======== == ========= ========== 38 ======== == ========= ==========
39 D0 2 - - 39 D0 2 - -
40 D1 3 --> V+ 5 40 D1 3 --> V+ 5
41 D2 4 --> V+ 5 41 D2 4 --> V+ 5
42 D3 5 --> V+ 5 42 D3 5 --> V+ 5
43 D4 6 --> V+ 5 43 D4 6 --> V+ 5
44 D5 7 --> nCS 8 44 D5 7 --> nCS 8
45 D6 8 --> SCLK 3 45 D6 8 --> SCLK 3
46 D7 9 --> SI/O 5 46 D7 9 --> SI/O 5
47 GND 25 - GND 7 47 GND 25 - GND 7
48 Select 13 <-- SI/O 1 48 Select 13 <-- SI/O 1
49 ======== == ========= ========== 49 ======== == ========= ==========
50 50
51 Note that since the LM70 uses a "3-wire" varia 51 Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
52 is connected to both pin D7 (as Master Out) an 52 is connected to both pin D7 (as Master Out) and Select (as Master In)
53 using an arrangement that lets either the parp 53 using an arrangement that lets either the parport or the LM70 pull the
54 pin low. This can't be shared with true SPI d 54 pin low. This can't be shared with true SPI devices, but other 3-wire
55 devices might share the same SI/SO pin. 55 devices might share the same SI/SO pin.
56 56
57 The bitbanger routine in this driver (lm70_txr 57 The bitbanger routine in this driver (lm70_txrx) is called back from
58 the bound "hwmon/lm70" protocol driver through 58 the bound "hwmon/lm70" protocol driver through its sysfs hook, using a
59 spi_write_then_read() call. It performs Mode 59 spi_write_then_read() call. It performs Mode 0 (SPI/Microwire) bitbanging.
60 The lm70 driver then interprets the resulting 60 The lm70 driver then interprets the resulting digital temperature value
61 and exports it through sysfs. 61 and exports it through sysfs.
62 62
63 A "gotcha": National Semiconductor's LM70 LLP 63 A "gotcha": National Semiconductor's LM70 LLP eval board circuit schematic
64 shows that the SI/O line from the LM70 chip is 64 shows that the SI/O line from the LM70 chip is connected to the base of a
65 transistor Q1 (and also a pullup, and a zener 65 transistor Q1 (and also a pullup, and a zener diode to D7); while the
66 collector is tied to VCC. 66 collector is tied to VCC.
67 67
68 Interpreting this circuit, when the LM70 SI/O 68 Interpreting this circuit, when the LM70 SI/O line is High (or tristate
69 and not grounded by the host via D7), the tran 69 and not grounded by the host via D7), the transistor conducts and switches
70 the collector to zero, which is reflected on p 70 the collector to zero, which is reflected on pin 13 of the DB25 parport
71 connector. When SI/O is Low (driven by the LM 71 connector. When SI/O is Low (driven by the LM70 or the host) on the other
72 hand, the transistor is cut off and the voltag 72 hand, the transistor is cut off and the voltage tied to its collector is
73 reflected on pin 13 as a High level. 73 reflected on pin 13 as a High level.
74 74
75 So: the getmiso inline routine in this driver 75 So: the getmiso inline routine in this driver takes this fact into account,
76 inverting the value read at pin 13. 76 inverting the value read at pin 13.
77 77
78 78
79 Thanks to 79 Thanks to
80 --------- 80 ---------
81 81
82 - David Brownell for mentoring the SPI-side dr 82 - David Brownell for mentoring the SPI-side driver development.
83 - Dr.Craig Hollabaugh for the (early) "manual" 83 - Dr.Craig Hollabaugh for the (early) "manual" bitbanging driver version.
84 - Nadir Billimoria for help interpreting the c 84 - Nadir Billimoria for help interpreting the circuit schematic.
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