1 .. SPDX-License-Identifier: GPL-2.0 <<
2 <<
3 ======================= 1 =======================
4 Intel(R) Trace Hub (TH) 2 Intel(R) Trace Hub (TH)
5 ======================= 3 =======================
6 4
7 Overview 5 Overview
8 -------- 6 --------
9 7
10 Intel(R) Trace Hub (TH) is a set of hardware b 8 Intel(R) Trace Hub (TH) is a set of hardware blocks that produce,
11 switch and output trace data from multiple har 9 switch and output trace data from multiple hardware and software
12 sources over several types of trace output por 10 sources over several types of trace output ports encoded in System
13 Trace Protocol (MIPI STPv2) and is intended to 11 Trace Protocol (MIPI STPv2) and is intended to perform full system
14 debugging. For more information on the hardwar 12 debugging. For more information on the hardware, see Intel(R) Trace
15 Hub developer's manual [1]. 13 Hub developer's manual [1].
16 14
17 It consists of trace sources, trace destinatio 15 It consists of trace sources, trace destinations (outputs) and a
18 switch (Global Trace Hub, GTH). These devices 16 switch (Global Trace Hub, GTH). These devices are placed on a bus of
19 their own ("intel_th"), where they can be disc 17 their own ("intel_th"), where they can be discovered and configured
20 via sysfs attributes. 18 via sysfs attributes.
21 19
22 Currently, the following Intel TH subdevices ( 20 Currently, the following Intel TH subdevices (blocks) are supported:
23 - Software Trace Hub (STH), trace source, wh 21 - Software Trace Hub (STH), trace source, which is a System Trace
24 Module (STM) device, 22 Module (STM) device,
25 - Memory Storage Unit (MSU), trace output, w 23 - Memory Storage Unit (MSU), trace output, which allows storing
26 trace hub output in system memory, 24 trace hub output in system memory,
27 - Parallel Trace Interface output (PTI), tra 25 - Parallel Trace Interface output (PTI), trace output to an external
28 debug host via a PTI port, 26 debug host via a PTI port,
29 - Global Trace Hub (GTH), which is a switch 27 - Global Trace Hub (GTH), which is a switch and a central component
30 of Intel(R) Trace Hub architecture. 28 of Intel(R) Trace Hub architecture.
31 29
32 Common attributes for output devices are descr 30 Common attributes for output devices are described in
33 Documentation/ABI/testing/sysfs-bus-intel_th-o 31 Documentation/ABI/testing/sysfs-bus-intel_th-output-devices, the most
34 notable of them is "active", which enables or 32 notable of them is "active", which enables or disables trace output
35 into that particular output device. 33 into that particular output device.
36 34
37 GTH allows directing different STP masters int 35 GTH allows directing different STP masters into different output ports
38 via its "masters" attribute group. More detail 36 via its "masters" attribute group. More detailed GTH interface
39 description is at Documentation/ABI/testing/sy 37 description is at Documentation/ABI/testing/sysfs-bus-intel_th-devices-gth.
40 38
41 STH registers an stm class device, through whi 39 STH registers an stm class device, through which it provides interface
42 to userspace and kernelspace software trace so 40 to userspace and kernelspace software trace sources. See
43 Documentation/trace/stm.rst for more informati 41 Documentation/trace/stm.rst for more information on that.
44 42
45 MSU can be configured to collect trace data in 43 MSU can be configured to collect trace data into a system memory
46 buffer, which can later on be read from its de 44 buffer, which can later on be read from its device nodes via read() or
47 mmap() interface and directed to a "software s !! 45 mmap() interface.
48 consume the data and/or relay it further. <<
49 46
50 On the whole, Intel(R) Trace Hub does not requ 47 On the whole, Intel(R) Trace Hub does not require any special
51 userspace software to function; everything can 48 userspace software to function; everything can be configured, started
52 and collected via sysfs attributes, and device 49 and collected via sysfs attributes, and device nodes.
53 50
54 [1] https://software.intel.com/sites/default/f 51 [1] https://software.intel.com/sites/default/files/managed/d3/3c/intel-th-developer-manual.pdf
55 52
56 Bus and Subdevices 53 Bus and Subdevices
57 ------------------ 54 ------------------
58 55
59 For each Intel TH device in the system a bus o 56 For each Intel TH device in the system a bus of its own is
60 created and assigned an id number that reflect 57 created and assigned an id number that reflects the order in which TH
61 devices were enumerated. All TH subdevices (de !! 58 devices were emumerated. All TH subdevices (devices on intel_th bus)
62 begin with this id: 0-gth, 0-msc0, 0-msc1, 0-p 59 begin with this id: 0-gth, 0-msc0, 0-msc1, 0-pti, 0-sth, which is
63 followed by device's name and an optional inde 60 followed by device's name and an optional index.
64 61
65 Output devices also get a device node in /dev/ 62 Output devices also get a device node in /dev/intel_thN, where N is
66 the Intel TH device id. For example, MSU's mem 63 the Intel TH device id. For example, MSU's memory buffers, when
67 allocated, are accessible via /dev/intel_th0/m 64 allocated, are accessible via /dev/intel_th0/msc{0,1}.
68 65
69 Quick example 66 Quick example
70 ------------- 67 -------------
71 68
72 # figure out which GTH port is the first memor 69 # figure out which GTH port is the first memory controller::
73 70
74 $ cat /sys/bus/intel_th/devices/0-msc0 71 $ cat /sys/bus/intel_th/devices/0-msc0/port
75 0 72 0
76 73
77 # looks like it's port 0, configure master 33 74 # looks like it's port 0, configure master 33 to send data to port 0::
78 75
79 $ echo 0 > /sys/bus/intel_th/devices/0 76 $ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33
80 77
81 # allocate a 2-windowed multiblock buffer on t 78 # allocate a 2-windowed multiblock buffer on the first memory
82 # controller, each with 64 pages:: 79 # controller, each with 64 pages::
83 80
84 $ echo multi > /sys/bus/intel_th/devic 81 $ echo multi > /sys/bus/intel_th/devices/0-msc0/mode
85 $ echo 64,64 > /sys/bus/intel_th/devic 82 $ echo 64,64 > /sys/bus/intel_th/devices/0-msc0/nr_pages
86 83
87 # enable wrapping for this controller, too:: 84 # enable wrapping for this controller, too::
88 85
89 $ echo 1 > /sys/bus/intel_th/devices/0 86 $ echo 1 > /sys/bus/intel_th/devices/0-msc0/wrap
90 87
91 # and enable tracing into this port:: 88 # and enable tracing into this port::
92 89
93 $ echo 1 > /sys/bus/intel_th/devices/0 90 $ echo 1 > /sys/bus/intel_th/devices/0-msc0/active
94 91
95 # .. send data to master 33, see stm.txt for m 92 # .. send data to master 33, see stm.txt for more details ..
96 # .. wait for traces to pile up .. 93 # .. wait for traces to pile up ..
97 # .. and stop the trace:: 94 # .. and stop the trace::
98 95
99 $ echo 0 > /sys/bus/intel_th/devices/0 96 $ echo 0 > /sys/bus/intel_th/devices/0-msc0/active
100 97
101 # and now you can collect the trace from the d 98 # and now you can collect the trace from the device node::
102 99
103 $ cat /dev/intel_th0/msc0 > my_stp_tra 100 $ cat /dev/intel_th0/msc0 > my_stp_trace
104 101
105 Host Debugger Mode 102 Host Debugger Mode
106 ------------------ 103 ------------------
107 104
108 It is possible to configure the Trace Hub and 105 It is possible to configure the Trace Hub and control its trace
109 capture from a remote debug host, which should 106 capture from a remote debug host, which should be connected via one of
110 the hardware debugging interfaces, which will 107 the hardware debugging interfaces, which will then be used to both
111 control Intel Trace Hub and transfer its trace 108 control Intel Trace Hub and transfer its trace data to the debug host.
112 109
113 The driver needs to be told that such an arran 110 The driver needs to be told that such an arrangement is taking place
114 so that it does not touch any capture/port con 111 so that it does not touch any capture/port configuration and avoids
115 conflicting with the debug host's configuratio 112 conflicting with the debug host's configuration accesses. The only
116 activity that the driver will perform in this 113 activity that the driver will perform in this mode is collecting
117 software traces to the Software Trace Hub (an 114 software traces to the Software Trace Hub (an stm class device). The
118 user is still responsible for setting up adequ 115 user is still responsible for setting up adequate master/channel
119 mappings that the decoder on the receiving end 116 mappings that the decoder on the receiving end would recognize.
120 117
121 In order to enable the host mode, set the 'hos 118 In order to enable the host mode, set the 'host_mode' parameter of the
122 'intel_th' kernel module to 'y'. None of the v 119 'intel_th' kernel module to 'y'. None of the virtual output devices
123 will show up on the intel_th bus. Also, trace 120 will show up on the intel_th bus. Also, trace configuration and
124 capture controlling attribute groups of the 'g 121 capture controlling attribute groups of the 'gth' device will not be
125 exposed. The 'sth' device will operate as usua 122 exposed. The 'sth' device will operate as usual.
126 <<
127 Software Sinks <<
128 -------------- <<
129 <<
130 The Memory Storage Unit (MSU) driver provides <<
131 drivers to register themselves as software sin <<
132 Such drivers can further export the data via o <<
133 USB device controllers or network cards. <<
134 <<
135 The API has two main parts:: <<
136 - notifying the software sink that a particul <<
137 "locking" that window, that is, making it u <<
138 collection; when this happens, the MSU driv <<
139 switch to the next window in the buffer if <<
140 the trace capture if it's not; <<
141 - tracking the "locked" state of windows and <<
142 software sink driver to notify the MSU driv <<
143 unlocked and can be used again to collect t <<
144 <<
145 An example sink driver, msu-sink illustrates t <<
146 software sink. Functionally, it simply unlocks <<
147 are full, keeping the MSU running in a circula <<
148 "multi" mode, it will fill out all the windows <<
149 to just the first one. It can be enabled by wr <<
150 file (assuming msu-sink.ko is loaded). <<
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