1 .. SPDX-License-Identifier: GPL-2.0
2
3 =========================
4 MPIC interrupt controller
5 =========================
6
7 Device types supported:
8
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPI
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPI
11
12 Only one MPIC instance, of any type, may be in
13 MPIC will act as the system interrupt controll
14 vcpu's interrupt inputs.
15
16 Groups:
17 KVM_DEV_MPIC_GRP_MISC
18 Attributes:
19
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
21 Base address of the 256 KiB MPIC registe
22 naturally aligned. A value of zero disa
23 Reset value is zero.
24
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
26 Access an MPIC register, as if the access
27 "attr" is the byte offset into the MPIC re
28 must be 4-byte aligned.
29
30 MSIs may be signaled by using this attribu
31 to the relevant MSIIR.
32
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
34 IRQ input line for each standard openpic s
35 is active, regardless of interrupt sense.
36
37 For edge-triggered interrupts: Writing 1
38 edge, and writing 0 is ignored. Reading r
39 signaled edge has not been acknowledged, a
40
41 "attr" is the IRQ number. IRQ numbers for
42 byte offset of the relevant IVPR from EIVP
43
44 IRQ Routing:
45
46 The MPIC emulation supports IRQ routing. Onl
47 be instantiated. Once that device has been c
48 irqchip id 0.
49
50 This irqchip 0 has 256 interrupt pins, which
51 the main array of interrupt sources (a.k.a.
52
53 The numbering is the same as the MPIC device
54 the register offset from the beginning of th
55 regard to any subdivisions in chip documenta
56 or "external" interrupts.
57
58 Access to non-SRC interrupts is not implemen
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