1 .. SPDX-License-Identifier: GPL-2.0 1 .. SPDX-License-Identifier: GPL-2.0
2 2
3 ========================= 3 =========================
4 MPIC interrupt controller 4 MPIC interrupt controller
5 ========================= 5 =========================
6 6
7 Device types supported: 7 Device types supported:
8 8
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPI 9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPI 10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
11 11
12 Only one MPIC instance, of any type, may be in 12 Only one MPIC instance, of any type, may be instantiated. The created
13 MPIC will act as the system interrupt controll 13 MPIC will act as the system interrupt controller, connecting to each
14 vcpu's interrupt inputs. 14 vcpu's interrupt inputs.
15 15
16 Groups: 16 Groups:
17 KVM_DEV_MPIC_GRP_MISC 17 KVM_DEV_MPIC_GRP_MISC
18 Attributes: 18 Attributes:
19 19
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit) 20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
21 Base address of the 256 KiB MPIC registe 21 Base address of the 256 KiB MPIC register space. Must be
22 naturally aligned. A value of zero disa 22 naturally aligned. A value of zero disables the mapping.
23 Reset value is zero. 23 Reset value is zero.
24 24
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit) 25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
26 Access an MPIC register, as if the access 26 Access an MPIC register, as if the access were made from the guest.
27 "attr" is the byte offset into the MPIC re 27 "attr" is the byte offset into the MPIC register space. Accesses
28 must be 4-byte aligned. 28 must be 4-byte aligned.
29 29
30 MSIs may be signaled by using this attribu 30 MSIs may be signaled by using this attribute group to write
31 to the relevant MSIIR. 31 to the relevant MSIIR.
32 32
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit) 33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
34 IRQ input line for each standard openpic s 34 IRQ input line for each standard openpic source. 0 is inactive and 1
35 is active, regardless of interrupt sense. 35 is active, regardless of interrupt sense.
36 36
37 For edge-triggered interrupts: Writing 1 37 For edge-triggered interrupts: Writing 1 is considered an activating
38 edge, and writing 0 is ignored. Reading r 38 edge, and writing 0 is ignored. Reading returns 1 if a previously
39 signaled edge has not been acknowledged, a 39 signaled edge has not been acknowledged, and 0 otherwise.
40 40
41 "attr" is the IRQ number. IRQ numbers for 41 "attr" is the IRQ number. IRQ numbers for standard sources are the
42 byte offset of the relevant IVPR from EIVP 42 byte offset of the relevant IVPR from EIVPR0, divided by 32.
43 43
44 IRQ Routing: 44 IRQ Routing:
45 45
46 The MPIC emulation supports IRQ routing. Onl 46 The MPIC emulation supports IRQ routing. Only a single MPIC device can
47 be instantiated. Once that device has been c 47 be instantiated. Once that device has been created, it's available as
48 irqchip id 0. 48 irqchip id 0.
49 49
50 This irqchip 0 has 256 interrupt pins, which 50 This irqchip 0 has 256 interrupt pins, which expose the interrupts in
51 the main array of interrupt sources (a.k.a. 51 the main array of interrupt sources (a.k.a. "SRC" interrupts).
52 52
53 The numbering is the same as the MPIC device 53 The numbering is the same as the MPIC device tree binding -- based on
54 the register offset from the beginning of th 54 the register offset from the beginning of the sources array, without
55 regard to any subdivisions in chip documenta 55 regard to any subdivisions in chip documentation such as "internal"
56 or "external" interrupts. 56 or "external" interrupts.
57 57
58 Access to non-SRC interrupts is not implemen 58 Access to non-SRC interrupts is not implemented through IRQ routing mechanisms.
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