1 .. SPDX-License-Identifier: GPL-2.0 1 .. SPDX-License-Identifier: GPL-2.0
2 2
3 ================= 3 =================
4 KVM Lock Overview 4 KVM Lock Overview
5 ================= 5 =================
6 6
7 1. Acquisition Orders 7 1. Acquisition Orders
8 --------------------- 8 ---------------------
9 9
10 The acquisition orders for mutexes are as foll 10 The acquisition orders for mutexes are as follows:
11 11
12 - cpus_read_lock() is taken outside kvm_lock <<
13 <<
14 - kvm_usage_lock is taken outside cpus_read_lo <<
15 <<
16 - kvm->lock is taken outside vcpu->mutex 12 - kvm->lock is taken outside vcpu->mutex
17 13
18 - kvm->lock is taken outside kvm->slots_lock a 14 - kvm->lock is taken outside kvm->slots_lock and kvm->irq_lock
19 15
20 - kvm->slots_lock is taken outside kvm->irq_lo 16 - kvm->slots_lock is taken outside kvm->irq_lock, though acquiring
21 them together is quite rare. 17 them together is quite rare.
22 18
23 - kvm->mn_active_invalidate_count ensures that <<
24 invalidate_range_start() and invalidate_rang <<
25 use the same memslots array. kvm->slots_loc <<
26 are taken on the waiting side when modifying <<
27 must not take either kvm->slots_lock or kvm- <<
28 <<
29 cpus_read_lock() vs kvm_lock: <<
30 <<
31 - Taking cpus_read_lock() outside of kvm_lock <<
32 being the official ordering, as it is quite <<
33 cpus_read_lock() while holding kvm_lock. Us <<
34 e.g. avoid complex operations when possible. <<
35 <<
36 For SRCU: <<
37 <<
38 - ``synchronize_srcu(&kvm->srcu)`` is called i <<
39 for kvm->lock, vcpu->mutex and kvm->slots_lo <<
40 be taken inside a kvm->srcu read-side critic <<
41 following is broken:: <<
42 <<
43 srcu_read_lock(&kvm->srcu); <<
44 mutex_lock(&kvm->slots_lock); <<
45 <<
46 - kvm->slots_arch_lock instead is released bef <<
47 ``synchronize_srcu()``. It _can_ therefore <<
48 kvm->srcu read-side critical section, for ex <<
49 a vmexit. <<
50 <<
51 On x86: 19 On x86:
52 20
53 - vcpu->mutex is taken outside kvm->arch.hyper !! 21 - vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock
54 22
55 - kvm->arch.mmu_lock is an rwlock; critical se !! 23 - kvm->arch.mmu_lock is an rwlock. kvm->arch.tdp_mmu_pages_lock and
56 kvm->arch.tdp_mmu_pages_lock and kvm->arch.m !! 24 kvm->arch.mmu_unsync_pages_lock are taken inside kvm->arch.mmu_lock, and
57 also take kvm->arch.mmu_lock !! 25 cannot be taken without already holding kvm->arch.mmu_lock (typically with
>> 26 ``read_lock`` for the TDP MMU, thus the need for additional spinlocks).
58 27
59 Everything else is a leaf: no other lock is ta 28 Everything else is a leaf: no other lock is taken inside the critical
60 sections. 29 sections.
61 30
62 2. Exception 31 2. Exception
63 ------------ 32 ------------
64 33
65 Fast page fault: 34 Fast page fault:
66 35
67 Fast page fault is the fast path which fixes t 36 Fast page fault is the fast path which fixes the guest page fault out of
68 the mmu-lock on x86. Currently, the page fault 37 the mmu-lock on x86. Currently, the page fault can be fast in one of the
69 following two cases: 38 following two cases:
70 39
71 1. Access Tracking: The SPTE is not present, b 40 1. Access Tracking: The SPTE is not present, but it is marked for access
72 tracking. That means we need to restore the 41 tracking. That means we need to restore the saved R/X bits. This is
73 described in more detail later below. 42 described in more detail later below.
74 43
75 2. Write-Protection: The SPTE is present and t 44 2. Write-Protection: The SPTE is present and the fault is caused by
76 write-protect. That means we just need to c 45 write-protect. That means we just need to change the W bit of the spte.
77 46
78 What we use to avoid all the races is the Host !! 47 What we use to avoid all the race is the Host-writable bit and MMU-writable bit
79 on the spte: 48 on the spte:
80 49
81 - Host-writable means the gfn is writable in t 50 - Host-writable means the gfn is writable in the host kernel page tables and in
82 its KVM memslot. 51 its KVM memslot.
83 - MMU-writable means the gfn is writable in th 52 - MMU-writable means the gfn is writable in the guest's mmu and it is not
84 write-protected by shadow page write-protect 53 write-protected by shadow page write-protection.
85 54
86 On fast page fault path, we will use cmpxchg t 55 On fast page fault path, we will use cmpxchg to atomically set the spte W
87 bit if spte.HOST_WRITEABLE = 1 and spte.WRITE_ 56 bit if spte.HOST_WRITEABLE = 1 and spte.WRITE_PROTECT = 1, to restore the saved
88 R/X bits if for an access-traced spte, or both 57 R/X bits if for an access-traced spte, or both. This is safe because whenever
89 changing these bits can be detected by cmpxchg 58 changing these bits can be detected by cmpxchg.
90 59
91 But we need carefully check these cases: 60 But we need carefully check these cases:
92 61
93 1) The mapping from gfn to pfn 62 1) The mapping from gfn to pfn
94 63
95 The mapping from gfn to pfn may be changed sin 64 The mapping from gfn to pfn may be changed since we can only ensure the pfn
96 is not changed during cmpxchg. This is a ABA p 65 is not changed during cmpxchg. This is a ABA problem, for example, below case
97 will happen: 66 will happen:
98 67
99 +--------------------------------------------- 68 +------------------------------------------------------------------------+
100 | At the beginning:: 69 | At the beginning:: |
101 | 70 | |
102 | gpte = gfn1 71 | gpte = gfn1 |
103 | gfn1 is mapped to pfn1 on host 72 | gfn1 is mapped to pfn1 on host |
104 | spte is the shadow page table entry co 73 | spte is the shadow page table entry corresponding with gpte and |
105 | spte = pfn1 74 | spte = pfn1 |
106 +--------------------------------------------- 75 +------------------------------------------------------------------------+
107 | On fast page fault path: 76 | On fast page fault path: |
108 +------------------------------------+-------- 77 +------------------------------------+-----------------------------------+
109 | CPU 0: | CPU 1: 78 | CPU 0: | CPU 1: |
110 +------------------------------------+-------- 79 +------------------------------------+-----------------------------------+
111 | :: | 80 | :: | |
112 | | 81 | | |
113 | old_spte = *spte; | 82 | old_spte = *spte; | |
114 +------------------------------------+-------- 83 +------------------------------------+-----------------------------------+
115 | | pfn1 is 84 | | pfn1 is swapped out:: |
116 | | 85 | | |
117 | | spte 86 | | spte = 0; |
118 | | 87 | | |
119 | | pfn1 is 88 | | pfn1 is re-alloced for gfn2. |
120 | | 89 | | |
121 | | gpte is 90 | | gpte is changed to point to |
122 | | gfn2 by 91 | | gfn2 by the guest:: |
123 | | 92 | | |
124 | | spte 93 | | spte = pfn1; |
125 +------------------------------------+-------- 94 +------------------------------------+-----------------------------------+
126 | :: 95 | :: |
127 | 96 | |
128 | if (cmpxchg(spte, old_spte, old_spte+W) 97 | if (cmpxchg(spte, old_spte, old_spte+W) |
129 | mark_page_dirty(vcpu->kvm, gfn1) 98 | mark_page_dirty(vcpu->kvm, gfn1) |
130 | OOPS!!! 99 | OOPS!!! |
131 +--------------------------------------------- 100 +------------------------------------------------------------------------+
132 101
133 We dirty-log for gfn1, that means gfn2 is lost 102 We dirty-log for gfn1, that means gfn2 is lost in dirty-bitmap.
134 103
135 For direct sp, we can easily avoid it since th 104 For direct sp, we can easily avoid it since the spte of direct sp is fixed
136 to gfn. For indirect sp, we disabled fast pag 105 to gfn. For indirect sp, we disabled fast page fault for simplicity.
137 106
138 A solution for indirect sp could be to pin the 107 A solution for indirect sp could be to pin the gfn, for example via
139 gfn_to_pfn_memslot_atomic, before the cmpxchg. !! 108 kvm_vcpu_gfn_to_pfn_atomic, before the cmpxchg. After the pinning:
140 109
141 - We have held the refcount of pfn; that means !! 110 - We have held the refcount of pfn that means the pfn can not be freed and
142 be reused for another gfn. 111 be reused for another gfn.
143 - The pfn is writable and therefore it cannot 112 - The pfn is writable and therefore it cannot be shared between different gfns
144 by KSM. 113 by KSM.
145 114
146 Then, we can ensure the dirty bitmaps is corre 115 Then, we can ensure the dirty bitmaps is correctly set for a gfn.
147 116
148 2) Dirty bit tracking 117 2) Dirty bit tracking
149 118
150 In the origin code, the spte can be fast updat 119 In the origin code, the spte can be fast updated (non-atomically) if the
151 spte is read-only and the Accessed bit has alr 120 spte is read-only and the Accessed bit has already been set since the
152 Accessed bit and Dirty bit can not be lost. 121 Accessed bit and Dirty bit can not be lost.
153 122
154 But it is not true after fast page fault since 123 But it is not true after fast page fault since the spte can be marked
155 writable between reading spte and updating spt 124 writable between reading spte and updating spte. Like below case:
156 125
157 +--------------------------------------------- 126 +------------------------------------------------------------------------+
158 | At the beginning:: 127 | At the beginning:: |
159 | 128 | |
160 | spte.W = 0 129 | spte.W = 0 |
161 | spte.Accessed = 1 130 | spte.Accessed = 1 |
162 +------------------------------------+-------- 131 +------------------------------------+-----------------------------------+
163 | CPU 0: | CPU 1: 132 | CPU 0: | CPU 1: |
164 +------------------------------------+-------- 133 +------------------------------------+-----------------------------------+
165 | In mmu_spte_clear_track_bits():: | 134 | In mmu_spte_clear_track_bits():: | |
166 | | 135 | | |
167 | old_spte = *spte; | 136 | old_spte = *spte; | |
168 | | 137 | | |
169 | | 138 | | |
170 | /* 'if' condition is satisfied. */| 139 | /* 'if' condition is satisfied. */| |
171 | if (old_spte.Accessed == 1 && | 140 | if (old_spte.Accessed == 1 && | |
172 | old_spte.W == 0) | 141 | old_spte.W == 0) | |
173 | spte = 0ull; | 142 | spte = 0ull; | |
174 +------------------------------------+-------- 143 +------------------------------------+-----------------------------------+
175 | | on fast 144 | | on fast page fault path:: |
176 | | 145 | | |
177 | | spte 146 | | spte.W = 1 |
178 | | 147 | | |
179 | | memory 148 | | memory write on the spte:: |
180 | | 149 | | |
181 | | spte 150 | | spte.Dirty = 1 |
182 +------------------------------------+-------- 151 +------------------------------------+-----------------------------------+
183 | :: | 152 | :: | |
184 | | 153 | | |
185 | else | 154 | else | |
186 | old_spte = xchg(spte, 0ull) | 155 | old_spte = xchg(spte, 0ull) | |
187 | if (old_spte.Accessed == 1) | 156 | if (old_spte.Accessed == 1) | |
188 | kvm_set_pfn_accessed(spte.pfn);| 157 | kvm_set_pfn_accessed(spte.pfn);| |
189 | if (old_spte.Dirty == 1) | 158 | if (old_spte.Dirty == 1) | |
190 | kvm_set_pfn_dirty(spte.pfn); | 159 | kvm_set_pfn_dirty(spte.pfn); | |
191 | OOPS!!! | 160 | OOPS!!! | |
192 +------------------------------------+-------- 161 +------------------------------------+-----------------------------------+
193 162
194 The Dirty bit is lost in this case. 163 The Dirty bit is lost in this case.
195 164
196 In order to avoid this kind of issue, we alway 165 In order to avoid this kind of issue, we always treat the spte as "volatile"
197 if it can be updated out of mmu-lock [see spte !! 166 if it can be updated out of mmu-lock, see spte_has_volatile_bits(), it means,
198 the spte is always atomically updated in this 167 the spte is always atomically updated in this case.
199 168
200 3) flush tlbs due to spte updated 169 3) flush tlbs due to spte updated
201 170
202 If the spte is updated from writable to read-o !! 171 If the spte is updated from writable to readonly, we should flush all TLBs,
203 otherwise rmap_write_protect will find a read- 172 otherwise rmap_write_protect will find a read-only spte, even though the
204 writable spte might be cached on a CPU's TLB. 173 writable spte might be cached on a CPU's TLB.
205 174
206 As mentioned before, the spte can be updated t 175 As mentioned before, the spte can be updated to writable out of mmu-lock on
207 fast page fault path. In order to easily audit !! 176 fast page fault path, in order to easily audit the path, we see if TLBs need
208 to be flushed caused this reason in mmu_spte_u !! 177 be flushed caused by this reason in mmu_spte_update() since this is a common
209 function to update spte (present -> present). 178 function to update spte (present -> present).
210 179
211 Since the spte is "volatile" if it can be upda 180 Since the spte is "volatile" if it can be updated out of mmu-lock, we always
212 atomically update the spte and the race caused !! 181 atomically update the spte, the race caused by fast page fault can be avoided,
213 See the comments in spte_has_volatile_bits() a 182 See the comments in spte_has_volatile_bits() and mmu_spte_update().
214 183
215 Lockless Access Tracking: 184 Lockless Access Tracking:
216 185
217 This is used for Intel CPUs that are using EPT 186 This is used for Intel CPUs that are using EPT but do not support the EPT A/D
218 bits. In this case, PTEs are tagged as A/D dis 187 bits. In this case, PTEs are tagged as A/D disabled (using ignored bits), and
219 when the KVM MMU notifier is called to track a 188 when the KVM MMU notifier is called to track accesses to a page (via
220 kvm_mmu_notifier_clear_flush_young), it marks 189 kvm_mmu_notifier_clear_flush_young), it marks the PTE not-present in hardware
221 by clearing the RWX bits in the PTE and storin 190 by clearing the RWX bits in the PTE and storing the original R & X bits in more
222 unused/ignored bits. When the VM tries to acce 191 unused/ignored bits. When the VM tries to access the page later on, a fault is
223 generated and the fast page fault mechanism de 192 generated and the fast page fault mechanism described above is used to
224 atomically restore the PTE to a Present state. 193 atomically restore the PTE to a Present state. The W bit is not saved when the
225 PTE is marked for access tracking and during r 194 PTE is marked for access tracking and during restoration to the Present state,
226 the W bit is set depending on whether or not i 195 the W bit is set depending on whether or not it was a write access. If it
227 wasn't, then the W bit will remain clear until 196 wasn't, then the W bit will remain clear until a write access happens, at which
228 time it will be set using the Dirty tracking m 197 time it will be set using the Dirty tracking mechanism described above.
229 198
230 3. Reference 199 3. Reference
231 ------------ 200 ------------
232 201
233 ``kvm_lock`` !! 202 :Name: kvm_lock
234 ^^^^^^^^^^^^ <<
235 <<
236 :Type: mutex 203 :Type: mutex
237 :Arch: any 204 :Arch: any
238 :Protects: - vm_list 205 :Protects: - vm_list
239 206
240 ``kvm_usage_lock`` !! 207 :Name: kvm_count_lock
241 ^^^^^^^^^^^^^^^^^^ !! 208 :Type: raw_spinlock_t
242 <<
243 :Type: mutex <<
244 :Arch: any 209 :Arch: any
245 :Protects: - kvm_usage_count !! 210 :Protects: - hardware virtualization enable/disable
246 - hardware virtualization enab !! 211 :Comment: 'raw' because hardware enabling/disabling must be atomic /wrt
247 :Comment: Exists to allow taking cpus_re !! 212 migration.
248 protected, which simplifies th <<
249 <<
250 ``kvm->mn_invalidate_lock`` <<
251 ^^^^^^^^^^^^^^^^^^^^^^^^^^^ <<
252 <<
253 :Type: spinlock_t <<
254 :Arch: any <<
255 :Protects: mn_active_invalidate_count, mn <<
256 213
257 ``kvm_arch::tsc_write_lock`` !! 214 :Name: kvm_arch::tsc_write_lock
258 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ !! 215 :Type: raw_spinlock
259 <<
260 :Type: raw_spinlock_t <<
261 :Arch: x86 216 :Arch: x86
262 :Protects: - kvm_arch::{last_tsc_write,la 217 :Protects: - kvm_arch::{last_tsc_write,last_tsc_nsec,last_tsc_offset}
263 - tsc offset in vmcb 218 - tsc offset in vmcb
264 :Comment: 'raw' because updating the tsc 219 :Comment: 'raw' because updating the tsc offsets must not be preempted.
265 220
266 ``kvm->mmu_lock`` !! 221 :Name: kvm->mmu_lock
267 ^^^^^^^^^^^^^^^^^ !! 222 :Type: spinlock_t
268 :Type: spinlock_t or rwlock_t <<
269 :Arch: any 223 :Arch: any
270 :Protects: -shadow page/shadow tlb entry 224 :Protects: -shadow page/shadow tlb entry
271 :Comment: it is a spinlock since it is u 225 :Comment: it is a spinlock since it is used in mmu notifier.
272 226
273 ``kvm->srcu`` !! 227 :Name: kvm->srcu
274 ^^^^^^^^^^^^^ <<
275 :Type: srcu lock 228 :Type: srcu lock
276 :Arch: any 229 :Arch: any
277 :Protects: - kvm->memslots 230 :Protects: - kvm->memslots
278 - kvm->buses 231 - kvm->buses
279 :Comment: The srcu read lock must be hel 232 :Comment: The srcu read lock must be held while accessing memslots (e.g.
280 when using gfn_to_* functions) 233 when using gfn_to_* functions) and while accessing in-kernel
281 MMIO/PIO address->device struc 234 MMIO/PIO address->device structure mapping (kvm->buses).
282 The srcu index can be stored i 235 The srcu index can be stored in kvm_vcpu->srcu_idx per vcpu
283 if it is needed by multiple fu 236 if it is needed by multiple functions.
284 237
285 ``kvm->slots_arch_lock`` !! 238 :Name: blocked_vcpu_on_cpu_lock
286 ^^^^^^^^^^^^^^^^^^^^^^^^ <<
287 :Type: mutex <<
288 :Arch: any (only needed on x86 though <<
289 :Protects: any arch-specific fields of me <<
290 in a ``kvm->srcu`` read-side c <<
291 :Comment: must be held before reading th <<
292 until after all changes to the <<
293 <<
294 ``wakeup_vcpus_on_cpu_lock`` <<
295 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ <<
296 :Type: spinlock_t 239 :Type: spinlock_t
297 :Arch: x86 240 :Arch: x86
298 :Protects: wakeup_vcpus_on_cpu !! 241 :Protects: blocked_vcpu_on_cpu
299 :Comment: This is a per-CPU lock and it 242 :Comment: This is a per-CPU lock and it is used for VT-d posted-interrupts.
300 When VT-d posted-interrupts ar !! 243 When VT-d posted-interrupts is supported and the VM has assigned
301 devices, we put the blocked vC 244 devices, we put the blocked vCPU on the list blocked_vcpu_on_cpu
302 protected by blocked_vcpu_on_c !! 245 protected by blocked_vcpu_on_cpu_lock, when VT-d hardware issues
303 wakeup notification event sinc 246 wakeup notification event since external interrupts from the
304 assigned devices happens, we w 247 assigned devices happens, we will find the vCPU on the list to
305 wakeup. 248 wakeup.
306 <<
307 ``vendor_module_lock`` <<
308 ^^^^^^^^^^^^^^^^^^^^^^ <<
309 :Type: mutex <<
310 :Arch: x86 <<
311 :Protects: loading a vendor module (kvm_a <<
312 :Comment: Exists because using kvm_lock <<
313 in notifiers, e.g. __kvmclock_cpufreq_noti <<
314 cpu_hotplug_lock is held, e.g. from cpufre <<
315 operations need to take cpu_hotplug_lock w <<
316 updating static calls. <<
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