1 ======================== 1 ========================
2 Kernel driver w1_ds28e04 2 Kernel driver w1_ds28e04
3 ======================== 3 ========================
4 4
5 Supported chips: 5 Supported chips:
6 6
7 * Maxim DS28E04-100 4096-Bit Addressable 1-W 7 * Maxim DS28E04-100 4096-Bit Addressable 1-Wire EEPROM with PIO
8 8
9 supported family codes: 9 supported family codes:
10 10
11 ================= ==== 11 ================= ====
12 W1_FAMILY_DS28E04 0x1C 12 W1_FAMILY_DS28E04 0x1C
13 ================= ==== 13 ================= ====
14 14
15 Author: Markus Franke, <franke.m@sebakmt.com> < 15 Author: Markus Franke, <franke.m@sebakmt.com> <franm@hrz.tu-chemnitz.de>
16 16
17 Description 17 Description
18 ----------- 18 -----------
19 19
20 Support is provided through the sysfs files "e 20 Support is provided through the sysfs files "eeprom" and "pio". CRC checking
21 during memory accesses can optionally be enabl 21 during memory accesses can optionally be enabled/disabled via the device
22 attribute "crccheck". The strong pull-up can o 22 attribute "crccheck". The strong pull-up can optionally be enabled/disabled
23 via the module parameter "w1_strong_pullup". 23 via the module parameter "w1_strong_pullup".
24 24
25 Memory Access 25 Memory Access
26 26
27 A read operation on the "eeprom" file 27 A read operation on the "eeprom" file reads the given amount of bytes
28 from the EEPROM of the DS28E04. 28 from the EEPROM of the DS28E04.
29 29
30 A write operation on the "eeprom" file 30 A write operation on the "eeprom" file writes the given byte sequence
31 to the EEPROM of the DS28E04. If CRC c 31 to the EEPROM of the DS28E04. If CRC checking mode is enabled only
32 fully aligned blocks of 32 bytes with 32 fully aligned blocks of 32 bytes with valid CRC16 values (in bytes 30
33 and 31) are allowed to be written. 33 and 31) are allowed to be written.
34 34
35 PIO Access 35 PIO Access
36 36
37 The 2 PIOs of the DS28E04-100 are acce 37 The 2 PIOs of the DS28E04-100 are accessible via the "pio" sysfs file.
38 38
39 The current status of the PIO's is ret 39 The current status of the PIO's is returned as an 8 bit value. Bit 0/1
40 represent the state of PIO_0/PIO_1. Bi 40 represent the state of PIO_0/PIO_1. Bits 2..7 do not care. The PIO's are
41 driven low-active, i.e. the driver del 41 driven low-active, i.e. the driver delivers/expects low-active values.
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