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Linux/arch/alpha/lib/memset.S

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Diff markup

Differences between /arch/alpha/lib/memset.S (Version linux-6.11.5) and /arch/alpha/lib/memset.S (Version linux-3.10.108)


  1 /* SPDX-License-Identifier: GPL-2.0 */         << 
  2 /*                                                  1 /*
  3  * linux/arch/alpha/lib/memset.S                    2  * linux/arch/alpha/lib/memset.S
  4  *                                                  3  *
  5  * This is an efficient (and small) implementa      4  * This is an efficient (and small) implementation of the C library "memset()"
  6  * function for the alpha.                          5  * function for the alpha.
  7  *                                                  6  *
  8  *      (C) Copyright 1996 Linus Torvalds           7  *      (C) Copyright 1996 Linus Torvalds
  9  *                                                  8  *
 10  * This routine is "moral-ware": you are free       9  * This routine is "moral-ware": you are free to use it any way you wish, and
 11  * the only obligation I put on you is a moral     10  * the only obligation I put on you is a moral one: if you make any improvements
 12  * to the routine, please send me your improve     11  * to the routine, please send me your improvements for me to use similarly.
 13  *                                                 12  *
 14  * The scheduling comments are according to th     13  * The scheduling comments are according to the EV5 documentation (and done by 
 15  * hand, so they might well be incorrect, plea     14  * hand, so they might well be incorrect, please do tell me about it..)
 16  */                                                15  */
 17 #include <linux/export.h>                      !!  16 
 18         .set noat                                  17         .set noat
 19         .set noreorder                             18         .set noreorder
 20 .text                                              19 .text
 21         .globl memset                              20         .globl memset
 22         .globl __memset                            21         .globl __memset
 23         .globl ___memset                       !!  22         .globl __memsetw
 24         .globl __memset16                      << 
 25         .globl __constant_c_memset                 23         .globl __constant_c_memset
 26                                                !!  24         .ent __memset
 27         .ent ___memset                         << 
 28 .align 5                                           25 .align 5
 29 ___memset:                                     !!  26 __memset:
 30         .frame $30,0,$26,0                         27         .frame $30,0,$26,0
 31         .prologue 0                                28         .prologue 0
 32                                                    29 
 33         and $17,255,$1          /* E1 */           30         and $17,255,$1          /* E1 */
 34         insbl $17,1,$17         /* .. E0 */        31         insbl $17,1,$17         /* .. E0 */
 35         bis $17,$1,$17          /* E0 (p-c lat     32         bis $17,$1,$17          /* E0 (p-c latency, next cycle) */
 36         sll $17,16,$1           /* E1 (p-c lat     33         sll $17,16,$1           /* E1 (p-c latency, next cycle) */
 37                                                    34 
 38         bis $17,$1,$17          /* E0 (p-c lat     35         bis $17,$1,$17          /* E0 (p-c latency, next cycle) */
 39         sll $17,32,$1           /* E1 (p-c lat     36         sll $17,32,$1           /* E1 (p-c latency, next cycle) */
 40         bis $17,$1,$17          /* E0 (p-c lat     37         bis $17,$1,$17          /* E0 (p-c latency, next cycle) */
 41         ldq_u $31,0($30)        /* .. E1 */        38         ldq_u $31,0($30)        /* .. E1 */
 42                                                    39 
 43 .align 5                                           40 .align 5
 44 __constant_c_memset:                               41 __constant_c_memset:
 45         addq $18,$16,$6         /* E0 */           42         addq $18,$16,$6         /* E0 */
 46         bis $16,$16,$0          /* .. E1 */        43         bis $16,$16,$0          /* .. E1 */
 47         xor $16,$6,$1           /* E0 */           44         xor $16,$6,$1           /* E0 */
 48         ble $18,end             /* .. E1 */        45         ble $18,end             /* .. E1 */
 49                                                    46 
 50         bic $1,7,$1             /* E0 */           47         bic $1,7,$1             /* E0 */
 51         beq $1,within_one_quad  /* .. E1 (note     48         beq $1,within_one_quad  /* .. E1 (note EV5 zero-latency forwarding) */
 52         and $16,7,$3            /* E0 */           49         and $16,7,$3            /* E0 */
 53         beq $3,aligned          /* .. E1 (note     50         beq $3,aligned          /* .. E1 (note EV5 zero-latency forwarding) */
 54                                                    51 
 55         ldq_u $4,0($16)         /* E0 */           52         ldq_u $4,0($16)         /* E0 */
 56         bis $16,$16,$5          /* .. E1 */        53         bis $16,$16,$5          /* .. E1 */
 57         insql $17,$16,$2        /* E0 */           54         insql $17,$16,$2        /* E0 */
 58         subq $3,8,$3            /* .. E1 */        55         subq $3,8,$3            /* .. E1 */
 59                                                    56 
 60         addq $18,$3,$18         /* E0   $18 is     57         addq $18,$3,$18         /* E0   $18 is new count ($3 is negative) */
 61         mskql $4,$16,$4         /* .. E1 (and      58         mskql $4,$16,$4         /* .. E1 (and possible load stall) */
 62         subq $16,$3,$16         /* E0   $16 is     59         subq $16,$3,$16         /* E0   $16 is new aligned destination */
 63         bis $2,$4,$1            /* .. E1 */        60         bis $2,$4,$1            /* .. E1 */
 64                                                    61 
 65         bis $31,$31,$31         /* E0 */           62         bis $31,$31,$31         /* E0 */
 66         ldq_u $31,0($30)        /* .. E1 */        63         ldq_u $31,0($30)        /* .. E1 */
 67         stq_u $1,0($5)          /* E0 */           64         stq_u $1,0($5)          /* E0 */
 68         bis $31,$31,$31         /* .. E1 */        65         bis $31,$31,$31         /* .. E1 */
 69                                                    66 
 70 .align 4                                           67 .align 4
 71 aligned:                                           68 aligned:
 72         sra $18,3,$3            /* E0 */           69         sra $18,3,$3            /* E0 */
 73         and $18,7,$18           /* .. E1 */        70         and $18,7,$18           /* .. E1 */
 74         bis $16,$16,$5          /* E0 */           71         bis $16,$16,$5          /* E0 */
 75         beq $3,no_quad          /* .. E1 */        72         beq $3,no_quad          /* .. E1 */
 76                                                    73 
 77 .align 3                                           74 .align 3
 78 loop:                                              75 loop:
 79         stq $17,0($5)           /* E0 */           76         stq $17,0($5)           /* E0 */
 80         subq $3,1,$3            /* .. E1 */        77         subq $3,1,$3            /* .. E1 */
 81         addq $5,8,$5            /* E0 */           78         addq $5,8,$5            /* E0 */
 82         bne $3,loop             /* .. E1 */        79         bne $3,loop             /* .. E1 */
 83                                                    80 
 84 no_quad:                                           81 no_quad:
 85         bis $31,$31,$31         /* E0 */           82         bis $31,$31,$31         /* E0 */
 86         beq $18,end             /* .. E1 */        83         beq $18,end             /* .. E1 */
 87         ldq $7,0($5)            /* E0 */           84         ldq $7,0($5)            /* E0 */
 88         mskqh $7,$6,$2          /* .. E1 (and      85         mskqh $7,$6,$2          /* .. E1 (and load stall) */
 89                                                    86 
 90         insqh $17,$6,$4         /* E0 */           87         insqh $17,$6,$4         /* E0 */
 91         bis $2,$4,$1            /* .. E1 */        88         bis $2,$4,$1            /* .. E1 */
 92         stq $1,0($5)            /* E0 */           89         stq $1,0($5)            /* E0 */
 93         ret $31,($26),1         /* .. E1 */        90         ret $31,($26),1         /* .. E1 */
 94                                                    91 
 95 .align 3                                           92 .align 3
 96 within_one_quad:                                   93 within_one_quad:
 97         ldq_u $1,0($16)         /* E0 */           94         ldq_u $1,0($16)         /* E0 */
 98         insql $17,$16,$2        /* E1 */           95         insql $17,$16,$2        /* E1 */
 99         mskql $1,$16,$4         /* E0 (after l     96         mskql $1,$16,$4         /* E0 (after load stall) */
100         bis $2,$4,$2            /* E0 */           97         bis $2,$4,$2            /* E0 */
101                                                    98 
102         mskql $2,$6,$4          /* E0 */           99         mskql $2,$6,$4          /* E0 */
103         mskqh $1,$6,$2          /* .. E1 */       100         mskqh $1,$6,$2          /* .. E1 */
104         bis $2,$4,$1            /* E0 */          101         bis $2,$4,$1            /* E0 */
105         stq_u $1,0($16)         /* E0 */          102         stq_u $1,0($16)         /* E0 */
106                                                   103 
107 end:                                              104 end:
108         ret $31,($26),1         /* E1 */          105         ret $31,($26),1         /* E1 */
109         .end ___memset                         !! 106         .end __memset
110 EXPORT_SYMBOL(___memset)                       << 
111 EXPORT_SYMBOL(__constant_c_memset)             << 
112                                                   107 
113         .align 5                                  108         .align 5
114         .ent __memset16                        !! 109         .ent __memsetw
115 __memset16:                                    !! 110 __memsetw:
116         .prologue 0                               111         .prologue 0
117                                                   112 
118         inswl $17,0,$1          /* E0 */          113         inswl $17,0,$1          /* E0 */
119         inswl $17,2,$2          /* E0 */          114         inswl $17,2,$2          /* E0 */
120         inswl $17,4,$3          /* E0 */          115         inswl $17,4,$3          /* E0 */
121         or $1,$2,$1             /* .. E1 */       116         or $1,$2,$1             /* .. E1 */
122         inswl $17,6,$4          /* E0 */          117         inswl $17,6,$4          /* E0 */
123         or $1,$3,$1             /* .. E1 */       118         or $1,$3,$1             /* .. E1 */
124         or $1,$4,$17            /* E0 */          119         or $1,$4,$17            /* E0 */
125         br __constant_c_memset  /* .. E1 */       120         br __constant_c_memset  /* .. E1 */
126                                                   121 
127         .end __memset16                        !! 122         .end __memsetw
128 EXPORT_SYMBOL(__memset16)                      << 
129                                                   123 
130 memset = ___memset                             !! 124 memset = __memset
131 __memset = ___memset                           << 
132         EXPORT_SYMBOL(memset)                  << 
133         EXPORT_SYMBOL(__memset)                << 
                                                      

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