1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 /*
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.s
4 */
5
6 #ifndef __ASM_BARRIER_H
7 #define __ASM_BARRIER_H
8
9 #ifdef CONFIG_ISA_ARCV2
10
11 /*
12 * ARCv2 based HS38 cores are in-order issue,
13 * due to micro-arch buffering/queuing of load
14 *
15 * Explicit barrier provided by DMB instructio
16 * - Operand supports fine grained load/store
17 * - Ensures that selected memory operation i
18 * before any subsequent memory operation o
19 * - DMB guarantees SMP as well as local barr
20 * (asm-generic/barrier.h ensures sane smp_
21 * UP: barrier(), SMP: smp_*mb == *mb)
22 * - DSYNC provides DMB+completion_of_cache_b
23 * in the general case. Plus it only provid
24 */
25
26 #define mb() asm volatile("dmb 3\n" : : : "
27 #define rmb() asm volatile("dmb 1\n" : : : "
28 #define wmb() asm volatile("dmb 2\n" : : : "
29
30 #else
31
32 /*
33 * ARCompact based cores (ARC700) only have SY
34 * heavy weight as it flushes the pipeline as
35 * There are no real SMP implementations of su
36 */
37
38 #define mb() asm volatile("sync\n" : : : "m
39
40 #endif
41
42 #include <asm-generic/barrier.h>
43
44 #endif
45
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.