1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /* 1 /*
3 * ARC CPU startup Code !! 2 * This file is subject to the terms and conditions of the GNU General Public
>> 3 * License. See the file "COPYING" in the main directory of this archive
>> 4 * for more details.
4 * 5 *
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Sy !! 6 * Copyright (C) 1994, 1995 Waldorf Electronics
6 * !! 7 * Written by Ralf Baechle and Andreas Busse
7 * Vineetg: Dec 2007 !! 8 * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
8 * -Check if we are running on Simulator or o !! 9 * Copyright (C) 1996 Paul M. Antoine
9 * to skip certain things during boot on !! 10 * Modified for DECStation and hence R3000 support by Paul M. Antoine
>> 11 * Further modifications by David S. Miller and Harald Koerfgen
>> 12 * Copyright (C) 1999 Silicon Graphics, Inc.
>> 13 * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
>> 14 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
10 */ 15 */
>> 16 #include <linux/init.h>
>> 17 #include <linux/threads.h>
11 18
12 #include <linux/linkage.h> !! 19 #include <asm/addrspace.h>
13 #include <asm/asm-offsets.h> !! 20 #include <asm/asm.h>
14 #include <asm/entry.h> !! 21 #include <asm/asmmacro.h>
15 #include <asm/arcregs.h> <<
16 #include <asm/cache.h> <<
17 #include <asm/dsp-impl.h> <<
18 #include <asm/irqflags.h> 22 #include <asm/irqflags.h>
19 !! 23 #include <asm/regdef.h>
20 .macro CPU_EARLY_SETUP !! 24 #include <asm/pgtable-bits.h>
21 !! 25 #include <asm/mipsregs.h>
22 ; Setting up Vectror Table (in case ex !! 26 #include <asm/stackframe.h>
23 sr @_int_vec_base_lds, [AUX_INTR_ !! 27
24 !! 28 #include <kernel-entry-init.h>
25 ; Disable I-cache/D-cache if kernel so !! 29
26 lr r5, [ARC_REG_IC_BCR] !! 30 /*
27 breq r5, 0, 1f ; I$ d !! 31 * For the moment disable interrupts, mark the kernel mode and
28 lr r5, [ARC_REG_IC_CTRL] !! 32 * set ST0_KX so that the CPU does not spit fire when using
29 #ifdef CONFIG_ARC_HAS_ICACHE !! 33 * 64-bit addresses. A full initialization of the CPU's status
30 bclr r5, r5, 0 ; 0 - !! 34 * register is done later in per_cpu_trap_init().
>> 35 */
>> 36 .macro setup_c0_status set clr
>> 37 .set push
>> 38 mfc0 t0, CP0_STATUS
>> 39 or t0, ST0_CU0|\set|0x1f|\clr
>> 40 xor t0, 0x1f|\clr
>> 41 mtc0 t0, CP0_STATUS
>> 42 .set noreorder
>> 43 sll zero,3 # ehb
>> 44 .set pop
>> 45 .endm
>> 46
>> 47 .macro setup_c0_status_pri
>> 48 #ifdef CONFIG_64BIT
>> 49 setup_c0_status ST0_KX 0
31 #else 50 #else
32 bset r5, r5, 0 ; I$ e !! 51 setup_c0_status 0 0
33 #endif 52 #endif
34 sr r5, [ARC_REG_IC_CTRL] !! 53 .endm
35 54
36 1: !! 55 .macro setup_c0_status_sec
37 lr r5, [ARC_REG_DC_BCR] !! 56 #ifdef CONFIG_64BIT
38 breq r5, 0, 1f ; D$ d !! 57 setup_c0_status ST0_KX ST0_BEV
39 lr r5, [ARC_REG_DC_CTRL] <<
40 bclr r5, r5, 6 ; Inva <<
41 #ifdef CONFIG_ARC_HAS_DCACHE <<
42 bclr r5, r5, 0 ; Enab <<
43 #else 58 #else
44 bset r5, r5, 0 ; Disa !! 59 setup_c0_status 0 ST0_BEV
45 #endif 60 #endif
46 sr r5, [ARC_REG_DC_CTRL] !! 61 .endm
47 <<
48 1: <<
49 62
50 #ifdef CONFIG_ISA_ARCV2 !! 63 #ifndef CONFIG_NO_EXCEPT_FILL
51 ; Unaligned access is disabled at rese !! 64 /*
52 ; gcc 7.3.1 (ARC GNU 2018.03) onwards !! 65 * Reserved space for exception handlers.
53 ; by default !! 66 * Necessary for machines which link their kernels at KSEG0.
54 lr r5, [status32] !! 67 */
55 #ifdef CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS !! 68 .fill 0x400
56 bset r5, r5, STATUS_AD_BIT <<
57 #else <<
58 ; Although disabled at reset, bootload <<
59 bclr r5, r5, STATUS_AD_BIT <<
60 #endif 69 #endif
61 kflag r5 <<
62 70
63 #ifdef CONFIG_ARC_LPB_DISABLE !! 71 EXPORT(_stext)
64 lr r5, [ARC_REG_LPB_BUILD] <<
65 breq r5, 0, 1f ; LPB <<
66 mov r5, 1 <<
67 sr r5, [ARC_REG_LPB_CTRL] <<
68 1: <<
69 #endif /* CONFIG_ARC_LPB_DISABLE */ <<
70 72
71 /* On HSDK, CCMs need to remapped supe !! 73 #ifdef CONFIG_BOOT_RAW
72 #ifdef CONFIG_ARC_SOC_HSDK !! 74 /*
73 mov r6, 0x60000000 !! 75 * Give us a fighting chance of running if execution beings at the
74 lr r5, [ARC_REG_ICCM_BUILD] !! 76 * kernel load address. This is needed because this platform does
75 breq r5, 0, 1f !! 77 * not have a ELF loader yet.
76 sr r6, [ARC_REG_AUX_ICCM] !! 78 */
77 1: !! 79 FEXPORT(__kernel_entry)
78 lr r5, [ARC_REG_DCCM_BUILD] !! 80 j kernel_entry
79 breq r5, 0, 2f !! 81 #endif
80 sr r6, [ARC_REG_AUX_DCCM] <<
81 2: <<
82 #endif /* CONFIG_ARC_SOC_HSDK */ <<
83 <<
84 #endif /* CONFIG_ISA_ARCV2 */ <<
85 <<
86 ; Config DSP_CTRL properly, so kernel <<
87 ; multiply-accumulate, and divide oper <<
88 DSP_EARLY_INIT <<
89 .endm <<
90 <<
91 .section .init.text, "ax",@progbits <<
92 <<
93 ;--------------------------------------------- <<
94 ; Default Reset Handler (jumped into from Rese <<
95 ; - Don't clobber r0,r1,r2 as they might have <<
96 ; - Platforms can override this weak version i <<
97 ;--------------------------------------------- <<
98 WEAK(res_service) <<
99 j stext <<
100 END(res_service) <<
101 <<
102 ;--------------------------------------------- <<
103 ; Kernel Entry point <<
104 ;--------------------------------------------- <<
105 ENTRY(stext) <<
106 82
107 CPU_EARLY_SETUP !! 83 __REF
108 84
109 #ifdef CONFIG_SMP !! 85 NESTED(kernel_entry, 16, sp) # kernel entry point
110 GET_CPU_ID r5 <<
111 cmp r5, 0 <<
112 mov.nz r0, r5 <<
113 bz .Lmaster_proceed <<
114 <<
115 ; Non-Masters wait for Master to boot <<
116 ; when they resume, tail-call to entry <<
117 mov blink, @first_lines_of_seconda <<
118 j arc_platform_smp_wait_to_boot <<
119 <<
120 .Lmaster_proceed: <<
121 #endif <<
122 <<
123 ; Clear BSS before updating any global <<
124 ; XXX: use ZOL here <<
125 mov r5, __bss_start <<
126 sub r6, __bss_stop, r5 <<
127 lsr.f lp_count, r6, 2 <<
128 lpnz 1f <<
129 st.ab 0, [r5, 4] <<
130 1: <<
131 <<
132 ; Uboot - kernel ABI <<
133 ; r0 = [0] No uboot interaction, [1 <<
134 ; r1 = magic number (always zero as <<
135 ; r2 = pointer to uboot provided cm <<
136 ; These are handled later in handle_ub <<
137 st r0, [@uboot_tag] <<
138 st r1, [@uboot_magic] <<
139 st r2, [@uboot_arg] <<
140 <<
141 ; setup "current" tsk and optionally c <<
142 mov r9, @init_task <<
143 SET_CURR_TASK_ON_CPU r9, r0 ; r9 = <<
144 86
145 ; setup stack (fp, sp) !! 87 kernel_entry_setup # cpu specific setup
146 mov fp, 0 <<
147 88
148 ; tsk->thread_info is really a PAGE, w !! 89 setup_c0_status_pri
149 GET_TSK_STACK_BASE r9, sp ; r9 = <<
150 90
151 j start_kernel ; "C" entry po !! 91 /* We might not get launched at the address the kernel is linked to,
152 END(stext) !! 92 so we jump there. */
>> 93 PTR_LA t0, 0f
>> 94 jr t0
>> 95 0:
153 96
154 #ifdef CONFIG_SMP !! 97 #ifdef CONFIG_MIPS_RAW_APPENDED_DTB
155 ;--------------------------------------------- !! 98 PTR_LA t0, __appended_dtb
156 ; First lines of code run by secondary bef <<
157 ;--------------------------------------------- <<
158 .section .text, "ax",@progbits <<
159 ENTRY(first_lines_of_secondary) <<
160 <<
161 ; setup per-cpu idle task as "current" <<
162 ld r0, [@secondary_idle_tsk] <<
163 SET_CURR_TASK_ON_CPU r0, r1 <<
164 99
165 ; setup stack (fp, sp) !! 100 #ifdef CONFIG_CPU_BIG_ENDIAN
166 mov fp, 0 !! 101 li t1, 0xd00dfeed
>> 102 #else
>> 103 li t1, 0xedfe0dd0
>> 104 #endif
>> 105 lw t2, (t0)
>> 106 bne t1, t2, not_found
>> 107 nop
>> 108
>> 109 move a1, t0
>> 110 PTR_LI a0, -2
>> 111 not_found:
>> 112 #endif
>> 113 PTR_LA t0, __bss_start # clear .bss
>> 114 LONG_S zero, (t0)
>> 115 PTR_LA t1, __bss_stop - LONGSIZE
>> 116 1:
>> 117 PTR_ADDIU t0, LONGSIZE
>> 118 LONG_S zero, (t0)
>> 119 bne t0, t1, 1b
>> 120
>> 121 LONG_S a0, fw_arg0 # firmware arguments
>> 122 LONG_S a1, fw_arg1
>> 123 LONG_S a2, fw_arg2
>> 124 LONG_S a3, fw_arg3
>> 125
>> 126 MTC0 zero, CP0_CONTEXT # clear context register
>> 127 PTR_LA $28, init_thread_union
>> 128 /* Set the SP after an empty pt_regs. */
>> 129 PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
>> 130 PTR_ADDU sp, $28
>> 131 back_to_back_c0_hazard
>> 132 set_saved_sp sp, t0, t1
>> 133 PTR_SUBU sp, 4 * SZREG # init stack pointer
167 134
168 ; set its stack base to tsk->thread_in !! 135 j start_kernel
169 GET_TSK_STACK_BASE r0, sp !! 136 END(kernel_entry)
170 137
171 j start_kernel_secondary !! 138 #ifdef CONFIG_SMP
172 END(first_lines_of_secondary) !! 139 /*
173 #endif !! 140 * SMP slave cpus entry point. Board specific code for bootstrap calls this
>> 141 * function after setting up the stack and gp registers.
>> 142 */
>> 143 NESTED(smp_bootstrap, 16, sp)
>> 144 smp_slave_setup
>> 145 setup_c0_status_sec
>> 146 j start_secondary
>> 147 END(smp_bootstrap)
>> 148 #endif /* CONFIG_SMP */
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